MEMORY COMPONENTS
xa-out <= xb-out <= e l s e -- a=b xa-out <= xb-out <=
15
(others=>’O’); data-in;
(others=>’O’); (others=>’O’);
end i f ; end p r o c e s s ;
30
--
with
default
output
signal
assignment
__
p r o c e s s ( a ,b , d a t a - i n ) begin ya-out <= ( o t h e r s = > ’ O ’ ) ; yb-out <= ( o t h e r s = > ’ O ’ ) ; i f a > b then
3s
ya-out
10
<= d a t a - i n ;
e l s i f a < b then yb-out <= d a t a - i n ; end i f ; end p r o c e s s ; IS
end a r c h ;
MEMORY COMPONENTS
A.3 A.3.1
Register template Listing A.8 Register template
5
library ieee; use ieee.std-logic-ll64.all; e n t i t y reg-template i s port ( clk, reset: in std-logic; e n : in std-logic; qi-next , q z - n e x t , q3-next : i n s t d - l o g i c - v e c t o r ( 7 downto 0 ) ; ql-reg , q 2 _ r e g , q 3 - r e g : o u t s t d - l o g i c - v e c t o r ( 7 downto 0 )
10
);
end r e g - t e m p l a t e ;
15
architecture begin
a r c h of r e g - t e m p l a t e
is
__ __ __ 20
register
without
reset
p r o c e s s (clk) begin i f ( c l k ’ e v e n t and c l k = ’ l ’ ) t h e n ql-reg
end i f ;
<= q l - n e x t ;
425