DPS-FPGA 2008-2009 Resource Guide by kwitte

V o l u m e N u m b e r

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FEATURES

COLUMNS

Tightly coupling FPGAs with x86 processors By Peter Carlston, Intel, and Geno Valente, XtremeData, Inc.

Pumping CD-quality stereo audio over digital networks in real-time By David Trainor, APT

Dynamically reconfigurable Massively Parallel Processor Arrays in high-performance embedded military systems By Mike Butts and Paul Chen, Ambric

Easing the integration headaches of FPGAs into heterogeneous embedded systems

Migrating PowerPC to FPGAs: New C-to-hardware tools renew PowerPC applications By David Pellerin, Impulse Accelerated Technologies, and Dan Isaacs, Xilinx, Inc.

Two competitive FPGA methodologies for run-time reconfiguration By J. Ryan Kenny, Altera Corporation, and David Rupe, BittWare, Inc.

Modeling C applications in UML with files and structures By Martin Bakal and Jeffrey Cohen, Telelogic

DEPARTMENTS 6, 16, 28, 35, 78 Editor’s Choice Products By Chris A. Ciufo

RESOURCE GUIDE 37

Profile Index Categories: 38 DSP based carrier boards 38 DSP chips and cores 39 DSP resource boards 47 FPGA 63 Hardware 73 Services 74 Software 77 Software-Defined Radio

Altera: Altera’s 40nm Stratix IV FPGAs: Highest density, highest performance, lowest power FPGAs available

2008-09 Annual Resource Guide

Everything you ever wanted to know about the cellular chip market By Will Strauss

ON THE COVER:

Published by:

ADI’s Blackfin says “no” to multicore By Chris A. Ciufo

9 Forward Thinking

By Mark Littlefield, Curtis-Wright Controls Embedded Computing

8 Editor’s Insight

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Xilinx: Xilinx® Virtex®-5 FPGAs: One family, five domain optimized FPGA platforms deliver the ultimate in system integration

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A “C Change” – from Linux to FPGAs and Processors We’re having that nirvana-like dream where one imagines programming FPGAs in a high-level language such as C and not having to deal with any of that semiconductor stuff. A fantasy? Not according to Impulse Accelerated Technologies, who asserts that its software-to-FPGA tools now work with BlueCat Linux from LynuxWorks. According to the company, the Impulse C-to-FPGA tools enable software developers to write C algorithms and easily “refactor them for parallel processing on an FPGA.” The companies claim a 10 – 100x performance increase in image, signal, and data processing algorithms. The concept here is three-fold: program in C (thank heavens!), do some load balancing across parallel resources, and provide hooks into Linux. The tool allows using C-language directly into optimized logic ready for use with popular FPGA devices. Developers can rapidly prototype mixed software/hardware systems and perform design iterations in just minutes or hours, instead of days or weeks. The Impulse CoDeveloper is essentially a C-based hardware accelerator that targets Xilinx APU and FSL interfaces with only a minimal rewrite between targets. There’s C-language compilation, optimization, and FPGA hardware generation. Also included are targets for Xilinx PowerPC and MicroBlaze processors, as well as the relevant interconnects. As well, the tools take advantage of LynuxWorks’ BlueCat port to the Xilinx processors, essentially allowing a developer to work in C, create FPGA logic, and also program the FPGA’s processors. Yes, indeed. Several steps closer to FPGA nirvana.

Impulse Accelerated Technologies • www.impulsec.com • RSC# 39361 6

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Editor’sInsight

ADI’s Blackfin says “no” to multicore

h, yes. The Digital Media Age. It’s changing everything, to the extent of requiring MP3 codecs and H.264 video decoders in cell phones and dashboard GPS nav systems. Backup car cameras and collision avoidance systems add more processing in the cabin than on some people’s desktops. Even the high-end Harmony universal remote controller’s processing horsepower rivals some PDAs from 2007. Companies like Intel call the multimedia revolution an “always on” connectivity – the Fourth Wave of the Internet. DSP expert Analog Devices (ADI) calls this convergent processing and has introduced the latest generation of the venerable single-point processing Blackfin family just in time to target these trends. But interestingly, ADI’s new System-on-Chip (SoC) devices focus on single-core processing surrounded by lots of intelligent peripherals. Is this ignoring the obvious multicore trend? Are these designs a bit too Year 2007? Maybe not. While FPGAs and their flexible parallelism can out-muscle the best general-purpose DSPs from Texas Instruments or Analog Devices, SoCs still run circles around an FPGA in purpose-built systems. In consumer-quality doodads such as handhelds streaming video over Wi-Fi, or VoIP telephones and infrastructure, Internet connectivity added to media processing with all-day battery life or passive cooling pretty much mandates a certain class of DSP plus MCU device that doesn’t spell F-P-G-A. That’s because no programmable sea of gates from Actel, Altera, Lattice, QuickLogic, Xilinx, or anyone else can match the svelte footprint, ease of programming, low cost, and low power of a DSP-enabled SoC from Analog Devices or Texas Instruments. ADI’s new catch phrase for the company’s latest Blackfin processors pinpoints these attributes even further: “Convergent Processing Performance at Low Power.” Analog Devices’ and their partners’ strategy is moving from the signal processing realm into the decision-making processor and peripheral arena. The Blackfin BF51x Family will be announced around the time you read this, and we were lucky enough to get a sneak preview of four devices. In a nutshell, a 400 MHz fixed-point SIMD Blackfin core is bolted to a host of peripherals designed to target certain low-power markets and applications. From audio and video boxes in your living room in the Digital Home, to portable multimedia Mobile, and onward to the company’s bread-and-butter Industrial & Instrumentation and Automotive segments, the 51x series emphasizes signal processing grunt in converged applications. Moreover, ADI is emphasizing low power and low price as key differentiators – how does under $5 sound? The company argues that one processor, not two, is best for tackling multimode connectivity, DSP, and embedded control. Power management, one tool chain, one memory subsystem, 8

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By Chris A.Ciufo, Editor

and a single instruction set are much easier to design with and optimize than a heterogeneous CPU plus coprocessor. (Could they be throwing rocks at the TI OMAP approach?1). Available in four tasty flavors, the BF512 and 514 surround a 90 nm geometry BF core with an LCD controller, I2C, SPI, UARTs, 40 GPIOs, SPORTs, PWM, and SDIO/CE-ATA (on the 514 only). From a block diagram perspective, this list of acronyms breaks down to the core, memory subsystem, a bunch of very flexible I/O, and even an optional stacked flash or mixed signal analog I/O (via a multichip module package). The higher-end devices are the BF516 and 518, which add an Ethernet MAC for wired connectivity. (The SDIO/CE-ATA interface can be used for flash storage cards and also for SDIO Wi-Fi or 3G cellular wireless I/O.) Interestingly, the 518 also adds IEEE-1588v2, which facilitates a synchronized networked timing protocol over Ethernet used in some measurement and control systems. ADI’s not stupid: This digital convergence is one thing, but the company’s history is in the automotive, industrial/military, and instrumentation markets. Equally interesting is that the devices are all optimized for always-on power sipping. According to company data (which they reprinted with permission from EE Times and DSP DesignLine), the BF516 consumes a mere 16.5 mW at 60 MHz versus 18 mW in TI’s C550x. Crank up the clock to 100 MHz and power is 24 mW versus 46 mW. Even better, that’s 200 MMACs or 8.5 MMAC/mW versus only 4.3 in TI’s C550x. So ADI knows where it wants to go with these four new Blackfins: fixed-point single-core DSP/RISC performance with lots o’ peripherals that use very little power. That’s all very nice, but the world is going multicore crazy. Desktop heavyweights AMD and Intel are all the way up to four cores with eight on the way. Already Intel is back in the SoC convergent multimedia game with their Canmore Media Processor CE 3100. Though it’s a single-core Pentium M device, how hard could it be to add a Core 2 Duo? At the other end of the scale, Intel’s single-core Atom Z500 consumes a mere 65 mW and costs only $20 at 1KU. The company has stated it wants to take on ARM in low-power Mobile Internet Devices (MIDs), and rumors abound of a dual-core 1.87 GHz Atom 230. It doesn’t seem a big stretch to me that within the next 12-18 months Intel will surround a low-power, dual-core Atom with a bunch of Blackfin-like peripherals – providing some competition for these new BF51x devices. Should ADI be worried about multicore or Intel? Maybe. While Intel’s migrating down the curve from desktop terrain into signal processing plus peripherals, ADI is moving up the curve from DSP into MCU plus peripherals. For now, Blackfins are cheaper ($5 at 25KU versus Atom $20 at 1KU), more integrated, and use a heck-of-a lot less power. I think there’s nothing to fear from multicore right now. But I wouldn’t take my eye off either TI or Intel just yet. Maybe that’s why ADI’s roadmap has a dual-core Blackfin past the existing BF561. 1

Hey, we’re not anti-TI. Check out the Editor’s Choice award we just gave to TI’s new OMAP floating point multicore processors on page 78.

ForwardThinking

Everything you ever wanted to know about the cellular chip market By WillStrauss

here’s a new in-depth study of the worldwide cell phone market and virtually all of the chips in them. The 564-page study entitled, “Cellular Handset & Chip Markets ’08,” gauges the performance of the top 38 handset vendors and ranks their 2007 market shares. The survey provides detailed forecasts by technology and global region through 2012 of handsets, subscribers, and cellular handset chips of all types. There are market forecasts for virtually all cell phone integrated circuits, including digital basebands, RF transceivers and PAs, application processors, graphics and other coprocessors, imagers, LCD drivers, touch-screen controllers, memories, and chips for all the new functions being added to cell phones. In addition, the report provides estimates of the market shares of cell phone vendors by air technology (GSM, GPRS, EDGE, CDMA2000 1xEV, 1xEV-DO, WCDMA, HSPA, and PHS/PDC/iDEN/TDMA). Even ultra-low-cost cell phones are forecast by air interface. Importantly, the study estimates market shares of chip vendors for every chip type and for every applicable air technology. Market metrics are the central focus of the study, but a key finding is that cell phone unit market growth is slowing globally in 2008. For instance:

n Japan’s growth turns negative at 3.4 percent n North America slows to 7.8 percent growth n Europe slows to only 3.8 percent In spite of a slowing economy, Europe continues to be the fastest growing market for WCDMA in 2008, outpacing North America. China and India continue to be the volume cell phone drivers, with the smaller markets of Africa and the Middle East experiencing far higher growth rates. Another finding is that HSPA air technology is emerging strong in 2008 and will begin displacing WCDMA. HSDPA.EDGE markets will continue to grow in spite of the excitement in 3G. Next-generation eEDGE will match first-generation WCDMA data rates at a much lower operator capital expense. The demand for voice-only, ultra-low-cost GSM/GPRS and CDMA2000 1x cell phones are growing rapidly and will dominate market volumes in emerging countries.

Over the next five years, the fast-growing Smart phone markets are driving the introduction of single-chip peripherals that support Wi-Fi, Bluetooth, GPS, FM radio, and even mobile TV. As the market for wireless payments expands, the demand for NFC radio and cell phone fingerprint sensors is also growing. Qualcomm’s MediaFLO has achieved dominance in the US mobile TV market, but Japan leads the market with ISDB-T followed by South Korea with T-DMB. Another conclusion that comes out of this study is that the global fragmentation of mobile TV standards will lead the demand for multi-standard single-chip mobile TV receivers. Also, touchscreen controller growth is driven by the huge success of Apple’s multi-touch iPhone. Multi-touch screens are forecasted to eventually displace single-touch ones. The mainstream cell phone camera market is migrating to 2 megapixels in 2008, as 3 megapixel (MP) volumes disappointed suppliers in 2007. However, with autofocus becoming a standard feature, expect new 3-MP phones to see stronger 2009 growth. Application processor competition is heating up as the demand for increasing video and Web functionality grows with 3G’s higher data rates. Qualcomm and Texas Instruments continue to dominate the cell phone chip market, but with new peripherals being added, there are opportunities for other vendors to target new chip types to get their piece of the market. Carter L. Horney, one of the main authors of the study asserts: “The cell phone continues to be the physical and market magnet that is pulling in the functionality of digital cameras, PDAs, MP3 players, GPS navigators, Bluetooth, FM Radio, mobile TV, cordless phones, Smart cards, and even fingerprint sensors, and is quickly becoming the dominant market for each and all of these functions.” “Cellular Handset & Chip Markets ’08” is available from the Forward Concepts website at www.fwdconcepts.com/cell8.htm.

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2008-09 Annual Resource Guide

Tightly coupling FPGAs

This article highlights the benefits of Acceleration Abstraction Layers and discusses how military systems designers can now leverage a new class of COTS board and accelerator modules to solve some of their most demanding tasks.

x86

with

adar, cryptography, and Software Defined Radio (SDR) applications can often benefit from being run on FPGAs tightly coupled with multicore, general-purpose processors. But until now, makers of FPGA devices have had to develop proprietary accelerator middleware so that platform-level services would be accessible from their products. This adds cost to In-Socket accelerator products and may lock application software into specific accelerators, or even specific accelerator generations. Intel QuickAssist Technology includes both third-party In-Socket Accelerator (ISA) FPGA modules and an Acceleration Abstraction Layer (AAL) developed by Intel. AAL provides a consistent interface for application software so that underlying accelerator and general-purpose processor hardware can evolve independently and application software can more easily scale.

processors

Uncovering the Issues of both GPP and FPGA

Radar, cryptography, SDR, and real-time surveillance video processing are examples of military applications whose workloads are highly parallel. Over the years many solutions have been deployed that run on COTS general-purpose processor (GPP) blades. Using general-purpose processors rather than specialized hardware accelerators are cost-effective since software is typically easier to develop, can scale from small to large systems, and can be easily ported to new processor generations. Using GPPs to do all the processing may not be the most effective approach, especially when a platform’s Size, Weight, and Power (SWaP) are constrained, or when extremely high-performance at high-efficiency are required.

FPGAs and GPPs: a good couple? By PeterCarlston

FPGAs require less power than GPPs of similar signal processing performance. Power savings is obviously important for UAVs, for example, where lightweight power and cooling systems can translate directly into larger fuel tanks that enable the craft to fly further and faster. Real-time performance is another key parameter, as when a system is trying to track a moving target. FPGA accelerators can process some classes of signal and image processing algorithms faster than GPPs, which decreases the time to compute and can help save lives.

and

GenoValente

FPGAs, however, don’t excel at every type of processing that modern integrated systems must handle. Many military applications have been designed to run on hybrid systems with tightly coupled GPPs and FPGAs. But developing such customized GPP plus FPGA boards is time-consuming and expensive. It can take six months or longer to design and build a complex custom PCB containing processor(s), FPGA(s), memory, interfaces, and other components. Issues uncovered during hardware validation may require “blue wires.” So boards may need to be re-spun, which adds cost and delay. Even after a new board boots correctly, application code developers must wait until communication mechanisms are designed, built, and debugged so that their application software will interface to the board hardware. This communication layer adds to the cost of developing new accelerator technology. It also locks in application software to the specific communication mechanism used on a specific board design. Software may need to be substantially changed when board design changes or even when new versions of accelerators are released. This leaves such non-COTS-based solutions in a vulnerable state. EOL issues can happen at any time, even with major components, as the recent, unexpected removal of PA Semi and their future products demonstrates. Just as bad is that processor and FPGA technology is evolving so quickly that a custom PCB can be obsolete the day it is released to production. 10

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Lastly, feature creep can get in the way as new requirements emerge from the battlefield that require larger amounts of processing, less power, or even different mechanicals. If more sockets, more cores, or a higher mix of FPGA to CPU are now required, the designer is forced into a new spin of the board to meet new requirements. These new challenges equal higher cost, longer project delays, and increased room for competition to get to the market first. Until recently the lack of flexible, COTS-based solutions that tightly couple FPGAs to CPUs have pretty much dictated a custom design route. But ultimately, custom designs can be the reason your project misses requirements, budgets, or future product life targets.

In-Socket Accelerators and the Accelerator Abstraction Layer to the rescue

Intel has been working with third parties such as XtremeData, an expert in FPGA acceleration technologies, to develop a comprehensive approach to hardware-based acceleration. These In-Socket Accelerators are small plug-in modules that contain FPGAs, memory, and all the necessary support circuitry. These modules work on COTS systems by plugging directly into processor sockets on rackmounted servers, AdvancedTCA, or bladed server boards. The FPGA modules are thus tightly coupled to the systemâ&#x20AC;&#x2122;s GPPs through the low-latency, high-bandwidth Front Side Bus (FSB). (Future modules are also planned for Intelâ&#x20AC;&#x2122;s next generation QuickPath Interconnect [QPI] technology.) Sophisticated FSB protocols ensure FPGAs and GPPs have a coherent view of memory and caches. Application software scalability and extensibility is being addressed with high-performance abstraction middleware known as the Accelerator Abstraction Layer. AAL provides a uniform set of platform services for both GPPs and In-Socket Accelerators. It decouples applications from system implementation details so that the exact location, number, and taxonomy of GPP and Accelerator resources are transparent to the application. As Figure 1 shows, the AAL does not define domain-specific libraries or functions. Instead, it provides consistent interfaces that existing libraries and frameworks can use to interface to hardware accelerator modules. Developers can use the programming languages, libraries, and software development environments they already know. AAL provides platform level services for basic system operations such as discovery, binding, transport, and exception handling. AAL also provides services for the use of shared system memory as an efficient means of passing data between the host and accelerator. Unnecessary memory-to-memory copies are eliminated and memory is efficiently mapped between the virtual address space used by the host CPU and the physical address space used by the FPGA accelerator.

Figure 1 DSP-FPGA.com

2008-09 Annual Resource Guide

The AAL has two major components: a common Unified Accelerator Interface (UAI) and Accelerator Abstraction Services (AAS). These provide access to the algorithms that enable accelerated performance – encryption, very large Fast-Fourier Transforms (FFTs), complex FIR filtering, and so on – without the need for application programmers to delve into the minutiae of a specific accelerator’s architecture.

There’s an Accelerator Function Unit at the door

Any accelerator design block can be plugged into the FPGA to become an Accelerator Function Unit (AFU). A double-precision 64K FFT could be one example of an AFU that runs on an In-Socket FPGA module. After an AFU instance has been created, it can be used in conjunction with the domain-specific accelerator library to implement an accelerated function. They can also be stitched together with other AFUs to create an array of accelerators, such as the XtremeFFT SeaOfFFT() socket solution. AAL provides a zero-copy interface to minimize latency and maximize throughput. It does this by allowing an application to access a shared memory block that is mapped (and locked) into user space and accessible to both the accelerator module and the generalpurpose processor. The application first allocates a block of shared memory for the source and destination matrices. It then initializes the source input buffer in shared memory and calls SeaOfFFT() in the domain-specific accelerator library. The library creates a message, includes the virtual pointers to the input and output buffers, and calls the Accelerator:: ProcessMessage() function. The AFU proxy forwards the message to the appropriate Accelerator Interface Adapter (AIA), a software layer that provides a uniform device transport interface (for example, device driver). Inside the AIA, a transaction descriptor is created and queued to the appropriate AFU for processing. When the accelerator processes the doorbell signal from the host CPU, it processes the transaction, reading the source buffer and calculating the FFT’s result, which it writes back into the shared memory. When it is finished, it issues another doorbell signal back to the host CPU and the AIA device driver reads the transaction result and triggers a call back to the accelerator library indicating that the very large FFT

Figure 2 function has completed. Finally, the application is able to read the results directly from shared memory (Figure 2).

Reaping the benefits

The benefits of using AAL and In-Socket Accelerators for military system designers are:

n Decreased development time. Proprietary acceleration layers no longer have to be

developed for each new device. In-Socket Accelerators will work with a variety of standard rack-mount or bladed server boards. n Increased flexibility. Designers have more options for balancing power consumption, processing speed, cost, and feature sets. End-users can choose devices and solutions that fit changing requirements without being tied to a particular accelerator generation or even a specific accelerator technology. n Evolution ready. AAL will allow safe and easy migration as multicore processor design changes, and next generation In-Socket Accelerators and future bus technologies come to market. AAL will also allow safe and easy evolution into the future. True “accelerated COTS solutions” are now available. When shrinking development time is of the essence, FPGA-based In-Socket Accelerators working with general-purpose processors via the AAL on COTS platforms are up to the challenge. Solutions like these can help designers gain significant competitive advantages. You can now design and deploy lower cost, lower power systems that solve problems faster. And best of all, your software investment is now accelerated and portable at the same time. Geno Valente is VP of Sales and Marketing for XtremeData, Inc., maker of very high-performance database Decision Support Systems (DSS) and other accelerated appliances. Geno has spent the last 13-plus years helping support, sell, and market FPGA technology into markets such as Financial Services, Bioinformatics, High-Performance Computing, and WiMAX/ LTE, while working for Altera Corporation and now XtremeData. Peter Carlston is a Platform Architect in Intel Corporation’s Embedded Computing Division. He has held a wide variety of systems and software engineering positions at Intel and Unisys.

XtremeData, Inc. • 847-871-0379 • gvalente@xtremedatainc.com • www.xtremedatainc.com Intel • 408-765-8080 • peter.carlston@intel.com • www.Intel.com 12

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Pumping CD-quality stereo audio over digital networks in real-time

By DavidTrainor

igital audio has become synonymous with highfidelity sound, but storing and “streaming”

CD-quality stereo audio can be resource-hungry in terms of processing power, programming effort, and energy consumption. In telecommunications, much research has been conducted over many years to develop sig-

The promotion of “digital lifestyles” over recent years has significantly raised consumer expectations in relation to video definition and audio fidelity. The latter challenge has been met with compact disc recordings, immersive surround sound for home theater, and more recently, satellite radio. But the inexpensive delivery of multi channel digital audio with PCM quality in real time over bandwidth-limited channels still poses a serious challenge to digital signal processing engineers. The telecommunications industry has conducted much research and development for many years into audio compression schemes capable of transporting intelligible human speech at considerably lower bit rates than PCM. Likewise, the consumer electronics industry has adopted both sophisticated compression standards put forward by international working groups and proprietary techniques developed and marketed by commercial organizations. CD and other high-end digital audio systems typically use 16-bit linear PCM. As its name implies, Adaptive Differential Pulse-Code Modulation (ADPCM) is a technique that re-codes the difference between actual and predicted audio samples, using quantization step-sizes that adapt to the magnitude of the prediction error. In this way ADPCM can provide a similar audio quality to linear PCM but at a much-reduced bit rate. The apt-X system (see sidebar on page 16) aims to transparently code 24-bit PCM audio with a fixed compression ratio of 4:1 and is based on an implementation of sub-band ADPCM.

of transmitting speech at lower

In order to better understand how this predictive type audio codec can be implemented in as IP cores in FPGA (for example, the Altera Cyclone II and the Xilinx Spartan-3E) or SoC/ASIC using industry-standard EDA design tools and methodologies, let’s examine the encoding and decoding processes.

bit rates than PCM. Here we

Encode side

nal processing systems capable

present a predictive coding algorithm that can be implemented in commodity FPGA devices and allows CD-quality audio to be transported in real time but at lower bit rates over packet-based digital networks, from Bluetooth wireless links to Internet Protocol networks. 14

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The analog audio signal must first be converted to a 24-bit/sample PCM digital signal. This signal is then presented to the encoding algorithm (as seen in Figure 1) where successive time blocks of four PCM samples are first filtered into four equal-bandwidth sub-bands. These signals, still in 24-bit format, are then simultaneously processed in four separate signal chains – each incorporating a backward linear prediction loop that provides an estimation of the input signal. The prediction, based on the history of previous PCM samples, is subtracted from the input to yield a difference signal that is commonly termed the error signal. It is this 24-bit error signal that is then quantized for each sub-band. The quantized values are packed and embedded non-audio data is added to allow decoder synchronization via the Autosync feature. This data packing results in a 24-bit codeword that represents the content of the original 4 x 24-bit linear PCM samples per channel (96 bits) and is therefore one quarter of the original PCM data rate, a rate reduction of 4:1.

Decode side

The input to the decoder is a 24-bit compressed word. Due to the embedded Autosync information added during encoding, the decoder can detect the boundaries of the 24-bit words even after transmission across networks that are inherently unframed. Once decoder

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and adding a relatively small amount of additional on-chip memory. Lower power operation is made possible by use of specific power-saving ASIC design techniques. Typically the power consumption of the core on ASIC is 25 percent to 40 percent of the power consumption on FPGA, assuming comparable technology nodes. Evidently, structured ASIC technology offers an attractive trade off between price, performance, and power consumption.

Audio codec in DSP-RISC Figure 1 synchronization has been achieved, each input word is demultiplexed into the four low-bit resolution codewords that are fed into four separate sub-band inverse quantizer chains. The output from each inverse quantizer is then combined with the output of an adaptive predictor of similar structure to the encoder predictor. This generates four reconstructed 24-bit bandwidth-limited samples, one per sub-band, and the four sub-bands are inverse filtered to recreate four 24-bit PCM samples. The decoder output stream has the same data rate as the original PCM signal at the input to the encoder. If required these samples can be converted to an analog audio signal using an external D/A converter.

Implementation

The apt-X algorithm can be readily implemented as software on a variety of DSP and RISC processors. On modern DSPs, apt-X typically uses 8 KB of program storage, a fixed data memory block of 7 KB, and an incremental data memory block of 0.5 KB per audio channel supported. Each channel of apt-X encoding or decoding requires about 17 MIPS. RISC processors can offer a lower cost solution, but their internal architecture is less well suited to efficient implementation of the DSP algorithms within apt-X, hence the processing requirements rises to 20-27 MIPS per audio channel, depending on the specific processor used.

Given that the problem is identifying the most elegant means of encoding audio for transport over a bandwidth-compromised channel, and having selected an ADPCM-based solution owing to the inherent benefits – low latency (no sample buffering), resilience in the presence of noise/drop-outs, and manageable complexity – the problem that remains to be solved is the determination of the most appropriate means of implementation. Here, no DSP versus FPGA conundrum Altera Cyclone II family exists, as both these device architectures are suitably evolved to cope with the modest demands of enhanced ADPCM algoTotal number of LE rithms on digital signal processing resources (compared to computation- and memory-intensive “psychoacoustic-” based Total memory bits audio codecs such as MP3, AAC, and their myriad variants). The physical implementation of signal processing functions and algorithms should be a straightforward process. The choice of target device – DSP, FPGA, ASIC, SoC – in which to integrate the IP core is a decision left open to the system-level design engineer. Various factors influence this choice: bill of materials cost, upgrade flexibility, and power consumption, to name a few. Audio codecs available for design-in are typically available in a variety of delivery formats, from C code for a RISC processor, or gate-level netlist for a Field Programmable Gate Array device.

Audio codec in SoC/ASIC

Implementation of the full-duplex stereo apt-X codec described in the previous section requires approximately 200K ASIC gates. The core architecture for ASIC is particularly efficient if a large number of audio channels is required, as additional channels can be supported by scaling the core clock frequency

120320

Embedded multiplier 9-bit elements

Recommended working frequency (clk0/clk1)* Dynamic power consumption of the core**

(56.2/43) MHz 102 mW

* C7 speed grade used / a sampling frequency of 48 KHz is assumed ** at recommended working frequency / typical conditions

Table 1

Audio codec in FPGA

Tables 1 and 2 show the key parameters from FPGA integration of the audio codec IP core under discussion. This implementation supports two channels of encode and two channels of decode concurrently. Hence, the core can function as a fullduplex stereo codec. These figures are indicative: they vary depending on the enforced design constraints and the setup of the logic synthesis tool. (This data was obtained using the QuartusII7.1sp1 synthesizer and the Xilinx ISE9.21sp1.)

8204

Xilinx Spartan 3E family Number of slices

4191

Total number of 4-input LUT

7090

Number of block RAM

Number of MULT18X18

Recommended working frequency (clk0/clk1)*

(56.2/43) MHz

* C5 speed grade used / a sampling frequency of 48 KHz is assumed ** at recommended working frequency / typical conditions (core only / excluding I/O power / 25° C ambient / no heat sink / no airflow)

Table 2 DSP-FPGA.com

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Product application

Audio codec IP cores are integrated in digital communications applications from professional broadcast equipment (Figure 2) for Audio-over-IP contribution between studios, to wireless microphones, active speakers, and Bluetooth A2DP Stereo headsets.

Figure 2 David Trainor is Engineering Manager within APT’s R&D licensing group and is responsible for new audio coding algorithms for hardware and software platforms. He designed the ADEPT core, a synthesizable DSP hardware platform for licensable audio codec IP. Previously, David led a team designing security systems for payTV at Latens Systems, and spent six years with Amphion Semiconductor (now NXP) designing standards-based IP cores for wireless communications. David earned his doctorate and masters in EE from the Queen’s University of Belfast, Northern Ireland.

Audio Processing Technology +44 (0)28 9067-7200 dtrainor@aptx.com • www.aptx.com

he broadcast industry has pioneered various audio compression schemes, from NICAM for television with stereo sound, to MPEG-2 for digital video broadcast. Less familiar outside the radio broadcasting and studio post-production world is an ADPCM-based audio data compression algorithm marketed as apt-X. Developed by APT (Belfast, Northern Ireland) and progressing to adoption by the European Broadcasting Union (EBU) as a standard audio codec on interoperable equipment for studio-to-studio-to-transmitter links, apt-X exhibits a blend of performance characteristics (see data below) that make it uniquely fit-for-purpose in certain digital wireless audio applications. These benefits extend beyond preservation of PCM-like audio quality and the introduction of negligible time-delay.

apt-X is an audio compression algorithm based on Sub-band Adaptive Differential Pulse Code Modulation (S-ADPCM) principles. It provides a number of key benefits to digital signal processing designers working in professional broadcast and consumer audio. n n n n n n n n n

real-time 4:1:4 data compression and expansion 98 percent reproduction accuracy supports audio sampling at 8, 16, 24, 32, 44.1 and 48 KHz ultra low coding delay (<2 ms @ 48 KHz audio sampling) stereo audio encode and decode tolerant to tandem coding and multiple encode-decode cycles linear phase response dynamic range >100 dB embedded “Autosync” functionality

RT Hypervisor for XP on x86 We are thoroughly convinced that no matter how enamored the world is with FPGAs for signal processing, multicore general purpose CPUs are going to soon be competing at the low end with FPGAs. The same thing happened between bit slice and general purpose DSPs, then between GP DSPs and FPGAs. So when we heard about Real-Time Systems’ updated hypervisor for Windows XP, it got us thinking: just how feasible is it for a multicore CPU to execute, say, Excel while also crunching an FIR algorithm in real time? Targeting deterministic behavior in real-time (and embedded) applications, the RTS Hypervisor makes it possible to run a number of homogeneous or heterogeneous OSs on a single multicore x86 platform. It’s a compelling concept to ponder. The individual operating systems have no knowledge of the RTS Hypervisor underneath them. A CONFIG file allows an OS to be assigned to (at least) one CPU core, and additional CPU resources are similarly assigned to specific OSs. Boot sequences can be specified, and shared memory or a virtual network allows resource interplay if desired. Protection mechanisms give each OS sole assess to designated resources, and standard device drivers work as expected because the hypervisor doesn’t virtualize or simulate peripheral access. Support exists for XP, Win CE, Linux, VxWorks, PharLab ETS and Microware OS-9. By the time you read this, version 2.0 should be available.

Real-Time Systems GmbH • www.real-time-systems.com • RSC# 35958 16

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Dynamically reconfigurable Massively Parallel Processor Arrays in high-performance embedded military sysems By MikeButts

and

PaulChen

he performance requirements of high-performance embedded military systems are outstripping the capabilities of ordinary CPU and DSP processors. These embedded systems are also required to become increasingly flexible,

multimodal, and even dynamically reconfigurable in field operation. Reliable system development and operation remains essential. A new architecture, the Massively Parallel Processor Array (MPPA) has been developed specifically for meeting the challenges of designing these embedded systems.

Many advanced surveillance, intelligence, and reconnaissance sensors support multimode operation to respond to unique situational demands. For example, the Lockheed Martin AN/SPY-2 is a long-range, 3D, multifunction radar designed for theater ballisticmissile defense and full-area anti-air warfare. These functions are in addition to short-to medium-range searching and multi-target tracking. Most advanced Electro-Optic (EO) systems integrate multiple types of EO/InfraRed (IR) detectors in one sensor package. For example, the Thales SIRIUS long-range IR search-and-track system provides bi-spectral panoramic surveillance with simultaneous Mid-Wavelength InfraRed- (MWIR) and Long Wavelength InfraRed- (LWIR) band operation for automatic detection, track initiation, target priority ranking, and tracking. In the past, separate hardware and software modules were dedicated to each of these functions. Today, however, this is too expensive and inefficient for a flexible, multi-modal system. A common set of hardware should be reconfigurable on demand. In fact, the Joint Tactical Radio System (JTRS) initiative of the Department of Defense has made reconfigurability a requirement for Software Defined Radio (SDR). SDR requires a system architecture that supports multiple, evolving protocol standards. Radio and protocol modules must be parameterized and components must be exchangeable. Sensor interface systems and other high-performance systems face similar requirements.

Existing platforms for reconfigurable embedded computing

Hardware implementations with ASIC chips cannot be reconfigured. FPGAs are hardware-programmable devices that are widely used in embedded systems today, but are rarely, if ever, dynamically reconfigured in the field. Other programmable solutions are based on software-programmable processors. Since a single CPU or DSP usually cannot deliver enough performance, multiple processors executing in parallel must be used.

Multi-core DSPs for embedded systems

Multi-core CPUs with a shared memory architecture have become common in general-purpose computing, and some DSP vendors have begun adopting this architecture for embedded systems. General purpose systems are naturally capable of runtime reconfiguration. To date, the relative ease of adoption of dual-core and quad-core chips is misleading, because, in the long run, performance demands will require more and more cores. Since each CPU core must share and communicate with every other core, expensive interconnect and complex cache coherency systems are required. Plus, the interconnect and systems grow faster than the number of cores. Multi-threaded shared-memory multicores are nondeterministic, due to the interplay of caches and runtime thread behavior, and become more so as they increase in size. Debugging massively parallel multithreaded applications promises to be difficult. In the long run, massively parallel multicore platforms are not likely to be well suited to the development, reliability, cost, and power constraints of embedded systems.

FPGAs and reconfiguration

FPGA architecture was never conceived to support runtime reconfiguration, which is why it has been complex, limited, and relatively slow, despite some recent improvements. The latest work on runtime reconfiguration of FPGAs still requires complex bit-stream location at compile time and at runtime. This is to account for arbitrary FPGA constraints such as the physical layout of logic and specialized blocks. Register-to-register timing closure

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must be achieved or reconfiguration fails. Hardware interfaces between regions of the application are non-standard and hardware-specific. In addition, application development requires hardware expertise. Partial bitstream sizes are hundreds of kilobytes and reconfiguration takes tens of milliseconds. Finally, the majority of recently published work in reconfigurable computing on FPGAs does not discuss runtime reconfiguration.

Massively Parallel Processor Arrays

In embedded computing, a new platform may be adopted as the specialized and implementation-specific designs aren’t bound by the enormous application compatibility constraints inherent in general-purpose platforms. A new parallel platform, the Massively Parallel Processor Array, has been developed specifically for embedded systems. Designers use an MPPA platform to optimize performance and performanceper-watt for reconfigurable embedded system applications. They also use MPPAs because of the reasonable and reliable application development process. And, they choose MPPAs so that their hardware architecture and development effort will scale with Moore’s Law many years into the future.

MPPA architecture

An MPPA is a massively parallel array of CPUs and memories, interconnected by a 2D-mesh configurable interconnect of word-wide buses, as shown in a general way in Figure 1. One or more CPUs and RAMs are combined with a configurablyswitched interconnect of channels to make a tile. Many tiles are stacked to form the array. MPPA is a Multiple Instruction streams, Multiple Data (MIMD) architecture in which memory is distributed and accessed locally, not shared globally. Each processor is strictly encapsulated, accessing only its own code and memory. Point-to-point communication between processors is directly realized in the configurable interconnect. Since a RISC CPU is now so small and inexpensive (< 0.5 mm2), processors are not multithreaded or multitasked. Likewise, memory is not cached or virtualized, and interconnect is not shared. The MPPA is a physical “what you see is what you get” platform aimed at deterministic and reliable real-time performance with straightforward debugging. Previous parallel systems were very hard to program largely because hardware was architected and chips were built without regard for how they would be programmed. Ambric first developed the Structured 18

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Figure 1 Object Programming Model (SOPM) for its MPPAs and then designed its architecture, the Am2045 chip, and software tools to realize the model. The SOPM is illustrated in Figure 2. Each application is designed from the top down as a structure of processor and memory objects and the data and control tokens they exchange. This structure is often similar to the block diagrams used to initially define the application. As in a block diagram, there is hierarchy, and the contents of a block may be another block diagram. Objects communicate through a parallel structure of dedicated self-synchronizing channels in the chip’s configurable interconnect. One processor’s program only sends a word down a channel when the second processor is ready to accept it; otherwise, the first processor stalls until the second processor is ready. In the same way, a program trying to receive a word stalls if the channel is empty. This way, sending a word from one processor to another is also an event, which keeps them directly in step with each other. Unlike a multicore system, this feature is built into the MPPA programming model, so it is not an option or a nondeterministic debugging and testing problem for the developer. Commonly used building blocks such as filters, transforms, and so forth are checked into libraries and reused. Once tested, MPPAs can be reused with confidence because they are encapsulated and have standard interfaces. Reuse is more effective than in other platforms, especially hardware platforms, which helps keep development effort scalable. The MPPA chip described has 336 32-bit CPUs and 336 2 KB memory blocks in a hierarchical 2D mesh interconnect running at 300 to 350 MHz. At full speed, all processors together are capable of 1.2 trillion operations per second (more than one teraOPS) and 60 GMACS of DSP performance. This is supported by the interconnect’s 792 Gbps bisection bandwidth, 26 Gbps of off-chip DDR2 memory, PCI Express at an effective 8 Gbps each way, and up to 13 Gbps of parallel general purpose I/O. An integrated development environment based on Eclipse includes the compiler and assembler, simulator, automatic realization with placement and routing onto the chip, and runtime source-level interactive parallel debugging on the actual system. Development and debugging are rapid: Compiling an entire application takes less than two minutes.

Dynamic MPPA reconfiguration

Dynamic Objects (DOs) may be used in the MPPA programming model just described. DOs reconfigure themselves in an orderly manner when a reconfiguration packet arrives on a specific input channel. To control execution and reconfiguration, the local memory of each processor includes a

DSP-FPGA.com

Figure 2

persistent tiny kernel. Also persistent is a loop of control channels, used only for reconfiguration, that link all the processors in the DOs in a closed daisy chain, as shown in Figure 3. When the input kernel receives the header of a reconfiguration packet, it sends a reconfigure token around the control channel loop to the other kernels. Then it reconfigures its own processor by loading its new code into its own local memory. It then sends the remaining processor configuration into the control channel. The next kernel reconfigures itself, sends the remainder on, and so forth. Finally, each kernel waits for another token to circulate through the control channel, presumably a work token, which will start the new active object.

Figure 4 Code (32-bit)

Data (32-bit)

Packet (Bytes)

Configuration (µsec)

JANAP128

––

316

0.52

Base64 encode

572

0.70

Base64 decode

256

1,176

1.07

Custom compress

––

188

0.31

Custom decompress

––

216

0.35

RC4 encrypt

––

332

0.55

AES 10 rounds

901

––

3,608

5.41

Function

Figure 3 Figure 4 is a runtime reconfigurable work farm featuring dynamic reconfiguration. The Boss object has a set of precompiled reconfiguration packets stored in its local memory. In normal operation, work packets are sent by the Boss to the selected worker objects in the work farm. New reconfiguration packets may be sent to the work farm anytime. When a Dynamic Object completes its reconfiguration, it sends an ID back to the Boss to indicate the completion of reconfiguration. Upon receipt of the ID, the Boss initiates the distribution of new work packets to the newly reconfigured DO until its configuration is changed again.

Reconfiguration time

Table 1 shows the time it takes to reconfigure objects. The Configuration column lists the total reconfiguration time in microseconds, from receipt of the first reconfiguration packet to the time Boss receives its ID to indicate completion of the reconfiguration process.

Full R & R

By using a Massively Parallel Processor Array and its straightforward programming model, engineers can develop very high-performance embedded military systems with full reconfigurability and runtime reliability. The MPPA platform is scalable for a long lifetime of investment in software methodology.

Table 1 Mike Butts, an Ambric Fellow, has an extensive background in computer architecture, especially large-scale reconfigurable hardware, and is the coinventor of hardware logic emulation using reconfigurable hardware. He has developed several processor architectures, reconfigurable chips, and systems at Mentor Graphics, Quickturn, Synopsys, Cadence, Tabula, which he cofounded, and Ambric. Mike has 38 U.S. patents issued and BSEE and MSEE/CS degrees from MIT. Paul Chen is Director of Strategic Business Development at Ambric and has extensive knowledge of sensor and image processing, graphics, computer system architecture, and real-time operating systems. Prior to Ambric, Paul was with Tektronix, Intel, Barco, and Metheus, where he served as Senior VP. Paul published several papers on medical imaging, radar processing, embedded X Window Systems, and real-time UNIX operating systems on multiprocessor platforms. He also was a major contributor in developing the world’s first graphics controller that drives a 2,048 x 2,048 pixel 20-inch square monitor for air traffic control applications. Paul holds a BS in EE from National Taiwan University and an MS in CS from the University of Oregon.

Ambric, Inc. 503-601-6500 • mike@ambric.com • paulc@ambric.com www.ambric.com

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Easing the integration headaches of FPGAs into heterogenous embedded systems

ilitary integrators are increasingly moving away from bus-based systems with homogeneous arrays of processors and are turning to heterogeneous systems with FPGAs and serial switched fabrics such as Serial RapidIO and PCI Express in their deployed embedded multiprocessor systems. The flexibility and raw computing power of FPGAs make them a compelling choice for integrators. In addition, many current generation FPGAs contain built-in high-speed serial data links, which are ideal for systems with switched fabrics. However, integrators face challenges when trying to incorporate FPGAs into complex, heterogeneous systems. Adding to these integration issues are the ever more challenging runtime requirements and time-to-deployment pressures imposed by complex, multi-mode radar, software radio, and signals intelligence systems. To ease these problems, commercial off-the-shelf (COTS) vendors have begun adding advanced features to their products such as specialized out-of-band control and maintenance interfaces and embedded debugging features. By examining two such features and how they are implemented on a recent FPGA-based product we can better understand their impact on the system integration problem.

By MarkLittlefield

Out-of-band command communications

Military systems integrators are increasingly turning to FPGAs and serial switched fabrics for their systems. While these technologies are powerful, they introduce new challenges that commercial off-the-shelf (COTS) board vendors need to address. Out-of-band control, plus embedded debugging can ease FPGA design issues.

One of the prime concerns facing embedded system developers is how to best meet the real-time requirements of their application. Key to the problem is how to ensure that data arrives where it is needed when it is needed. To address this issue many system designers choose to keep commands separate from data. While this is often achievable between boards by using Gigabit Ethernet (GbE) for commands, leaving primary communications fabrics for their data, it is typically not a practical approach for processor/FPGA heterogeneous systems because the burden of encoding and decoding TCP/IP packets is rarely the best use of FPGA resources. A much better approach for an out-of-band command path would be to have some sort of direct connection between the FPGA and a local general purpose processor. Many processors implement a local bus for communicating with devices such as flash memories. The Freescale 8641D is one such processor. While not a particularly high-performance processor, at 31.25 MHz/32 bits, the 8641D local bus makes a fine “command bus” when hooked to a user-programmable FPGA, as seen in Figure 1. The processor’s memory space is large enough to give developers complete access to the FPGA and its attached memories. Board Support Package (BSP) functions such as Direct Memory Access (DMA) commands and interrupt control can be handled over this command bus – leaving primary fabric connections such as Serial RapidIO or PCI Express completely free for high-speed data streams. This command bus could even be extended to mezzanine cards via the XMC connectors.

Fabric port monitoring

Once a system has been implemented and the application developer has data flowing between the microprocessors and FPGAs within the system, the next questions to be 22

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Figure 1 addressed are typically “Are the data flows correct?” and “Where can I optimize data flows to get better performance from my system?” In traditional bus-based systems such as VME or CompactPCI it was easier to address these concerns because integrators had the benefit of bus analyzers to examine not only the logical behavior of their data transfers but the physical characteristics of the bus itself. This made it relatively easy for developers to tune their system for performance or to identify subtle bugs related to interprocessor communications. With the recent introduction of the VPX (VITA 46) standard and high-speed switched serial fabrics in embedded multicomputing systems, integrators face a problem that they never had to deal with previously in bus-based systems: mesh fabric connectivity. Not only does VPX utilize high-speed serial links to transfer data between boards, but it also supports mesh fabric connectivity. With mesh fabric switching, functionality is distributed between cards in the system and each card has a dedicated communication channel to the other boards in the system. While this offers system developers tremendous I/O bandwidth, it also presents several challenges to integrators, such as:

n A distributed fabric with numerous high-speed serial links signifies that there

is no single point for placing an analyzer device and see all of the interactions between components. n Placing multiple protocol analysis monitors is prohibitive from the standpoint of test equipment cost, board space requirements, and the impact on the signal integrity of high-speed serial links. n Understanding the interaction between components in a multi-stage switched interconnect, and how that impacts application level performance, requires a high level view of dataflow within the system. These issues are further complicated by the increasing use of the RapidIO multicast transport capabilities in signal processing applications. While the use of multicast can simplify the distribution of data in complex multiprocessing systems, it complicates the optimization of traffic and flow control in systems that take advantage of it. A key concern involves the ability of misbehaving nodes to lock up the system with multicast traffic streams. In one example of a response to these challenges, a RapidIO protocol capture feature has been implemented (by a third-party partner) directly into a Serial RapidIO Endpoint FPGA core for the Xilinx Virtex-5 (used in Curtiss-Wright’s Serial RapidIO Endpoint Block). The block gives users the ability to monitor and capture Tx and Rx traffic directly at the RapidIO interface. The protocol capture block can be programmed by the user at a high level to capture traffic based on complex traffic sequences. These sequences can consist of traffic events at the physical, transport, and logical layers of the RapidIO protocol. Since traffic is monitored and captured in both the transmit and receive directions, problems with flow control and protocol handshaking can be analyzed. The ability to monitor flow control can be crucial when analyzing multicast traffic issues. These capabilities can be controlled and monitored either by the 8641D processor located on the card, or remotely by any other processing element that has access to the RapidIO fabric. Using the remote capture capabilities, traffic capture on several endpoint nodes can DSP-FPGA.com

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Figure 2 be coordinated by a single management entity as shown in Figure 2 This facilitates the debug of complex problems involving multiple RapidIO endpoints on multiple cards. This protocol capture capability is supported with a library of software routines to setup capture sequences, and to decode captured data into several easily understandable formats. When combined with system level debug tools, the visibility afforded by this capability provides a powerful solution for system debug and optimization. Both of these features – an out-of-band control bus and a RapidIO protocol capture capability – are found on Curtiss-Wright’s CHAMP-FX2 FPGA-based processor board (Figure 3). The CHAMP-FX2 features two large Virtex-5 based FPGA nodes and a dualcore 8641D processor, all connected by a Serial RapidIO communications fabric with an onboard switch. The 8641D’s local bus is tied to both of the FPGA processing nodes, as well as the mezzanine site, so that boards like Curtiss-Wright’s XMC-442 can be commanded in a similar fashion. The Serial RapidIO endpoint block utilizes a Serial RapidIO core with its protocol capture port, and provides enhanced visibility into system dataflow. The common theme for today’s military systems is better time to deployment and the ability to diagnose complex problems in the field. As embedded heterogeneous multicomputing systems become more common and more complex, the need for better visibility into system operation is becoming critical to system integration and optimization. Embedding protocol capture and analysis in endpoint nodes within a RapidIO fabric gives greater visibility, reduces cost, and extends debug capabilities from the lab to the field deployments. Over time, one can expect board vendors to introduce new and innovative features to give developers better visibility and debugging capabilities. Mark Littlefield is the Product Marketing Manager for Curtiss-Wright Controls Embedded Computing’s FPGA computing products. He has more than 15 years of experience in the embedded computing industry, first as an engineer developing robot vision systems for NASA, then later as a field applications engineer, technical program manager, and product manager. Mark has a BS and an MS in Control Systems Engineering from the University of West Florida.

Curtiss-Wright Controls Embedded Computing 703-779-7800 • Mark.Littlefield@curtisswright.com www.cwcembedded.com 24

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Migrating PowerPC to FPGAs: C-to-hardware tools renew PowerPC applications By DavidPellerin

and

DanIsaacs

here is a large and established body of intellectual property developed in C for embedded systems. Much of this code resides in legacy embedded processors, and for cost reduction

or for increased performance must be migrated to more modern processing elements. Engineers tasked with this migration have many choices including the use of newer, more powerful processors and/or the redeployment of applications into FPGA devices.

Porting a legacy application to a new type of embedded computing platform is in large part determined by how much redesign work is needed. The full cost of redeployment in these cases goes beyond the bill of materials difference in hardware to include the cost of refactoring the embedded code for a different processor or, in the case of FPGA conversion, rewriting some substantial portions of the application in a hardware description language. FPGAs with embedded standard processors can greatly simplify this migration path. In the shortest FPGA conversion path, it is possible to move legacy PowerPC code to an embedded PowerPC core on an FPGA. In more sophisticated deployments, application developers also take the opportunity to consider moving high bandwidth processing elements of their code out of the processor and into the actual hardware logic on the FPGA. This has value because the FPGA hardware can exploit parallelism to run algorithms at a slower clock speed, using less power, but with higher performance than a softwareonly version. This article explores the considerations that make migrating legacy embedded code better or worse candidates for FPGA deployment, including algorithm refactoring and decisions about software/hardware partitioning, as well as re-deployment involving both migration of existing processor code and consolidation of peripheral logic to create “systems on programmable devices.” We’ll also explore how software-to-hardware tools can be used to greatly speed the redesign and refactoring process, and discuss some new architectural options this configuration opens up. The PowerPC has been a solid workhorse processor for many years. There are tens of thousands of PowerPC-based embedded applications that range from satellites to

set-top-boxes. Many of these legacy applications and their underlying algorithms remain valid and useful. Moving such applications to FPGAs is a low-cost way to value-engineering a product so it can run faster, include new features, be cheaper to produce, and use less power. FPGA manufacturers offer well-realized versions of existing processors like the PowerPC and ARM. Royalty-free “soft” processors such as Altera NIOS and Xilinx MicroBlaze are powerful targets for legacy application conversion.

Design types that will benefit from migration to FPGA

Today, the most common applications being moved to FPGAs from discrete processors include image and signal processing, sonar, radar, data security, and automotive. Key shared characteristics of these applications include: significant nonsequential logic that can be accelerated through parallelizing, I/O requirements that are outside the scope of a traditional processor, and the need for flexible memories. These projects also tend to have low to medium production volumes (too low to amortize the cost of a full ASIC implementation) or require frequent hardware field updates or customization. The goals and constraints of an FPGA migration can include performance, power, cost, heat, physical size, and reliability. Additional benefits are the classic FPGA attributes of shorter time to market and last-minute design flexibility, as well as reduced risk of component obsolescence.

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Obviously, if the current system is stable, with a non-obsolete PowerPC, migration to an FPGA-based equivalent may only pay off if there is significant consolidation of peripheral logic such that the overall device count, power consumption, and board size is reduced. In these situations the system team weighs the total cost difference, including board savings, to make a payback decision. If the system is actually scheduled for revision and it already has a PowerPC and an FPGA, there is a higher probability of payback through slightly upsizing the FPGA in order to eliminate a discrete processor. Examples of this might include:

n Trying to reduce device count and/or physically shrink a PowerPC based system. In

this format, the PowerPC code moves to the embedded processor and as much of the peripheral and processing logic moves to the remaining logic elements on the FPGA. n Increasing throughput. The more sophisticated use of this layout comes with higher speed application. In these cases it is possible to use the PowerPC as the control element in the system, and to configure logic processing engines in the FPGA fabric that can run C code in multiple threads or streams. This can enable the FPGA to out run higher clock speed processors, at significantly lower power. Central to this is hardware/software partitioning. The FPGA embedded CPU core can handle both control and processing logic. This is the mode primarily under discussion here. In this mode, the original PowerPC code runs “native” on an embedded processor core. The porting is nominal; the original application can often be brought up in the FPGA in hours. But simply porting the application from a discrete PowerPC processor to the FPGA does not carry with it substantial benefits; it may in fact run slower. The key to leveraging the FPGA’s parallel processing capability is moving processing code to dedicated hardware accelerators. Prime candidates for moving are the processing bottlenecks, those subroutines and inner code loops that consume the most processor cycles. In a coprocessing implementation, on one FPGA device there can be one or more PowerPC processors running legacy C code, closely coupled to hardware accelerators that offload the performance-critical computations.

Image processing migration example

accelerators and back. From these API function calls, the Impulse compiler generated appropriate software/hardware interfaces, using the Xilinx Auxiliary Processing Unit (APU) streaming interface. The Impulse software automatically generated the code to connect through this bus so the team did not need to learn how to write the VHDL code that this interconnection would otherwise have required. This is a key aspect of modern tools for hardware/ software codesign: by abstracting away the details of hardware/software interfaces, the tools allow software developers to focus their energy on the application, and on optimizing the actual calculations being performed rather than on the details of the hardware-level systems interfaces. Interface development, in fact, is one of the hurdles that many software teams report keeps them from trying an FPGA acceleration approach. In this case, abstract streaming interfaces provided in the Impulse APIs allowed for automatic connections between the main algorithm running on the PowerPC and hardware accelerated subroutines running in the FPGA. The modified software algorithm, which now includes three independently synchronized

As an example, one design team recently moved a JPEGbased video image filtering application to an embedded/ FPGA platform. They took an existing image processing algorithm that had been written in C, using common tools for embedded systems design. Using the Xilinx Embedded Development Kit and its cross-compiler environment, they were then able to port the legacy algorithm to an embedded PowerPC residing inside a Xilinx Virtex-5 FXT device. The Base System Builder tools (part of the EDK tools) were used to assemble the PowerPC-based system and select the needed I/O devices for a specific Xilinx reference board, in this case the Xilinx ML510 development kit. Two versions of this application were created, one using a single embedded PowerPC device for algorithm testing purposes (see sidebar) and one using two embedded PowerPC processors, custom C-language coprocessors, and an embedded web server to create a complete systemon-FPGA as shown in Figure 1. This initial porting of the application created a baseline for validation. The team was able to run the application against the original discrete processor, against the embedded PowerPC processor, and provide a software test bench for use on a development PC – all from a single code source. To identify opportunities for acceleration, they ran gprof (a common, publically available profiler) and identified computational hotspots. For example, a discrete cosine transform (DCT) algorithm was identified as one computational bottleneck. Using the Impulse CoDeveloper tools, the team was able to offload the DCT, image filters, and other bottleneck functions into dedicated FPGA hardware. Impulse C API functions were used to describe how the data moved from the PowerPC processor to the FPGA 26

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Figure 1

processes and two embedded PowerPC processors, was simulated again with standard C tools to verify that its behavior remained equivalent to the original. The C-language subroutines are now hardware accelerators and are analyzed and optimized by the Impulse C compiler, resulting in VHDL files. These files were exported to Xilinx ISE for a first pass synthesis. Synthesis took about 15 minutes for this project. The team looked at the FPGA usage post synthesis and determined that there were some improvements to be made. Optimization reports generated by the Impulse C compiler helped the team determine that using a relatively low clock rate (50 MHz) in the FPGA fabric – in combination with increased cycle-by-cycle throughput (through the use of automated pipelining) – produced the best overall results. This works because the overhead of software-to-hardware data communication via APU is nominal, and the pipelining of the inner code loop results in high throughput even at a low clock speed. Note that during this compilation process, additional compiler outputs were generated that represented hardware-to-software interfaces, including the necessary Virtex-5 APU interface logic. Software runtime libraries were automatically generated at this point, corresponding to the abstract stream and shared memory interfaces specified on the processor side of the application. Finally, the generated hardware and software files were exported from the Impulse tools (as a PCORE peripheral) and imported directly into the Xilinx Platform Studio environment for connection to the embedded PowerPC.

Different ways to allocate resources

Combining a PowerPC processor and programmable logic on a single chip opens up new possibilities for acceleration of software applications, and acceleration of the design process as well. A certain amount of effort is required to make the switch to FPGA-accelerated embedded processors, but the use of software-to-hardware methods allows software

programmers to create the entire embedded system, including the hardware accelerators in C, experiment with partitioning strategies and create effective, deploymentready results. Libraries are playing an increasingly important role in such applications. In one configuration, the system designer may rely on pre-optimized libraries (such as those found in the Xilinx CORE Generator) as well as writing customized hardware modules specific to a particular algorithm. The field reconfigurable nature of FPGAs also plays a strong role in many applications. Configurations can be updated remotely, which is a key capability for space applications as other domains including Software Defined Radio (SDR) where remote frequency changes must be performed. Another more theoretical use of this reconfiguration capability is dynamic reconfiguration, whereby FPGA logic is dynamically “recycled” into other configurations during operation. In this mode of

Using FPGA Embedded Processors as Test Generators

sing HDL simulators, FPGA hardware designers often create test benches that will exercise specific modules by providing stimulus (test vectors or their equivalents) and verifying the resulting outputs. For algorithms that process large quantities of data, such testing methods can result in very long simulation times, or may not adequately emulate real-world conditions. Adding an in-system prototype test environment bolsters simulation-based verification and inserts more complex real-world testing scenarios. Unit testing is most effective when it focuses on unexpected or boundary conditions that might be difficult to generate when testing at the system level. For example, in an image processing application that performs multiple convolutions in sequence, you may want to focus your efforts on one specific filter by testing pixel combinations that are outside the scope of what the filter would normally encounter in a typical image. It may be impossible to test all permutations from the system perspective, so the unit test lets you build a suite to test specific areas of interest or test only the boundary/corner cases. Performing these tests with actual hardware (which may for testing purposes be running at slower than usual clock rates) obtains real, quantifiable performance numbers for specific application components. Introducing C-to-hardware compilation into the testing strategy can be an effective way to increase testing productivity. For example, to quickly generate mixed software/hardware test routines that run on the both the embedded processor and in dedicated hardware, you can use the Impulse C compiler to create prototype hardware and custom test generation hardware that operates within the FPGA to generate sample inputs and validate test outputs. Impulse C generates FPGA hardware from the C-language software processes and automatically generates software-to-hardware and hardware-to-software interfaces. You can optimize these generated interfaces for the MicroBlaze processor and its fast simplex link (FSL) interface or the PowerPC and its processor local bus (PLB) interface. Other approaches to data movement, including shared memories and the use of Xilinx auxiliary processing unit (APU), are also supported. In-system testing using embedded processors is a viable complement to simulation-based testing methods, allowing you to test hardware elements using actual hardware interfaces, resulting in more accurate real-world input stimulus. This helps to augment simulation, because even at reduced clock rates the hardware under test will operate substantially faster than is possible in RTL simulation. By combining this approach with C-to-hardware compilation tools, you can model large parts of the system (including the hardware test bench) in C language.

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use, the same device could act as an image convolution filter one moment, and an object recognition algorithm the next.

Setting proper expectations

In this article we have summarized the process of moving applications from legacy C and legacy processors into mixed software/hardware implementations on FPGAs. We do not want to suggest, however, that this is a trivial, push-button process. Software programmers targeting FPGA devices need to learn some new concepts, and think about how to optimize their applications for greater levels of parallelism. Important considerations include:

n The need to refactor critical algorithms for increased performance, for example n n n n

by enabling loop-level pipelining or re-partitioning to taking better advantage of multiprocess parallelism Coding styles or coding errors that are of little concern in a traditional processor, but have great impact in an FPGA Hardware-centric, difficult to understand errors and warning messages generated by FPGA synthesis and routing tools Long place-and-route times that limit the ability for software programmers to use code-compile-debug methods of development Algorithm partitioning that makes sense in a microprocessor implementation (for example, using threads) but propagates differently in an FPGA

These considerations and issues can be overcome by software engineers, but do require some new learning. Software developers who are familiar with threading libraries or multiprocess parallelism have less difficultly taking advantage of FPGA parallelism than those who don’t. With these skills, legacy PowerPC applications can be moved to FPGAs with minimum modification. Once implemented in the FPGA and validated, their processing-intensive components can also be partitioned and compiled directly from C software descriptions to efficient, high-performance hardware that can be mapped directly into FPGA logic. Tools available today can parallelize C code for hardware implementation and generate the required software/hardware interfaces. The generated interfaces and other support files are exported into the FPGA mapping tools. This process renews existing PowerPC applications by moving them to easily upgraded hardware with minimal software modification. This process also typically improves performance, reduces device count, and reduces development time.

The authors wish to thank Glenn Steiner of Xilinx, and Brian Durwood of Impulse for their assistance with this article. David Pellerin is CTO and co-founder of Impulse Accelerated Technologies. He has been involved with software-to-hardware tools and programmable logic for more than 25 years, and is the author of five books including Practical FPGA Programming in C from Prentice Hall Publishers. Dan Isaacs is director of embedded processing for Advance Products at Xilinx. He is responsible for technical marketing in Virtex Platforms. With more than 20 years experience, Dan has worked in many aspects of engineering, including hardware and software design as well as systems engineering. Prior to joining Xilinx, Dan held engineering and technical marketing positions at LSI Logic, NEC Electronics, Ford Motor Company, and Hughes Aircraft. Dan holds a BS in electrical engineering and another in geophysics from California State University and Appalachian State University.

Impulse Accelerated Technologies • 425-605-9543 • David.Pellerin@ImpulseC.com • www.ImpulseC.com Xilinx, Inc. • 408-559-7778 • Dan.Isaacs@Xilinx.com • www.Xilinx.com

VCXO? Don’t need ’em no more. Voltage-controlled crystal oscillators (VCXO) are the preferred way to provide stable clock references in high-precision cellular base stations or frequency-sensitive A/D front end sensors. But VCXOs consume real estate, power, and cost…and they can be tricky to design with. National Semiconductor asserts that you don’t need them anymore, as long as you design with the PowerWise LMK04000 Family of clock jitter cleaners. Using only a simple external crystal, the new devices provide sub-200 femtosecond (fs) RMS jitter to improve system performance and accuracy; levels difficult to achieve even with high-dollar VCXOs. There are five members of the new jitter cleaner family ranging from 24.4 mW-ps per channel to 37.4 mW-ps per channel. Each uses National’s PLLatinum architecture consisting of two cascaded PLLs, a low-noise XO, a high-perf VCO, and low-noise dividers and drivers. Each also has dual-redundant inputs, 5 differential outputs, and an optional default clock at power-up, which is intended to drive the FPGA used to program the clock jitter cleaner’s own power-up sequence. Multiple output options exist, but can drive clocks either up to 250 MHz (LVCMOS) or 1080 MHz (LVPECL or LVDS).

National Semiconductor • www.national.com • RSC# 39359

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Two competitive FPGA methodologies for run-time reconfiguration By J. RyanKenny

and

DavidRupe

Modifying or changing the functional configuration of a device during its operation is a feature unique to FPGAs. For years, FPGA designers have been able to reconfigure a portion of their design with a new bitstream, either through hardware or software. Ryan and David discuss run-time reconfiguration approaches in the FPGA arena.

he ability to perform run-time reconfiguration is primarily used in communications, military, and consumer applications as an approach to reducing component count and power consumption. Examples of run-time reconfiguration applications include Software Defined Radio (SDR), field testing, airborne applications, and remote sensors. While a significant amount of time and effort has been dedicated to solving the run-time reconfiguration challenge in FPGAs, the resolution came from two very different approaches.

Partial Reconfiguration

Partial Reconfiguration is a design flow that creates reconfiguration regions in an FPGA. Figure 1 shows the architecture of Xilinxâ&#x20AC;&#x2122;s Virtex family of FPGAs that allows design modules to be swapped on the fly using this PR methodology. This capability allows limited resources within the device to be timeshared (reconfigured) while mission-critical or other base design requirements continue to operate in system.

Two approaches to run-time reconfiguration

Currently, there are two FPGA-based solutions to run-time reconfiguration: Partial Reconfiguration (PR) employed by Xilinx and Software Programmable Reconfiguration (SPR) used by Altera. The more ambitious PR approach necessitates an FPGA architecture designed to support reconfiguration zones. With the SPR approach, FPGA components are created as highly flexible building blocks controlled and manipulated through embedded software code running on an embedded processor or even through host software running on a general-purpose processor (GPP). 30

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Figure 1 The FPGA is divided into reconfiguration regions, and a partial bitstream must be created for programming each. The FPGA continues to operate mission-critical functions and meet external interface requirements while reconfiguration regions are reprogrammed to provide different functionality. An analogy can be drawn with a microprocessor methodology known as context switching, which is where the current state is preserved in order to switch to a different process. FPGA reconfiguration, however, switches the functional hardware, not a software state. The main advantage of this methodology is that mission-critical operations can be preserved, while only part of the FPGA device is reconfigured, as opposed to full reconfiguration of the FPGA, which does not allow for uninterrupted operation. FPGAs using PR are typically limited to a single reconfiguration region that falls within logic column boundaries, adding significant additional timing constraints. Although these FPGAs currently promote a design flow offering partial reconfigurability, only available

DSP-FPGA.com

through Application Engineering, there is no robust documented design methodology to guide a user through the implementation of the reconfiguration region. In order to implement PR, a strict design methodology must be followed:

n n n n n n

Insert bus macros between the PR modules and the static portion of the design Follow the PR synthesis guidelines to generate a partially reconfigurable netlist Create floor plans for all PR and cluster static modules Place bus macros Follow PR-specific design rules Run the PR implementation flow

Due to the strict guidelines, requirements, and a steep learning curve, significant effort is required to implement PR. The required methodology significantly complicates FPGA development efforts, lowering the abstraction level and forcing developers to focus their time and efforts on device-dependent designs close to the gates. In an effort to achieve more design flexibility and reduce risk, PR adds a significant amount of design risk to programs, especially those in the military sector. In addition, the PR approach is very dependent on tool version and device, limiting the designerâ&#x20AC;&#x2122;s selection of FPGA for size, I/O capability, and power. (Currently, there is no PR support for Spartan-class FPGA devices.)

Software Programmable Reconfiguration

Software Programmable Reconfiguration is the designed-in capability used by Altera to modify digital logic flows through internal or external software commands in the Cyclone family of FPGAs. SPR is a methodology that leverages existing IP and design software to provide an FPGA reconfiguration solution superior to PR. By taking a more softwarebased approach to FPGA development and looking at the FPGA as a System-on-Chip (SoC) with the peripheral infrastructure in place, the goals of SPR and rapid development of FPGA-based Software Defined Radio applications can be achieved with all of the pre-

SoC

viously stated advantages. Figure 2 shows the similarities between a SPR implementation and a standard microprocessor with peripheral support. The application is separated into two distinct processing planes, each utilizing a common interface standard for component interconnect. The first is the control plane used for control, (re)configuration, status, and memory management. Routing of control/configuration and status is accomplished with a control fabric. The second plane is the streaming data plane. Each of the processing blocks is connected to a streaming data fabric that allows for pointto-point data transfer between waveform components. The functionality of an FPGA can be increased significantly by using SPR, as the developer is able to raise the abstraction level to one similar to software. Additionally, design and hardware reuse is promoted, which allows multiple waveforms to be implemented on one device or across multiple devices and component building blocks that can be reused with each different application. The integration of a soft-core microprocessor into the design improves design exploration and test, providing a method of control, status, and flexible, real-time adaptive reconfiguration. Instead of redesigning, rewriting HDL, simulating, resynthesizing, and finally, reprogramming the FPGA every time a change is required, the whole range of application requirements are implemented and all the necessary adaptive software reconfigurable components are deployed to a single device or across multiple devices for easy software reconfiguration. As with microprocessors, this type of high level design is scalable, allowing for an increase in application complexity, mapping directly to an ASIC flow, and resulting in a significant increase in overall design portability. Instead of reconfiguring the device with a new bitstream, the whole application is implemented with a single unchanged bitstream, integrating all components in a single device. A control plane provides a path for control, configuration, and status of the implemented components, allowing dynamic reconfiguration and feedback of each function. It also allows commands to be sent to the streaming data switch fabric, reconfiguring the date path and allowing other functions to operate.

FPGA using SPR

Figure 2

Similar components within each function can be shared by multiple functions to save resources. In addition, a mixed Time Division Multiplexed (TDM) mode can be applied that is not supported by Partial

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2008-09 Annual Resource Guide

Reconfiguration. PR is function A or function B. The SPR-based methodology is not a true TDM function, in that f(x) can be operating while g(x) also operates, sharing only the resources necessary, as shown in Figure 3.

can prevent the propagation of SEU failures, though such a system may require the device to be reconfigured, interrupting operations. It should again be emphasized that for systems using various different waveforms, SPR holds significant assurance in singleFPGA implementations. As Moore’s Law continues to hold true, the advantages of SPR implementations will increase.

Future growth opportunities

Current FPGA capabilities for run-time reconfiguration are maturing to meet the needs of military and wireless communications applications. As the capabilities of programmable logic devices grow, there will be more demand for flexible reuse of FPGA resources. Advances in this area continue to be made in device configuration and reconfiguration speed, built-in error detection and recovery, and ease of design of the reconfiguration modes. Designers will continue developing sophisticated multifaceted designs that require robust implementations of PR. For this reason, work will continue both in developing the capabilities and ease-of-use of PR, as well as SPR. As is the case with many FPGA capabilities, having the technology available today is not sufficient to compel usage; crossing over a “design usability” barrier is required. SPR has both the design usability and reconfigurable features for today’s reconfigurability requirements.

Figure 3 In order for SPR to meet Size, Weight, and Power (SWaP) requirements using this methodology, FPGAs must feature low power, providing a significant amount of computational resources. By leveraging low-power, high-density FPGAs, the goals of FPGA reconfiguration can be easily achieved. The core static power curve shown in Figure 4 illustrates a comparison of the significant power savings per logic block available in various FPGAs.

David Rupe is BittWare’s FPGA product manager. David has spent the majority of his career in the research field, focusing on portability, reuse, and rapid development of FPGA based signal processing systems. Originally spending most of his time architecting and implementing FPGA communications systems on both custom and COTs FPGA platforms, he now leads up the FPGA architecture and development efforts for BittWare’s latest Altera-based FPGA signal processing systems. He holds a BA in Computer Engineering from Rochester Institute of Technology and an MA, also in Computer Engineering, from Northeastern University. J. Ryan Kenny is the technical marketing manager in Altera’s military and aerospace business unit. He is responsible for creating FPGA-based technical solutions for the military data and signal processing market. He joined Altera in March 2007 and has more than 10 years of experience in space and defense electronics in the U.S. Air Force and at Lockheed Martin. He graduated from the U.S. Air Force Academy, and completed an MSEE and MBA from California State University Northridge and Santa Clara University respectively.

One drawback to SPR is that it has no significant capability to recover from Single Event Upsets (SEUs) as a properly designed PR scheme could theoretically achieve. Specific FPGAs that have memory-scanning capabilities, however,

BittWare, Inc. 603-226-0404 drupe@bittware.com www.bittware.com Altera Corporation 408-544-7276 rkenny@altera.com www.altera.com

Figure 4 32

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Modeling C applications in UML with files and structures By MartinBakal

s DSP applications become more complex, the benefits of modeling the applica-

tions increase. While implementing models in an object-oriented language is easier, C developers can implement their models using either object-oriented or functional techniques. Code is intrinsically complex, and Digital Signal Processor (DSP) code is even more convoluted because of the environment its code is executed in. DSP code interacts directly with hardware, has real-time constraints coupled with size, and memory limits â&#x20AC;&#x201C; which makes designing, reviewing, and reusing DSP code a challenge.

and

JeffreyCohen

Fortunately, modeling technologies such as the Unified Modeling Language (UML) help software engineers understand applications by clearly showing structure and behavior; unfortunately, many DSP developers believe that they cannot use UML to design their applications. The basis for this belief is that UML is designed for object-oriented applications, and C code does not support object-oriented approaches. In actuality, using a functional UML approach is natural to C programmers, and modeling C applications in UML with files and structures is consistent with the way many seasoned C programmers design their applications today.

Modelingâ&#x20AC;&#x2122;s advantages

DSP application developers give many reasons why they cannot model their applications, and managers and developers need to weigh them against development costs and concerns. Companies invest heavily in the Intellectual Property (IP) that makes up these complex applications. These investments include not only development time, but testing, maintaining, and enhancing the IP, which are all areas where the abstraction and organizational benefits of a modeling process can be beneficial. While DSP development has unique historical reasons as to why they have not embraced modeling, the increase in power and complexity necessitates a new paradigm in DSP application development. Specifically, new DSP development challenges require a solution that will enable reuse (to overcome the fact that each chipset has a unique interface) and one that leverages increased DSP power, too. The new paradigm that DSP developers are using is modeling the application using UML files, allowing them to work in the manner to which they are accustomed. Modeling reduces development time: it makes the design of the programâ&#x20AC;&#x2122;s structure easier to understand, facilitates collaboration among team members, simplifies reuse, and allows testing to take place earlier in the development process.

Improving design and development

UML formalizes the graphics that DSP application developers already use. Engineers are visual people, and communicate using pictures. Long before there was a UML, engineers used graphics to design applications. Even developers unfamiliar with UML use flow charts, state machines, and sequence diagrams to design their DSP applications. Many DSP-FPGA.com

2008-09 Annual Resource Guide

use diagrams akin to UML object model diagrams that show the application’s structure. Figure 1 shows a sample of a statechart diagram for a sensor controller. UML object model diagrams show what functions each C file contains and the signatures of those functions. They also show the application’s data structures. In one view, a developer sees both the data structures and the functions, without having to page through multiple code files. Even for small applications, this one advantage saves significant development time.

Improving collaboration

On many DSP projects, few people understand the entire scope. New team members require extensive mentoring and training before becoming productive – mentoring that takes the experienced developer away from developing the new application. Using UML allows all team members to understand critical design concepts and the application’s structure quickly. When team members understand the design beyond their own areas, they can collaborate on complex part designs. Design reviews can then concentrate on finding exception conditions and logic errors, not just coding standards violations.

Modeling C applications in UML with files and structures is consistent with the way many seasoned C programmers design their applications. Improving reuse

Developers see the advantages of reusing existing designs and code, but they often cannot see what features exist in the current code base because they are buried in pages of text. By reverse engineering existing applications into a model, developers get a graphical representation of the existing code. This visualization helps 34

2008-09 Annual Resource Guide

Figure 1 them make informed decisions about which files should be included in a new model and which functionality they have to redevelop. For new development, modeling helps the developers see generalized functionality that should be abstracted. For example, most DSP applications interact with hardware. By abstracting the interface to the hardware, the reusable IP does not change each time the hardware changes. Thus, the function enumStatus analogRead(unsigned int* theInput) has to be implemented for each version of hardware, but the reusable IP calls this the same function regardless which hardware the application uses.

Improving testing

Traditionally, DSP developers do not begin testing until the hardware becomes available, which usually happens late in the development cycle. Even with hardware, physical limitations of the environment (for example: temperatures or speed of events) limit the range that the application is tested. But by abstracting the IP from the hardware, developers can test IP thoroughly and earlier in the development cycle. If the modeling tool produces sequence diagrams as the code runs and animates statecharts during execution, testers can compare these model outputs directly to the test case designs, proving that they meet requirements. The net effect of improved testing on the DSP development process is a higher quality product that meets all of the customer’s stated requirements.

Modeling function-based designs

One reason that DSP and C developers have been slow to adopt modeling is because they are accustomed to function-based programming. Even though UML was designed for object-oriented programming, C developers can still use UML concepts to model their applications. By representing C files, functions, and data structures as UML classes, developers show C language constructs on UML class diagrams, activity diagrams, sequence diagrams, and statechart diagrams. The UML element “file” becomes the basic entity for functional designs. A UML file represents the source files. These files contain all elements that C developers use: variables, functions, types, and structures. Figure 2 shows how files look on an Object model diagram, an Object model diagram showing C files instead of classes. Figure 3 shows that code generated from Telelogic Rhapsody, a UML modeling environment, is the same as handwritten code, a Header file showing the attribute CurVal and functions get CurrentValue() and reset(). All pictures in this article were created in Telelogic Rhapsody. UML includes the concept that data and functions are either public or private. Any program object may manipulate public data or call public functions; only functions within the file may use private data and private functions. In C, private attributes map to variables defined in the file’s implementation (the .c file); private operations map to functions defined in the file’s implementation. Public attributes and public operations map to variables and functions defined in the file’s specification (its .h file).

DSP-FPGA.com

Martin Bakal is a Sr. manager of business development with Telelogic, an IBM company modeling division. He has consulted on numerous embedded projects from Lockheed Martin on the Joint Strike Fighter (JSF) project to working with various customers in the automotive industry. Previously, he worked at Phar Lap Software (a Real-Time Operating System vendor) as a technical support manager. Martin has a BS in Electrical Engineering and a MS in Engineering Management from Tufts University.

Figure 2

Figure 3 C programmers represent composite data as structures. In UML, a file or class without any operations represents a structure. Frequently, developers manipulate a structure’s data via functions (for example, range checking or ensuring data consistency). The designer may model the structures and the supporting functions in the same file or in different files; however, including the structure and functions in the same file simplifies maintenance and configuration management.

Modeling keeps it simple

Developers can use the UML file construct to model C applications without changing the format of their code. Modeling simplifies the development process, facilitates collaboration, and enables reuse. As DSP applications become more complex, the benefits of modeling the applications increase.

Jeffrey R. Cohen, PE of Telelogic, an IBM company modeling division, has more than 22 years experience developing realtime and embedded applications and has been using UML to develop complex systems and embedded applications since 1998. He has worked in a variety of industries, including defense, materials handling, machine controls, and postal automation. Jeffrey has a BS in Mechanical Engineering from Carnegie Mellon University and a MS in Information Technology from Capella University.

Telelogic, an IBM company bakalm@us.ibm.com cohenje@us.ibm.com 949-830-8022 • Telelogic.com

Harsh environment PrPMC with FPGA Sometimes less is more. Consider the PrPMC520 from AcQ. The single FPGA-based ProcessorPMC (PrPMC) mezzanine board brings simple elegance to rugged, conduction-cooled embedded military designs. Based on the Freescale MPC5200B CPU running at a relatively sedate 396 MHz, the PowerPC 603e-based CPU includes double-precision floating point math, 10/100 Ethernet, USB, I2C, CAN, and myriad other “goes-innas and goes-outtas.” Wrapped around the feature-packed CPU is a Lattice XP SRAM-based, Flash-programmed FPGA ready to accept either user-defined or vendor-created functions and peripherals. AcQ suggests a TCP/IP protocol stack or offload engine, ARINC-429, MIL-STD-1553, secondary PCI, or any custom logic design. The PrPMC520 also can be populated with up to 256 MB of SDRAM, 32 MB of Flash, 64 Kbits of E2PROM, and a real-time clock with optional GoldCap battery. All I/O is routed off the PMC connectors, but a carrier board is available with connectors and breakout cables for benchtop development.

AcQ Inducom • www.acq.nl • RSC# 39358 DSP-FPGA.com

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EMAC 2390 EMAC Way, P.O. Box 2042 • Carbondale, IL 62902 Phone: 618-529-4525 • Fax: 618-457-0110

www.emacinc.com SoM-536EM

The SoM-536EM is based on the Analog Devices Blackfin ADSP-BF536 processor. This embedded DSP module has Ethernet and 2 serial ports. The BF536 combines a 32-bit RISC-like instruction set and dual 16-bit Multiply Accumulate (MAC) signal processing functionality with the ease-of-use attributes found in general-purpose microcontrollers. It is equipped with an MMU and can utilize a uClinux Operating System with real-time extensions. The SoM-536EM is designed to plug into a carrier board that contains all the connectors and any custom I/O required for the application. This approach allows the customer or EMAC to design a custom carrier board that meets the dimensional and connector requirements without having to worry about processor, memory, and standard I/O functionality. Alternatively, an off-the-shelf carrier board can be purchased. With this approach, a semi-custom hardware platform can be developed in as little as a month. For more info: www.emacinc.com/som/som536em.htm.

FEATURES ›› Small, 144-pin SODIMM form factor (2.66" x 1.5") ›› Blackfin hybrid RISC/DSP high-performance core running at

600 MHz

›› Low power consumption with dynamic power management ›› 10/100BASE-T Ethernet with onboard PHY and 1-Wire® Network ›› Two serial ports with handshake and 1 CAN 2.0B port ›› Up to 64 MB SDRAM, up to 4 MB flash, and 128 KB serial flash ›› Battery-backed real-time clock and SPI, I2S, and I2C ›› Timer/counters and Pulse Width Modulation (PWM) port ›› Typical power requirement less than 1 W ›› uClinux with Xenomai real-time extensions ›› FREE Eclipse IDE with GCC and GDB development tools

For more information, contact: Sales@emacinc.com

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Octasic Inc.

4101 Molson, Suite 300 • Montreal, QC Canada H1Y 3L1 514-282-8858

www.octasic.com Vocallo

Vocallo is a multi-core processor for voice and video over IP. Vocallo offers a complete suite of features and focuses on reduced system cost, low power, and high density solutions. Vocallo is the industry’s lowest power consumption media gateway and allows you to increase your system density, therefore reducing system cost. Through Vocallo’s scalable pricing, you can select the features and capacity you need at optimal price points and create a wide range of products from a single hardware design. Furthermore, with software development and verification being a critical path in any development schedule, Vocallo’s Megacobased API integrates easily with your application software so that you can deploy your solution quickly. Vocallo supports applications such as 3G-324M, video phones, video-conferencing, and video-enabled services with capabilities such as real-time video transcoding, video transrating, and conferencing. For more information, contact: sales@octasic.com

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FEATURES ›› ›› ›› ›› ›› ›› ›› ›› ››

Feature selection Scalable and upgradeable capacity selection User programmable and extensible Flexible I/O Lowest power per channel Best performance to power ratio in the industry Smallest space per channel API uses terminations with a connection based model H.248 objects are reflected in the Vocallo API

RSC# 34776 @ www.dsp-fpga.com/rsc

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Traquair Data Systems, Inc. 114 Sheldon Road • Ithaca, NY 14850 607-266-6000

www.traquair.com

micro-line C641x DSP/FPGA Boards The micro-line series of embedded DSP/FPGA boards provides embedded systems developers with a tightly integrated suite of programmable DSP, FPGA, and I/O resources in small, stand-alone capable board formats. micro-line C6412Compact and C641xCPU DSP/FPGA boards target high-performance integer DSP applications, using the Texas Instruments TMS320C6410, TMS320C6412, TMS320C6413, and TMS320C6418 DSPs. The C6412Compact combines a powerful 720 MHz TMS320C6412 DSP processor, up to 128 MB SDRAM, 8 or 32 MB Flash ROM, and a high-density 1 Mgate or 4 Mgate Spartan-3 FPGA. The optionally programmable FPGA greatly expands processing as well as hardware interfacing possibilities. Two independent 400 Mbps 1394a FireWire interfaces are included, enabling simultaneous highbandwidth video-in and video-out for a completely integrated video processing system. A 64-bit bus connects the DSP, FPGA, SDRAM, and FireWire resources. Onboard USB 2.0 and 10/100BASE-Tx Ethernet interfaces round off the impressive feature set available on the C6412Compact. The C641xCPU family of boards features a smaller (98 mm x 67 mm footprint) and leaner configuration, with up to 64 MB SDRAM, 8 MB Flash ROM, and a high-density 500 Kgate, 1 Mgate, or 1.6 Mgate Spartan-3E FPGA. 10/100BASE-Tx Ethernet support is optionally provided using Windmill Innovations’ eXpressDSP™-compliant bf3Net TCP/IP protocol stack and bf3Web embedded web server (SC100BASE-Tx Ethernet daughtercard is required when using C641xCPU boards). Optional Analog I/O daughtercards can also be used with the C6412Compact and C641xCPU boards: ORS-112 (16-bit A/D/A) • 4-ch A/D 2.5 MSps; 4-ch D/A 625 KSps ORS-114 (14-bit A/D/A) • 2-ch A/D 65 MSps; 2-ch D/A 125 MSps • 4-ch A/D 65 MSps; 4-ch D/A 62.5 MSps ORS-116 (16-bit A/D/A) • 12-ch A/D 250 KSps; 12-ch D/A 100 KSps

For more information, contact: sales@traquair.com

FEATURES ›› C6412Compact Features:

• 720 MHz TMS320C6412 integer DSP • 1 Mgate or 4 Mgate Spartan-3 FPGA; up to 211 configurable I/O pins • Up to 128 MB SDRAM • Up to 32 MB flash ROM for DSP and FPGA boot code, as well as non-volatile parameter/data storage • Two independent IEEE 1394a FireWire interfaces for streaming data in/out simultaneously • 10/100BASE-Tx Ethernet interface • USB 2.0 and RS-232 interfaces • External access to DSP Processor I/O interfaces: 64-bit EMIF, XF0/1 pins, Timer input/output pins, McBSP ports, I2C, and 16-/32-bit HPI • 120 mm x 72 mm footprint ›› C641xCPU Features: • 400 MHz TMS320C6410, 500MHz TMS320C6413, or 500 MHz TMS320C6418 integer DSP • 500 Kgate, 1.2 Mgate, or 1.6 Mgate density Xilinx Spartan™-3E FPGA; up to 98 configurable digital I/O pins • Up to 64 MB SDRAM • 8 MB flash ROM for DSP and FPGA boot code, as well as non-volatile parameter/data storage • RS-232 interface • External access to DSP Processor I/O interfaces: 32-bit EMIF, XF0/1 pins, Timer input/output pins, McASP and McBSP ports, I2C, and HPI • 98 mm x 67 mm footprint; ISO9001:2000 accredited production and CE certification

RSC# 31755 @ www.dsp-fpga.com/rsc

DSP-FPGA.com

2008-09 Annual Resource Guide

DSP-FPGA.com

DSP resource boards

E m b e d d ed

Resource Guide 2008-09

Traquair Data Systems, Inc. 114 Sheldon Road • Ithaca, NY 14850 607-266-6000

www.traquair.com

micro-line C6713 DSP/FPGA Boards The micro-line series of embedded DSP/FPGA boards provides embedded systems developers with a tightly integrated suite of programmable DSP, FPGA, and I/O resources in small, stand-alone capable board formats. micro-line C6713Compact and C6713CPU DSP/FPGA boards target high-performance floating-point DSP applications, using the powerful Texas Instruments TMS320C6713 DSP. The C6713Compact combines a powerful 300 MHz TMS320C6713 floating-point DSP processor, 64 MB SDRAM, 8 MB Flash ROM, and an onboard, high-density 250 Kgate, 500 Kgate, or 1 Mgate Virtex-II FPGA (optionally programmable). The FPGA greatly expands processing as well as hardware interfacing possibilities. A 400 Mbps IEEE 1394a FireWire interface is also included onboard, for communications with other embedded DSP resources, cameras, sensors, and PCs. Software APIs are available to utilize the FireWire interface for general purposes, video frame capture from cameras, and data storage to hard drives and CompactFlash memory. The C6713CPU offers a smaller (98 mm x 67 mm footprint) and leaner configuration, which has up to 64 MB SDRAM, and 2 MB flash ROM, along with a high-density 400 Kgate or 1 Mgate Spartan-3 FPGA. 10/100BASE-Tx Ethernet support is optionally available using Windmill Innovations’ eXpressDSP™-compliant bf3Net TCP/IP protocol stack and bf3Web embedded web server (requires SC100BASE-Tx Ethernet daughtercard). Optional Analog I/O daughtercards can also be used with the C6713Compact and C6713CPU boards: ORS-112 (16-bit A/D/A) • 4-ch A/D 2.5 MSps; 4-ch D/A 625 KSps ORS-114 (14-bit A/D/A) • 2-ch A/D 65 MSps; 2-ch D/A 125 MSps • 4-ch A/D 65 MSps; 4-ch D/A 62.5 MSps ORS-116 (16-bit A/D/A) • 12-ch A/D 250 KSps; 12-ch D/A 100 KSps

For more information, contact: sales@traquair.com

2008-09 Annual Resource Guide

DSP-FPGA.com

FEATURES ›› C6713Compact Features:

• 300 MHz TMS320C6713 floating-point DSP • 250 Kgate, 500 Kgate, or 1 Mgate Virtex-II FPGA; up to 160 configurable digital I/O pins • Up to 64 MB SDRAM • 8 MB flash ROM for DSP and FPGA boot code, as well as non-volatile parameter/data storage • Onboard 400 Mbps IEEE 1394a FireWire interface • RS-232 interface • External access to TMS320C6713 DSP I/O interfaces: 32-bit EMIF, XF0/1 pins, Timer input/output pins, McASP and McBSP ports, I2C, and HPI • 120 mm x 67 mm footprint; ISO9001:2000 accredited production and CE certification ›› C6713CPU Features: • 300 MHz TMS320C6713 floating-point DSP • 400 Kgate or 1 Mgate Spartan-3 FPGA; up to 96 configurable digital I/O pins • 64 MB SDRAM • 2 MB flash ROM for DSP and FPGA boot code, as well as non-volatile parameter/data storage • RS-232 interface • External access to TMS320C6713 DSP I/O interfaces: 32-bit EMIF, XF0/1 pins, Timer input/output pins, McASP and McBSP ports, I2C, and HPI • 98 mm x 67 mm footprint; ISO9001:2000 accredited production and CE certification

RSC# 31754 @ www.dsp-fpga.com/rsc

DSP-FPGA.com

Resource Guide 2008-09

Embedded

DSP resource boards

Xilinx, Inc. 2100 Logic Drive • San Jose, CA 95124 408-559-7778

ww.xilinx.com

Embedded Development HW/SW Kit - Spartan-3A DSP S3D1800A MicroBlaze Processor Edition The XtremeDSP™ Starter Kit – Spartan®-3A DSP 1800A FPGA Edition is a comprehensive development kit that includes hardware, design tools, IP, and pre-verified reference designs that can rapidly accelerate the development of your next DSP application. This kit is RoHS compliant and also includes the power adapters for US, UK, and Europe. The Spartan-3A DSP FPGA platform is ideal for cost sensitive DSP algorithmic and co-processing applications requiring significant DSP performance and can be used in a variety of applications targeting wireless, automotive, consumer, multimedia, video, imaging, industrial, medical, military/aerospace, and security markets.

FEATURES ›› Spartan-3A DSP 1800A XtremeDSP development board ›› Power supply 100-240 V, 50/60 Hz with universal plug adapters ›› USB platform download cable for configuration and debug ›› System Generator for DSP design software ›› ISE® WebPACK™ 9.2i software ›› CD containing design software, reference designs, documentation,

and board schematics

Visit: www.xilinx.com/spartandspkit.

For more information, contact: lisa.hartman@xilinx.com

DSP-FPGA.com

RSC# 37668 @ www.dsp-fpga.com/rsc

Resource Guide 2008-09

Embedded

Xilinx, Inc. 2100 Logic Drive • San Jose, CA 95124 408-559-7778

ww.xilinx.com

Embedded Development HW/SW Kit – Virtex-5 FX70T Edition PowerPC and MicroBlaze Processor Edition Develop high-performance embedded systems on Virtex®-5 FXT FPGAs with embedded PowerPC® 440 processor cores. This development kit makes it easy for designers to quickly develop full embedded system designs on a single device, utilizing immersed DSP, high-speed gigabit transceivers, and numerous IP cores as well as a new PowerPC block architecture that is optimized for high-performance processing applications targeting wired communications, wireless communications, audio video broadcast, military and aerospace, industrial, scientific, and medical markets. Learn more: http://www.xilinx.com/virtex507.

For more information, contact: lisa.hartman@xilinx.com

FEATURES ›› Xilinx Device: XC5VFX70TFFG1136 ›› Flexible Virtex®-5 FXT ML507 Development Board ›› Full set of the award winning platform studio embedded tool suite

and ISE® Foundation design software

›› Communications cables and comprehensive documentation ›› USB JTAG probe, regional power supply ›› Cross-over Ethernet and serial cables, flash device

RSC# 37663 @ www.dsp-fpga.com/rsc

DSP-FPGA.com

2008-09 Annual Resource Guide

DSP-FPGA.com

DSP resource boards

CompactPCI

Resource Guide 2008-09

Lyrtech

2800 Louis-Lumière Street, Suite 100 • Quebec City Canada G1P 0A4 418-877-4644

www.lyrtech.com SignalMaster Dual

The SignalMaster Dual is designed around one Virtex-4 LX FPGA and two C6416 DSPs. This 6U CompactPCI development platform is specifically designed to help develop advanced DSP algorithms. The board’s integration to the model-based design software tools for Simulink makes it possible to simultaneously design and test in a real-time environment. In addition, the built-in RapidCHANNEL RX/TX ports provide inter-board communication with various Lyrtech platforms through their full-duplex, 8-Gbps sustained raw data exchange capabilities. The board also features a LYRIO+ interface and RTM I/Os that allow connecting highspeed ADC/DAC, Camera Link, audio, and video (NTSC/ PAL/SECAM/DVI), and RapidCHANNEL/FPDP-I/II add-on modules.

FEATURES ›› Mixed DSP-FPGA architecture based on one Xilinx Virtex-4 LX80

FPGA and two TI C6416 1 GHz DSPs

›› LYRIO+ expansion site to connect to Lyrtech add-on I/O modules,

yielding 12 Gbps sustained, full-duplex raw data exchanges

›› 128 MB external SDRAM per DSP and FPGA ›› Four 8 Gbps RapidCHANNEL links for full-duplex communications

through external I/O interfaces

›› Stackable unit, which allows building seamless DSP-FPGA large-

scale processing farms

›› Supports model-based design flow for the most powerful integrated

development environments on the market

For more information, contact: info@lyrtech.com

RSC# 38781 @ www.dsp-fpga.com/rsc

Embedded Computing Knowledge Webcasts presented by OpenSystems Media

Look for these upcoming E-casts Reducing the Risk of Migrating to Multicore

Virtualization: Operating Systems and IO

Presented by: Wind River Systems, and Telelogic

Presented by: Freescale, LynuxWorks

Moderated by: Chris A. Ciufo

Moderated by: Jerry Gipper

October 30th, 2 p.m. EDT

November 11th, 2 p.m. EST

ecast.opensystemsmedia.com

DSP-FPGA.com

Resource Guide 2008-09

I/O: Analog

DSP resource boards

Curtiss-Wright Controls Embedded Computing 741-G Miller Drive SE • Leesburg, VA 20175 703-779-7800

www.cwcembedded.com XMC/PMC-E2202

The XMC/PMC-E2202 digital receiver XMC/PMC mezzanine is a leading solution for acquisition of high-speed analog signals in Radar, Software Radio, and Signal Intelligence applications. Quad 16-bit 160 MSps analog acquisition channels are augmented by a user-programmable Xilinx Virtex-5 SX95T FPGA. This provides the XMC/PMC-E2202 with class-leading performance in both SNR and SFDR. The high-speed digitization allows direct sampling of the most popular IF frequencies for radar systems, as well as capturing instantaneous bandwidths of >60 MHz to >700 MHz – an important feature for communications applications. It was designed from the start to be deployed with commercial and rugged (both air-cooled and conduction-cooled) versions available. The XMC/PMC-E2202 can be used either as a PCI-X (64-bit, 133 MHz) PMC board, or an XMC providing either 4 or 8 lanes of PCI Express. An FPGA developers kit is available, as well as drivers for VxWorks, Linux, and Windows operating systems.

FEATURES ›› Quad channel, 16-bit resolution with up to 160 MSps sampling speed ›› Wide I/P bandwidth >700 MHz ›› Class-leading SNR >77 dB ›› High spectral purity ›› SIND >77 dB ›› SFDR >88 dBc ›› Xilinx Virtex-5 SX95T user-programmable FPGA for digital signal

processing and A/D control

›› 16 MB ZBT RAM ›› FPGA developers kit available ›› Drivers for VxWorks, Windows, and Linux

For more information, contact: info@cwcembedded.com

DSP-FPGA.com

RSC# 38780 @ www.dsp-fpga.com/rsc

Resource Guide 2008-09

PCI-104

Sheldon Instruments 10393 San Diego Mission Road, Suite 202 • San Diego, CA 92108 619-282-6700

www.sheldoninst.com

SI-MPC-C6713DSP with GbitEthernet+USB+PCI The SI-MPC-C6713DSP is a powerful dual processor card equipped with the 300 MHz C6713 DSP for general development, and PowerPC MPC8313 communications controller to service data across PCI, 1 GbE, and 400 MB USB. Transparent links to your host PC are achieved irrespective of bus, whether it be in stand-alone connected via Ethernet/USB or in a PCI slot. Additionally, expansion hardware includes multifunction analog I/O modules, a dense FPGA with 1 Mgate open resources, 256 MB onboard flash, and microSD socket. For custom development, comprehensive APIs/driver libraries and examples are supplied with all projects and related source code. For turnkey development of real-time applications, QuVIEW and QuBASE are sets of DSP resident libraries for LabVIEW and Visual Basic.

For more information, contact: info@sheldoninst.com

FEATURES ›› Embedded/Stand-alone capability with 1 GbE and 400 MB high

speed USB connectivity

›› Several PCI and PCI Express form factors offered (PCI/PCI Express,

CompactPCI, PCI-104/PCIe-104, PMC/XMC)

›› Flexible expansion hardware includes multifunction I/O modules,

microSD flash port, and large FPGA with 1 Mgate open resources

›› Turnkey DSP development with QuVIEW/QuBASE libraries to ac-

celerate LabVIEW/Visual Basic

›› Custom application support with comprehensive APIs/driver librar-

ies and examples supplied with all projects and related source code

RSC# 38775 @ www.dsp-fpga.com/rsc

DSP-FPGA.com

2008-09 Annual Resource Guide

DSP-FPGA.com

DSP resource boards

PCI

Resource Guide 2008-09

Annapolis Micro Systems, Inc. 190 Admiral Cochrane Drive, Suite 130 • Annapolis, MD 21401 410-841-2514

www.annapmicro.com

WILDSTAR 5 for PCI Express Annapolis Micro Systems, Inc. is a world leader in high-performance COTS, FPGA-based processing for radar, sonar, SIGINT, ELINT, Digital Signal Processing, FFTs, communications, software radio, encryption, image processing, prototyping, text processing, and other processing intensive applications. Twelfth generation WILDSTAR 5 for PCI Express uses Xilinx Virtex-5 FPGAs for state-of-the-art performance. It accepts one or two I/O mezzanine cards, including Single 1.5 GHz 8-bit ADC, Quad 250 MHz 12-bit ADC, Single 2.5 GHz 8-bit ADC, Quad 130 MHz 16-bit ADC, Dual 2.3/1.5 GSps 12-bit DAC, Quad 600 MSps 16-bit DAC, Universal 3 Gbit SeriaI I/O (RocketIO, 10 Gb Ethernet, InfiniBand), and Tri XFP (10G Fibre Channel, 10 Gb Ethernet, OC-192). Our boards work on a number of operating systems, including Windows, Linux, Solaris, IRIX, ALTIX, and VxWorks. We support our board products with a standardized set of drivers, APIs, and VHDL simulation models. Develop your application very quickly with our CoreFire™ FPGA Application Builder, which transforms the FPGA development process, making it possible for theoreticians to easily build and test their algorithms on the real hardware that will be used in the field. CoreFire, based on dataflow, automatically generates distributed control fabric between cores. Our extensive IP and board support libraries contain more than 1,000 cores, including floating point and the world’s fastest FFT. CoreFire uses a graphical user interface for design entry, supports hardware-in-the-loop debugging, and provides proven, reusable, high-performance IP modules. WILDSTAR 5 for PCI Express, with its associated I/O cards, provides extremely high overall throughput and processing performance. The combination of our COTS hardware and CoreFire allows our customers to make massive improvements in processing speed, while achieving significant savings in size, weight, power, person-hours, dollars, and calendar time to deployment.

FEATURES ›› Up to three Xilinx Virtex-5 FPGA I/O processing elements – LX110T,

LX220T, LX330T, or FXT

›› Up to 7 GB DDR2 DRAM in 12 memory banks per WILDSTAR 5 for

PCI Express board or up to 2 GB DDR2 DRAM in two memory banks and up to 40 MB DDRII, QDRII SRAM, or up to 1.4 GB RLDRAM ›› Programmable Flash for each FPGA to store FPGA image ›› 8x PCI Express bus. High-speed DMA multichannel PCI controller ›› Supports PCI Express Standard External Power Connector ›› Available in commercial or industrial temperature ranges ›› Full CoreFire Board Support Package for fast, easy application development ›› VHDL model, including source code for hardware interfaces and ChipScope access ›› We offer training and exceptional special application development support, as well as more conventional support ›› Includes one-year hardware warranty, software updates, and customer support ›› Proactive thermal management system – board level current measurement and FPGA temperature monitor, accessible through Host API ›› Save time and effort. Reduce risk with COTS boards and software ›› Achieve world-class performance; WILD solutions outperform the competition

Annapolis is famous for the high quality of our products and for our unparalleled dedication to ensuring that the customer’s applications succeed.

For more information, contact: wfinfo@annapmicro.com

2008-09 Annual Resource Guide

DSP-FPGA.com

RSC# 36017 @ www.dsp-fpga.com/rsc

DSP-FPGA.com

Resource Guide 2008-09

Resource boards

DSP resource boards

Hunt Engineering Chestnut Court, Burton Row • Brent Knoll, Somerset TA9 4BP, UK +44 (0)1278 760188

www.hunt-dsp.com Hunt DSP Systems

Hunt Engineering modular systems for PCI-based, USB connected and embedded use are high-performance and designed for real-time. Our systems are programmable and reconfigurable, using common APIs to provide compatibility and complete flexibility. Configure your custom system from our off-the-shelf modules. Choose from modules with C6x DSP or Xilinx FPGA with digital and analog I/O and external memory options. Use one or a combination of these modules to create exactly the system you need. Mount your selected modules on a module carrier providing real-time data connections. Start your development straightaway. You can create your unique solution quickly and easily using the APIs, extensive examples, software frameworks and IP we include.

FEATURES ›› Choice of Xilinx FPGA and TI 'C6x modules with external memory

and I/O options

›› Can be used in a PC, USB connected or stand-alone ›› Real-time data exchange between modules ›› Systems are programmable and reconfigurable ›› System tools, plus ready-made IP, examples, frameworks included ›› Free technical support

Hunt Engineering DSP systems are suitable for a wide range of demanding applications. For more information, contact: sales@hunteng.co.uk

DSP-FPGA.com

RSC# 38783 @ www.dsp-fpga.com/rsc

Resource Guide 2008-09

VPX/VSX

Curtiss-Wright Controls Embedded Computing 741-G Miller Drive SE • Leesburg, VA 20175 703-779-7800

www.cwcembedded.com CHAMP-AV6

The CHAMP-AV6 utilizes the VPX-REDI format to unleash the tremendous I/O bandwidth of its eight Freescale Power Architecture 8641 processor cores (four 8641D dual-core processors). The local and offboard Serial RapidIO interfaces provide up to 10X the communications bandwidth that was achievable with the VME format. Signal processing applications with streaming data flows will benefit greatly from the dual 64-bit DDR2 memory subsystem associated with each 8641. The CHAMP-AV6 is supported with the Continuum suite of software development tools including board support packages, communications middleware, DSP libraries, and multiprocessor instrumentation and analysis tools.

For more information, contact: info@cwcembedded.com

FEATURES ›› Quad 8641/8641D processors at 1 GHz ›› Up to 1 GB DDR2 SDRAM with ECC per processor ›› Each processor has dual 64-bit memory banks ›› VPX-REDI format (1" pitch) with 4 Serial RapidIO ports on P1 connec-

tor and option for one PCI Express port

›› 256 MB Flash with write-protection ›› 128 KB NVRAM ›› One XMC site supporting PCI Express ›› Gigabit Ethernet to all processors with onboard switch ›› VxWorks 6.x BSP and Driver Suite supporting Workbench 2.x IDE ›› Inter-Processor Communications (IPC) library ›› Continuum Vector DSP function library with VSIPL support RSC# 38779 @ www.dsp-fpga.com/rsc

DSP-FPGA.com

2008-09 Annual Resource Guide

DSP-FPGA.com

DSP resource boards

VMEbus

Resource Guide 2008-09

Annapolis Micro Systems, Inc. 190 Admiral Cochrane Drive, Suite 130 • Annapolis, MD 21401 410-841-2514

www.annapmicro.com WILDSTAR 4 for VXS

Annapolis Micro Systems is a world leader in highperformance, COTS FPGA-based processing for radar, sonar, SIGINT, ELINT, DSP, FFTs, communications, SoftwareDefined Radio, encryption, image processing, prototyping, text processing, and other processing intensive applications. Our tenth-generation WILDSTAR 4 for VME64x/VXS uses Xilinx’s newest Virtex-4 FPGAs for state-of-the-art performance. It accepts one or two I/O mezzanine cards in one VME64x or VXS slot, including Quad 250 MHz 12-bit ADC, Single 2.5 GHz 8-bit ADC, Quad 130 MHz 16-bit ADC, Dual 2.3/1.5 GSps 12-bit DAC, Quad 600 MSps 16-bit DAC, Universal 3 Gbit Serial I/O (RocketIO, 10 Gb Ethernet, InfiniBand), and Tri XFP (OC-192, 10G Fibre Channel, 10 Gb Ethernet). Our boards work on Windows, Linux, Solaris, IRIX, ALTIX, VxWorks, and others. We support our board products with a standardized set of drivers, APIs, and VHDL simulation models. Develop your application very quickly with our CoreFire™ FPGA Application Builder, which transforms the FPGA development process, making it possible for theoreticians to easily build and test their algorithms on the real hardware that will be used in the field. CoreFire, based on dataflow, automatically generates distributed control fabric between cores. Our extensive IP and board support libraries contain more than 1,000 cores, including floating point and the world’s fastest FFT. With a graphical user interface for design entry, hardware-in-the-loop debugging, and proven, reusable, high-performance IP modules, WILDSTAR 4 for VME64x/VXS, with its I/O cards, provides extremely high overall throughput and processing performance. The combination of our COTS hardware and CoreFire allows our customers to make massive improvements in processing speed, while achieving significant savings in size, weight, power, person-hours, dollars, and calendar time to deployment.

FEATURES ›› Four Virtex-4 FPGA processing elements – two XC4VFX100 or

XC4VFX140, and two XC4VSX55 or XC4VLX40, LX80, LX100, or LX160

›› Up to 6 GB DDR2 DRAM in 12 banks or up to 2 GB DDR2 DRAM and

up to 64 MB DDRII or QDRII SRAM

›› Available for either VME64x or VXS backplanes ›› High-speed DMA multichannel PCI controller ›› Programmable Flash to store FPGA images and for PCI controller ›› Full CoreFire Board Support Package for fast, easy application

development

›› VHDL model, including source code for hardware interfaces and

ChipScope access

›› Host software: Windows, Linux, VxWorks, and more ›› Available in both commercial and industrial temperature grades/

Integrated heatsink for cooling and stiffness

›› Proactive thermal management system – board level current

measurement and FPGA temperature monitor, accessible through Host API ›› Save time and effort. Reduce risk with COTS boards and software ›› Achieve world-class performance; WILD solutions outperform the competition ›› Includes one-year hardware warranty, software updates, and customer support; training available

Annapolis is famous for the high quality of our products and for our unparalleled dedication to ensuring that the customer’s applications succeed. We offer training and exceptional special application development support, as well as more conventional customer support.

For more information, contact: wfinfo@annapmicro.com

2008-09 Annual Resource Guide

DSP-FPGA.com

RSC# 33233 @ www.dsp-fpga.com/rsc

DSP-FPGA.com

Resource Guide 2008-09

VPX/VXS

DSP resource boards

Curtiss-Wright Controls Embedded Computing 741-G Miller Drive SE • Leesburg, VA 20175 703-779-7800

www.cwcembedded.com CHAMP-FX2

The CHAMP-FX2 is Curtiss-Wright’s next-generation FPGAbased computing platform. Utilizing a 6U VPX-REDI form factor, the CHAMP-FX2 harnesses the tremendous computing power of two Xilinx Virtex™-5 FPGAs, combined with the high-performance floating-point capabilities of the Freescale 8641D dual-core PowerPC™ processor and the exceptional performance and flexibility of a Serial RapidIO switching fabric to deliver unprecedented computational densities. Equipped with multiple large DDR2 SDRAM and fast QDR-II+ SRAM blocks (>13 GBps total FPGA memory bandwidth) and several onboard and offboard RocketIO™ serial ports, the two FPGA nodes provide a balanced mix of processing capabilities with memory, inter-FPGA, and offboard bandwidths. The CHAMP-FX2 may be used in a single board configuration, or with CHAMP-AV6 or VPX-185 Single Board Computers (SBCs) with a high-speed Serial RapidIO switching fabric to form large, heterogeneous multicomputing platforms.

FEATURES ›› 6U VPX-REDI ›› Two Xilinx Virtex-5 Platform FPGAs (LX110T, LX220T, or FX130T) ›› 512 MB or 1 GB DDR2 SDRAM per FPGA in two banks (1-2 GB total

onboard), 4.4 GBps peak bandwidth per FPGA

›› 36 MB QDR-II+ SRAM per FPGA in four banks (72 MB total onboard),

8.8 GBps peak bandwidth per FPGA

›› 4-lane RocketIO connection between the two FPGAs ›› 1 GHz 8641D dual-core 8641 processor with 512 MB of DDR2 SDRAM

in two banks

›› XMC mezzanine site ›› Onboard Serial RapidIO switch with 4-lane connectivity to the

PowerPC and each FPGA and four 4-lane ports to the backplane

For more information, contact: info@cwcembedded.com

RSC# 38778 @ www.dsp-fpga.com/rsc

SP-FPGA.com Resource Guide 2008-09 DSP-FPGA.com

FPGA

Altium Inc. 3207 Grey Hawk Court, Suite 100 • Carlsbad, CA 92010 800-544-4186

www.altium.com

Altium Designer with Desktop NanoBoard NB2 Altium’s award-winning unified electronic design software combines with Altium’s NanoBoard reconfigurable development platform to transform your desktop into the ultimate Innovation Station. It allows engineers to rapidly develop systems and use FPGA technology to interactively implement, test, and debug their designs. Unlike conventional electronics design flows, where hardware must be frozen early and prototypes manufactured to provide the platform for developing and testing the intelligent portions of the device, the Innovation Station eliminates the need to work in simulated environments and build multiple prototypes. The Innovation Station provides a complete end-to-end system design environment that includes software, hardware, and programmable hardware development. All IP necessary to quickly build a working system is included.

For more information, contact: sales.na@altium.com

FEATURES ›› Altium Designer supports: design capture, PCB design and layout,

FPGA-based system design, and embedded software development

›› Desktop NanoBoard NB2 features include: application-specific

plug-in peripheral boards, high-speed PC interconnection through USB 2.0, plug-in daughter boards to target a wide range of FPGA and processor devices, integrated color TFT touch screen, and builtin, high-quality audio sub-system ›› The Innovation Station includes: Altium Designer 12 month timebased core license + Desktop NanoBoard NB2 ›› Choice of Altera Cyclone II, Lattice ECP, or Xilinx Spartan-3 FPGA

RSC# 38776 @ www.dsp-fpga.com/rsc

DSP-FPGA.com

2008-09 Annual Resource Guide

DSP-FPGA.com

FPGA

DSP Platforms

Resource Guide 2008-09

Texas Instruments 12500 TI Blvd • Dallas, TX 75243 972-995-2011

www.ti.com

Texas Instruments Family of Products Digital signal processing (DSP) from Texas Instruments offers technologies for innovative system development and application design. Find DSPs, system solutions, OMAP™ applications processors, DaVinci™ technology, software development tools, evaluation modules, codecs, algorithms, and more. DaVinci™ Digital Media Processors TI’s portfolio of DaVinci processors leverages the TMS320C64x+™ DSP core and consists of scalable, programmable Digital Signal Processing SoCs, accelerators and peripherals that are optimized for a broad spectrum of digital video end equipment. OMAP™ Applications Processors TI’s OMAP™ platform delivers a variety of high-performance applications processors with fast, portable power and a robust support network with a software portfolio that includes open source. TMS320C6000™ High-performance fixed-point DSPs High-performance TMS320C6000™ DSPs offer the industry’s highest performance fixed point DSPs ideal for imaging, broadband infrastructure, and performance audio applications. TMS320C6000™ Performance Value DSPs C6000 Performance Value DSPs offer the industry's most efficient performance value fixed-point DSPs ideal for broadband infrastructure and performance audio applications. TMS320C6000™ Floating-point DSPs C6000™ processors, the industry’s highest performance floating-point DSPs, offer precision, speed, power savings and dynamic range for professional audio, medical, industrial and more. TMS320C5000™ Low Power DSPs C5000™ DSPs enable designers of power-sensitive systems to find the device that best suits their design. The TMS320C5000 DSP platform includes a broad portfolio of over 20 devices with the optimal combination of high performance, peripheral options, small packaging and the best power-efficient performance in the industry.

For more information, contact: support@ti.com

2008-09 Annual Resource Guide

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FEATURES DIGITAL MEDIA PROCESSORS ›› TMS320DM646x is a multicore SoC consisting of DSP+ARM9 core specifically tuned for real-time, multi-format, HD video transcoding at 10x the performance and 1/10th the price ›› TMS320DM644x consists of the fully programmable TMS320C64x+™ DSP core and a scalable, programmable ARM926-based SoCs, plus accelerators and peripherals optimized for digital video end equipment ›› TMS320DM643x is based on the C64x+ DSP core and features video, memory, and network interfaces ideal for networked video, vision applications, and other cost-sensitive digital media applications OMAP APPLICATIONS PROCESSORS ›› OMAP35x applications processors are based on the market’s first broad offering of the ARM® Cortex™-A8 core to provide an unprecedented combination of laptop-like performance at handheld power levels in a single chip ›› OMAP-L1x applications processors combine high levels of connectivity with low power to enable developers to integrate GUIs into their portable designs. The OMAP-L1x product line includes ARM9 and ARM9-plus-DSP architectures C6000 FIXED- AND FLOATING-POINT DSPs ›› TMS320C6455 is the highest-performance fixed-point DSP generation in the C6000 DSP platform and is based on the advanced VelociTI™ VLIW architecture developed by TI, making these DSPs the ideal choice for video and telecom infrastructure and imaging/medical applications ›› TMS320C674x processors combine the high-precision of floatingpoint DSPs with low power to enable portable innovation. TMS320C640x DSPs offer the lowest power consumption at highperformance levels. These DSPs give designers the ability to add portability to processing-intensive applications ›› TMS320C550x DSPs maximize battery life with the industry’s lowest power fixed-point DSPs

RSC# 38790 @ www.dsp-fpga.com/rsc

DSP-FPGA.com

Resource Guide 2008-09

High-density FPGAs

FPGA

Xilinx, Inc. 2100 Logic Drive • San Jose, CA 95124 408-559-7778

ww.xilinx.com

The XtremeDSP™ Development Kit – Virtex®-5 SXT FPGA Edition The XtremeDSP™ Development Kit – Virtex®-5 SXT FPGA Edition includes hardware, design tools, IP, and preverified reference designs that can rapidly accelerate the development of your next DSP application. This unique combination of design technologies enables thousands of DSP algorithm and system designers who use MATLAB® and Simulink® (The MathWorks™) to create high-performance systems using Xilinx FPGAs. Ideal for applications such as data transmission and manipulation for many markets including wireless, automotive, consumer, multimedia, video, imaging, industrial, medical, military/aerospace, broadcast, and security.

FEATURES ›› Virtex®-5 SXT ML506 DSP Development ›› Full license of XtremeDSP Development Tools Package ›› Reference Designs (available online) ›› Xilinx Platform Cable USB ›› Universal power supply

Visit: www.xilinx.com/virtex5fxtkit.

For more information, contact: lisa.hartman@xilinx.com

DSP-FPGA.com

RSC# 37670 @ www.dsp-fpga.com/rsc

Resource Guide 2008-09

High-density FPGAs

Connect Tech Inc. 42 Arrow Road • Guelph, ON N1K 1S6 Canada 519-836-1291

www.connecttech.com Virtex-5 FPGA Card

Connect Tech’s FreeForm/PCI-104 combines a programmable FPGA with a 32-bit, 33 MHz PCI-104 interface. PCI-104’s high bandwidth, along with the versatility of the Virtex-5 FPGA, allows users to create a high-speed data and control solution that is suited to each unique application. FreeForm/PCI-104 provides an effective balance of logic fabric, on-chip RAM, DSP blocks, and user I/O to ensure that performance targets are met easily, while reducing systems costs. Features include: 3 million logic gates, 100 MHz clocking, 8 MB flash, 128 MB DDR2-400 memory, 64 single-ended or 32 LVDS I/O, 2 x 10/100 Ethernet, 2 x RS-485 serial interface, and industrial temperature range.

FEATURES ›› Provides an external 5 V power connector for stand-alone usage ›› Onboard flash memory for runtime design changes ›› Industrial temperature range models available (-40 °C to +85 °C) ›› Free ISE WebPACK for complete FPGA design ›› Reconfigurable in the field or through CTI Engineering Services ›› Lifetime warranty and free technical support

FreeForm/PCI-104 is perfect for avionics, DSP, radar, radio signal monitoring, and more. For more information, contact: www.connecttech.com

RSC# 38777 @ www.dsp-fpga.com/rsc

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2008-09 Annual Resource Guide

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FPGA

High-density FPGAs

Resource Guide 2008-09

Innovative Integration 2390 Ward Avenue • Simi Valley, CA 93065 805-578-4260

www.innovative-dsp.com X5 Family XMC Modules

The X5 module family integrates high-performance I/O with a Xilinx Virtex-5 FPGA computing core on an IEEE 1386 CMC mezzanine module with a PCI Express interface. The Virtex-5 SXT FPGA provides up to 640 DSP48 elements combined with memory blocks and logic that support a complete DSP system-on-a-chip. QDR SRAM and DDR2 DRAM memory tools provide the FPGA with deep, fast memory that is critical to implementing efficient signal processing algorithms and data acquisition. X5 modules offer a new level of performance for data logging and system integration using either PCI Express or a private data link capable of over 1 GBps sustained transfer rates. Innovative’s unique Velocia architecture provides highperformance data streaming to the host that is flexible and extensible for all types of applications. It's fast and easy to use – allowing you to concentrate on your application work because it handles all the data flow and routing. You can freely mix high rate data streams with control and status making it easy to adapt to your application, yet still achieve the full GBps data rate capabilities of the PCI Express interface. All X5 modules are architected to deliver high data throughput to the Host, along with the flexibility of usercustomizable FPGA signal processing. Board specific analog or digital I/O flows directly into the user-configurable Xilinx 5 logic device. The supplied stock logic functionality allows the board to be used out-of-the-box as a highspeed I/O board in which the large onboard DDR2 DRAM is configured as an enormous virtual FIFO, to dramatically increase the instantaneous load-carrying capacity of the board to eliminate data overruns/underruns during realtime streaming. The QDR SRAM interface is a very highspeed local cache for custom algorithms running within the FPGA. Using the FrameWork Logic VHDL source code or MATLAB board support package in the supplied FrameWork Logic BSP, you can readily customize the functionality of the FPGA to include real-time processing such as independent FIR and IIR filters on each channel, real-time FFT processing, ultra-fast feedback, and control loops and much more. Supports: Linux, Windows, RoHS, Simulink/MATLAB, C++ Drivers, Malibu Libraries, and FrameWork Logic Support! Download pricing and data sheets now!

For more information, contact: sales@innovative-dsp.com

2008-09 Annual Resource Guide

DSP-FPGA.com

FEATURES X5-400M ›› Two 400 MSps, 14-bit A/D channels, two 500 MSps ›› 16-bit DAC channels ›› ±1V, 50 ohm, SMA inputs and outputs ›› Xilinx Virtex-5, SX95T FPGA ›› 512 MB DDR2 DRAM, 4 MB QDR-II SRAM ›› Eight RocketIO private links, 2.5 Gbps each ›› >1 GBps, 8-lane PCI Express Host Interface ›› Power Management features ›› XMC Module (75 x 150 mm), PCI Express (VITA 42.3) X5-GSps ›› Two 1.5 GSps, 8-bit A/D channels (National ADC08D1500) ›› ±1 V, 50 ohm, SMA inputs ›› Xilinx Virtex-5, SX95T FPGA ›› 512 MB DDR2 DRAM, 4 MB QDR-II SRAM ›› Eight RocketIO private links, 2.5 Gbps each ›› >1 GBps, 8-lane PCI Express Host Interface ›› Power Management features ›› XMC Module (75 x 150 mm), PCI Express (VITA 42.3) X5-210M ›› Four 250 MSps, 14-bit A/D channels ›› ±1 V, 50 ohm, SMA inputs and outputs ›› Xilinx Virtex-5, SX95T ›› 512 MB DDR2 DRAM, 4 MB QDR-II SRAM ›› Eight RocketIO private links, 2.5 Gbps each ›› >1 GBps, 8-lane PCI Express Host Interface ›› Power Management features ›› XMC Module (75 x 150 mm), PCI Express (VITA 42.3) ›› PCI Express (VITA 42.3) RSC# 33650 @ www.dsp-fpga.com/rsc

DSP-FPGA.com

Resource Guide 2008-09

I/O Modules

FPGA

Acromag 30765 South Wixom Road • Wixom, MI 48393-7037 877-295-7088

www.acromagembedded.com

PMC Virtex-5 FPGA I/O with PowerPC Acromag’s new PMC-VFX modules bring together the computing power of a reconfigurable Virtex-5 FPGA and a PowerPC processor in a single package. The onboard Virtex-5 VFX FPGA has an embedded PowerPC 440 with a 32-bit RISC core to handle the most complex and memoryintensive computing applications. The module’s processing power is supported with plenty of memory. A minimum of 1 Gb of DDR2 memory is directly coupled to the PowerPC block for storage of program code and variables. Additionally, 256K x 64-bit dual-port SRAM is positioned between the FPGA and a 64-bit PCI-X bus capable of 133 MHz data rates. This large data bank optimizes high-speed DMA transfer to and from the bus. The combination of high-performance processors, plentiful memory, and a fast data interface provides a complete system package capable of solving your most demanding embedded processing challenges. Now you can customize an off-the-shelf PMC module to your requirements using high-performance parallel and serial processing. With a PowerPC on the FPGA, you are able to design system-on-chip functionality with real-time processing capabilities. Offload CPU-intensive operations such as video processing, 3D data processing, and floatingpoint math for superior system performance. The possibilities are unlimited, but the time and cost savings will keep your project within schedule and budget requirements. To further simplify development, Acromag’s Engineering Design Kit provides utilities to help write custom programs, load VHDL into the FPGA, and establish DMA transfers between the FPGA and CPU. Example VHDL code for all major functions is included.

For more information, contact: solutions@acromag.com

FEATURES ›› User-configurable Xilinx Virtex-5 FPGA with embedded PowerPC ›› XC5VFX70T FPGA provides 70K logic cells and 128 DSP48E slices ›› FPGA has embedded PowerPC® 440 processor block ›› Supports front I/O (via extension modules) and rear I/O (internal) ›› Plug-in I/O extension modules available with 16-bit 105 MHz A/D,

RS-485 differential, CMOS, or LVDS I/O interface

›› 64 I/O lines with direct connection to FPGA via rear J4 connector ›› FPGA code loads from PCI bus or flash memory ›› Two banks of 256 Kb x 32-bit dual-ported SRAM ›› Two banks of 32 Mb x 16-bit DDR2 SDRAM ›› Supports dual DMA channel data transfer to CPU/bus ›› Supports both 5 V and 3.3 V signaling ›› Conduction-cooled or up to -40 °C to +85 °C operating range

RSC# 38769 @ www.dsp-fpga.com/rsc

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2008-09 Annual Resource Guide

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FPGA

I/O Modules

Resource Guide 2008-09

Acromag 30765 South Wixom Road • Wixom, MI 48393-7037 877-295-7088

www.acromagembedded.com

PMC Virtex-5 FPGA I/O for Logic or DSP Acromag’s new PMC-VLX and PMC-VSX modules interface I/O signals to a user-configurable Xilinx Virtex-5 FPGA. This powerful FPGA can process user-defined algorithms and custom logic routines on analog or digital I/O signals depending on the interchangeable I/O extension module inserted. All models are designed for either air-cooled or conduction-cooled applications. Typical uses include sonar/ radar, military servers, signal intelligence, hardware simulators, communication processing, and automated test equipment. Powerful and versatile, these PMC modules offer a choice of Virtex-5 FPGAs to match your logic and signal processing requirements. PMC-VLX models are optimized for high-performance logic with a choice of three logic cell capacities. The PMC-VSX is designed for high-speed DSP operations. The PMC base board provides 64 I/O lines, configurable as LVTTL or 32 LVDS, via the J4 rear connector. Optional AXM extension I/O mezzanine modules can plug in to interface a variety of additional analog and digital I/O signals. Large, high-speed memory banks provide efficient data handling. Generous DDR2 SDRAM buffers store captured data prior to FPGA processing. Afterward, data is moved to dual-port SRAM for high-speed DMA transfer to the bus or CPU. A PCI-X interface ensures fast data throughput. Acromag’s Engineering Design Kit provides utilities to help users develop custom programs, load VHDL into the FPGA, and establish DMA transfers between the FPGA and the CPU. The kit includes a compiled FPGA file and example VHDL code for all major board functions.

For more information, contact: solutions@acromag.com

2008-09 Annual Resource Guide

DSP-FPGA.com

FEATURES ›› User-configurable Xilinx Virtex-5 FPGA optimized for logic or DSP ›› XC5VLX85T/110T/155T FPGA models provide up to 155K logic cells ›› XC5VSX95T FPGA provides 94K logic cells and 640 DSP48E slices ›› PCI-X bus 100 MHz 64-bit interface ›› Supports dual DMA channel data transfer to CPU/bus ›› Supports front I/O (via extension modules) and rear I/O (internal) ›› Plug-in I/O extension modules provide 16-bit 105 MHz A/D, RS-485

differential, CMOS, or LVDS I/O

›› 64 I/O lines with direct connection to FPGA via rear J4 connector ›› FPGA code loads from PCI bus or flash memory ›› Two banks of 256 Kb x 32-bit dual-ported SRAM and two banks of

32 Mb x 16-bit DDR2 SDRAM

›› Supports both 5 V and 3.3 V signaling ›› Supports Xilinx ChipScope™ Pro interface ›› Conduction-cooled or up to -40 °C to +85 °C operating range

RSC# 38770 @ www.dsp-fpga.com/rsc

DSP-FPGA.com

Resource Guide 2008-09

I/O Modules

FPGA

Innovative Integration 2390 Ward Avenue • Simi Valley, CA 93065 805-578-4260

www.innovative-dsp.com X3 XMC Family

The X3 PCI Express modules are industry standard XMCe devices which deliver performance with lower system cost and less development effort than custom designs. Use X3 XMCe modules in any PCI Express system or any XMCecompatible carrier card. Eliminate custom hardware by harnessing the power of PCI Express and customizable FPGA. All X3 modules utilize the common bus interface to deliver high data throughput to the Host, along with the flexibility of user-customizable FPGA signal processing. Board specific analog or digital I/O flows directly into the userconfigurable Spartan-3 or 3a logic device. The supplied stock logic functionality allows the board to be used outof-the-box as a high-speed I/O board in which the large onboard RAM is configured as a virtual FIFO, to increase the instantaneous load-carrying capacity of the board to eliminate data overruns/underruns during real-time streaming. However, using the FrameWork Logic VHDL source code or MATLAB board support package, you can readily customize the functionality of the FPGA to include real-time processing such as independent FIR and IIR filters on each channel, real-time FFT processing, ultra-fast feedback and control loops, and much more. Use of MATLAB/Simulink in conjunction with the supplied MATLAB board support package opens an entirely new range of real-solution possibilities. Importantly, this capability can be effectively used by anyone – you need not be an FPGA or logic design maven to effectively develop custom logic solutions!

FEATURES ›› XMC.3 module industry-standard COTS works with any PCI Express

system or host card

›› PCI Express with >150 MBps data rates. Fast, industry-standard host

bus eliminates custom hardware!

X3-10M –– PCI Express XMC Module with 8 simultaneous channels of 25 MSps 16-bit A/D, and 1.8M FPGA with DSP X3-25M –– PCI Express XMC Module – (2) 105 MSps A/Ds, (2) 50 MSps D/As, Spartan-3A DSP 1.8 M FPGA X3-A4D4 –– (4) 4 MSps A/Ds, (4) 50 MSps DACs, and 1.8 M FPGA with DSP X3-DIO

Supports: Windows, Linux, RoHS, Simulink MATLAB, C++ Drivers, and FrameWork Logic Support!

–– PCI Express XMC Module, LVDS, or LVCMOS digital I/O and 1 M FPGA with DSP X3-SD

Download Data Sheets and Pricing Now!

–– PCI Express XMC Module, 16 Channel, 216 KHz, 24-bit analog input X3-SDF –– PCI Express XMC Module, (4) 24-bit, Fast Sigma-Delta A/D > 110 dB, 1M FPGA, 4 MB memory X3-Servo –– PCI Express XMC Module – (12) 250 KSps A/Ds, (12) 2 MSps DACs, 1.8 M FPGA with DSP

For more information, contact: sales@innovative-dsp.com

RSC# 37676 @ www.dsp-fpga.com/rsc

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2008-09 Annual Resource Guide

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FPGA

I/O: Analog

Resource Guide 2008-09

VMETRO Inc. 1880 South Dairy Ashford, Suite 400 • Houston, TX 77077 281-584-0728

www.vmetro.com/ad3000 AD3000 3 GSPS ADC

The AD3000 is a Xilinx Virtex-5 SXT or LXT FPGA closely coupled to a high-speed analog input front end providing processing and acquisition in a single XMC/PMC card. The Virtex-5 FPGA controls the analog to digital converter and provides the off-board digital interfaces of PCI-X and the multi-Gbps serial I/O used for the XMC interface. The combination of a user programmable FPGA closely coupled to both data I/O sub-systems and multiple banks of fast memory provides a platform for acquiring and processing the data in one board. An LVPECL trigger input, an LVPECL output, an LVTTL output, and the sample clock input are provided on the front panel. This connectivity allows the AD3000 to be operated in a range of modes, including multi-board synchronous sampling.

FEATURES ›› 3 GSps, 8-bit ADC in PMC/XMC form factor ›› Xilinx Virtex-5 LX110T or SX95T FPGA (user programmable) ›› Dual banks of QDR and SDRAM memories ›› Windows, VxWorks, and Linux support ›› Rugged and commercial build options

For more information, contact: info@vmetro.com

RSC# 33182 @ www.dsp-fpga.com/rsc

DSP-FPGA.com

I/O Modules

Resource Guide 2008-09

Lavacore, Inc. 2280 Faraday Ave., Suite 163 • Carlsbad, CA 92008 760-494-7268

www.lavacore.com

PF5100 PC/104-PLUS Virtex-4 Embedded PowerPC FPGA Module The PF5100/FX™ is an ultra high-density reconfigurable PC/104-Plus module based on the Xilinx Virtex-4 Platform FPGA. The module provides a comprehensive product line, supporting the Virtex-4 FX60 and FX100 devices. The FX family incorporates the embedded PowerPC processor and is a full featured solution for embedded systems. These high-performance modules are designed for deployment in embedded systems for avionics, military, automotive, marine, and industrial applications. Applications include data acquisition, high-speed control, image and signal processing, robotics, and prototyping. Software includes a set of utilities and an API that provide module diagnostics, FPGA configuration, and Flash programming. IP support includes an SDRAM controller, SRAM controller, ISA interface, and PCI interface.

FEATURES ›› PC/104 (ISA) and PC/104-Plus (PCI) Bus compliant stackable mod-

ules

›› Choice of Xilinx Virtex-4 FX60 and FX100 FPGAs ›› Standalone and/or host peripheral operation ›› FPGA configuration from Flash or host ›› 8-bit FPGA SelectMAP configuration interface via PC/104 bus ›› 64x2 user configurable I/O ›› 128 MB DDR SDRAM, 2 MB ZBT SRAM, 8 MB Flash Memory ›› 10/100BASE-T Ethernet PHY, 2 RS-232 ports, JTAG port ›› OS support includes Linux, DOS, QNX 6.x, Win9x, WinNT/2000/XP ›› Software utilities include FPGA configuration, Flash programming,

and diagnostics

For more information, contact: info@lavacore.com

2008-09 Annual Resource Guide

DSP-FPGA.com

RSC# 38793 @ www.dsp-fpga.com/rsc

DSP-FPGA.com

Resource Guide 2008-09

IP and System Cores

FPGA

RF Engines Ltd Innovation Centre

St Cross Business Park • Newport, Isle of Wight, UK 44 (0)1983 550330

www.rfel.com ChannelCore64

ChannelCore64 is a fully flexible 64-channel Digital DownConversion (DDC) core, which enables designers to replace up to 16 specialist DDC ASIC devices with a single IP core for FPGA, significantly reducing board area, lowering power consumption, and increasing flexibility. The approach represents a major cost saving over traditional methods, with savings becoming more significant as the number of channels increases. ChannelCore64 is targeted at applications such as wireless base stations, satellite ground stations, and other multichannel radio receivers. RFEL provides high specification signal processing solutions for FPGAs, as well as receiver and complete product solutions for the homeland security, defense, communications, and instrumentation markets.

FEATURES ›› 64 independent, reconfigurable Down-Conversion channels ›› Support for two 16-bit ADC inputs up to 220 MSps ›› Alias-free channel bandwidths, up to 687.5 KHz ›› Independent tuning of channel center frequencies with a resolution

<0.01 Hz

›› Fraction resampler for setting output sample rates with a resolution

<0.01 Hz

›› Reconfigure channels without affecting operation of other channels ›› End-to-end dynamic range of >80 dB ›› Gain control

For more information, contact: sales@rfel.com

DSP-FPGA.com

RSC# 31164 @ www.dsp-fpga.com/rsc

Resource Guide 2008-09

Low- and mid-density FPGAs

Connect Tech Inc. 42 Arrow Road • Guelph, ON N1K 1S6 Canada 519-836-1291

www.connecttech.com FPGA & Digital I/O

Connect Tech’s FreeForm/104 offers two PC/104 solutions in one. Based on Xilinx’s Spartan-3E FPGA, FreeForm/104 is fully customizable and field programmable. When used with its standard core, FreeForm/104 is also a digital I/O and counter/timer solution. Use FreeForm/104 when time to market is of the essence, field-reprogrammability is a must, and when speed and accuracy are critical. CTI’s standard core includes 96 digital I/O (8255), 6 counter/ timers (8254), and Opto-22 compatibility. Off-the-shelf flexibility and a high-speed processing core within a rugged design make the FreeForm/104 ideal for real-time applications including: DSP, software-defined radio, aerospace, defense systems, laboratory testing, and industrial process monitoring/control. For more information, contact: www.connecttech.com

FEATURES ›› Provides an external 5 V power connector for stand-alone usage ›› Onboard flash memory for runtime design changes ›› LEDs, rotary switch, and reset button ease the VHDL development

process

›› Free ISE WebPACK for complete FPGA design ›› Reconfigurable in the field or through CTI Engineering Services ›› Lifetime warranty and free technical support

RSC# 32921 @ www.dsp-fpga.com/rsc

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2008-09 Annual Resource Guide

FPGA

Low and mid-density FPGAs

DSP-FPGA.com

Resource Guide 2008-09

Xilinx 2100 Logic Drive • San Jose, CA 95124 USA 408-559-7778

www.xilinx.com

The XtremeDSP™ Starter Kit – Spartan®-3A DSP 1800A FPGA The XtremeDSP™ Starter Kit – Spartan®-3A DSP 1800A FPGA Edition is a comprehensive development kit that includes hardware, design tools, IP, and preverified reference designs that can rapidly accelerate the development of your next DSP application. This kit is RoHS compliant and also includes the power adapters for US, UK, and Europe. The Spartan-3A DSP FPGA platform is ideal for cost sensitive DSP algorithmic and co-processing applications requiring significant DSP performance and can be used in a variety off applications targeting wireless, automotive, consumer, multimedia, video, imaging, industrial, medical, military/aerospace, and security markets.

FEATURES ›› Spartan-3A DSP 1800A XtremeDSP development board ›› Power supply 100-240 V, 50/60 Hz with universal plug adapters ›› USB Platform download cable for configuration and debug ›› System Generator for DSP design software ›› ISE® WebPACK™ 9.2i Software ›› CD containing design software, reference designs, documentation,

and board schematics

Visit: www.xilinx.com/spartandspkit.

For more information, contact: lisa.hartman@xilinx.com

RSC# 37669 @ www.dsp-fpga.com/rsc

DSP-FPGA.com

Processor Boards

Resource Guide 2008-09

Nallatech 1010 Liberty Road • Eldersburg, MD 21784 410-552-3352

www.nallatech.com BenONE-PCIe™

The BenONE-PCIe™ provides a powerful PCI Express® computing platform for high-performance FPGA development and deployment across a range of application areas including signal intelligence, image processing, software defined radio, and algorithm acceleration. Featuring a DIME-II™ expansion slot, the BenONE-PCIe motherboard supports multiple analog and digital I/O interfaces, memory types, and Xilinx® user FPGAs on a single 8-lane PCI Express card. Off-card high speed digital I/O headers allow multiple BenONE-PCIe cards to be interconnected via low latency point-to-point links. These deterministic datapaths are independent of the Host operating system and an ideal way of scaling applications.

For more information, contact: contact@nallatech.com

2008-09 Annual Resource Guide

DSP-FPGA.com

FEATURES ›› 8-lane PCI Express 1.1 ›› Xilinx Virtex-5 PCI Express interface FPGA ›› Up to 1.1 GBps full duplex host bandwidth ›› DIME-II FPGA module expansion slot ›› Multiple off-card I/O headers including RS-232, single-ended GPIO,

differential GPIO, or high-speed serial I/O

›› Windows® and Linux® Operating System support ›› Compatible with Intel QuickAssist Accelerator Abstraction Layer

RSC# 34491 @ www.dsp-fpga.com/rsc

DSP-FPGA.com

Resource Guide 2008-09

Processor Boards

FPGA

Nallatech 1010 Liberty Road • Eldersburg, MD 21784 410-552-3352

www.nallatech.com

XMC-220™ – FPGA and 16-bit Analog I/O PMC/XMC The XMC-220™ FPGA and 16-bit Analog I/O PMC/XMC is designed to meet the data acquisition and digital signal processing needs of modern signal intelligence, software defined radio, and radar applications. The very latest high-resolution A/D and D/A conversion technology enables analog signal input and output directly to the FPGA for processing. The FPGA processing resources can be used to implement complex algorithms such as FFTs, digital down conversion, and filtering in real-time. As part of the scalable VME and XMC series of products from Nallatech, the XMC-220 is complemented by further PMC/XMC mezzanines, VME compute cards, and application development tools.

FEATURES ›› Single-width PMC/XMC mezzanine ›› Xilinx® Virtex™-5 LX155T or SX95T FPGA ›› Two banks 256 MB DDR2 SDRAM ›› PCI-X 133 PMC interface ›› Eight GTP serial links to XMC connector ›› Interface controller to simplify communications and control ›› Two 16-bit 180 MSps A/D converters ›› Two 16-bit 1 GSps D/A converters ›› Linux and VxWorks OS support packages ›› FPGA Development Kit provides IP cores for all FPGA peripherals ›› Commercial (forced-air) and rugged (forced-air or conduction-

cooled) versions

For more information, contact: contact@nallatech.com

DSP-FPGA.com

RSC# 38709 @ www.dsp-fpga.com/rsc

Resource Guide 2008-09

Processor Boards

Nallatech 1010 Liberty Road • Eldersburg, MD 21784 410-552-3352

www.nallatech.com

XMC-210™ – FPGA and dual 8-bit 3 GSps A/D PMC/XMC The XMC-210™ FPGA and dual 8-bit 3 GSps A/D PMC/XMC is designed to meet the data acquisition and digital signal processing needs of needs of modern signal intelligence, software defined radio, and radar applications. The very latest high-speed analog to digital conversion technology enables signals to be digitized and passed directly to the FPGA for processing. The FPGA processing resources can be used to implement complex algorithms such as FFTs, digital down conversion, and filtering in realtime. As part of the scalable VME and XMC series of products from Nallatech, the XMC-210 is complemented by further PMC/XMC mezzanines, VME compute cards, and application development tools.

FEATURES ›› Single-width PMC/XMC mezzanine ›› Xilinx® Virtex™-5 LX155T or SX95T FPGA ›› Two banks 256 MB DDR2 SDRAM ›› PCI-X 133 PMC interface ›› Eight GTP serial links to XMC connector ›› Interface controller to simplify communications and control ›› Two 8-bit 3 GSps A/D converters ›› 3 GHz input signal bandwidth ›› Linux and VxWorks OS support ›› FPGA Development Kit provides IP cores for all FPGA peripherals ›› Commercial (forced-air) and rugged (forced-air or conduction-

cooled) versions

For more information, contact: contact@nallatech.com

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FPGA

Processor Boards

Resource Guide 2008-09

Nallatech 1010 Liberty Road • Eldersburg, MD 21784 410-552-3352

www.nallatech.com BenADDA-16™

The BenADDA-16™ integrates multi-channel, high-speed analog I/O with the extreme processing of an FPGA. The DIME-II™ module combines a Xilinx® Virtex-5™ SXT, LXT, or FXT FPGA with two Linear Technology 16-bit, 180 MSps ADCs and a single Texas Instruments dual channel 16-bit 1 GSps DAC. Two independent banks of QDR-II SRAM directly coupled to the Xilinx Virtex-5 FPGA are capable of double buffering ADC data prior to processing. The result is a high-performance data acquisition and processing platform in a proven COTS solution. The BenADDA-16 is the ideal solution for easy, low risk system integration or in-field deployment.

FEATURES ›› DIME-II expansion module ›› Dual 16-bit, 180 MSps analog capture channels ›› Dual 16-bit, 1 GSps analog output channels ›› External clock input and onboard high accuracy fixed oscillator

clocking options

›› Onboard Xilinx Virtex-5 SXT, LXT or FXT user FPGA ›› 18 MB QDR-II SRAM – 2 independent banks ›› Compatible with all Nallatech DIME-II motherboards

For more information, contact: contact@nallatech.com

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Processor Boards

Resource Guide 2008-09

VMETRO, Inc. 1880 South Dairy Ashford, Suite 400 • Houston, TX 77077 281-584-0728

www.vmetro.com/hpe640

HPE640 6U VPX PowerPC and FPGA Processor The HPE640 high-performance 6U VPX hybrid processing engine couples two dual-core Freescale Power Architecture™ MPC8641D processors with two latest generation Xilinx Virtex-5 FPGAs. With its combination of dual highperformance CPUs and latest generation twin FPGAs, this DSP board provides leading edge performance with flexible high-bandwidth I/O. Input/output is provided through a number of channels including GbE ports, FMC (VITA 57) site, or VPX serial I/O for interboard communications. The HPE640 is now available in both air-cooled and conduction-cooled versions with VxWorks or Linux board support packages. The HPE640 is supported by the FusionXF FPGA design suite.

For more information, contact: info@vmetro.com

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FEATURES ›› 2x dual-core Freescale Power Architecture™ MPC8641D processors

at 1.25 GHz

›› 2x Xilinx Virtex-5 FPGAs (LX155T or SX95T) ›› Multiple banks of DDR2 SDRAM and QDR2 SRAM memories ›› VITA 57/FMC site ›› Aurora and PCI Express backplane connectivity ›› 6U VPX form factor

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Resource Guide 2008-09

Processor Boards

FPGA

Embedded Systems Design, Inc. 6810 Deerpath Road, Suite 300 • Elkridge, MD 21075 410-712-7290

www.embedded-sys.com StreamBlade Family

The Embedded Systems Design, Inc. (ESD) StreamBlade™ Family of products provides developers with the software infrastructure and hardware building blocks necessary to implement distributed FPGA-based processing systems. ESD products are designed to transport and process realtime streaming data and are ideally suited to streaming applications such as telecommunications protocol processing, software-defined radio applications, and real-time streaming data, including video and voice processing, generation, recording, and playback. All ESD products were derived from actual client requirements. The SB-SOE-4 was designed to replace data formatting functions performed by two 1U rack-mounted Linux servers and 4-bit capture cards used in a GbE-based streaming data distribution system. The SB-MiniFX was designed to implement one quarter of the SB-SOE-4 board’s functions and interface with a client’s dual ADC board. The SB-5600 was designed as a stand-alone real-time streaming I/O processing system utilizing a combination of FPGA, embedded, and general purpose processing nodes. The SB-5600 platform was designed to be a self-contained system to generate Pseudo Random Bit Sequence (PRBS) patterns and verify PRBS patterns with bit-error injection capability.

FEATURES ›› FPGA-based platforms support development of combined software

and reconfigurable hardware processing applications

›› Developers have full access to configured FPGAs and general

purpose processors

›› GbE ports utilizing hard core MACs allow for the implementation of

distributed FPGA processing nodes

›› Ethernet connectivity provides network-based command, control,

and status

The SB-5600 is ideally suited to real-time applications including: streaming data (voice, video, and image), telecom/datacom, symbol-to-bit conversion, algorithm acceleration, data formatting, pattern generation/recognition, and test instrumentation. FPGAs provide an extraordinary opportunity to reduce Size, Weight, and Power (SWaP) consumption while accelerating processing capabilities in numerous applications.

›› Innovative CPLD-controlled flash memory provides rapid configura-

ESD plans to add additional products to the StreamBlade™ Family based on the constant input the company receives from its embedded engineering services business.

›› Available I/O modules support parallel differential clock and data

For more information, contact: info@embedded-sys.com

tion of FPGAs and embedded processors

›› StreamBlade™ architecture leverages well-understood technolo-

gies, such as: Ethernet, TCP/IP, Linux, and FPGA

›› ESD provides an Application Development Kit (ADK) including FPGA

cores, sample applications, and source code

›› Linux and GNU development tools may be used in combination with

the FPGA design flow

›› Signal conditioning is provided by plug-in modules ›› Available I/O modules support serial differential clock and data

streams (LVDS, RS-422, and ECL) streams (LVDS, RS-422, and ECL)

›› Available I/O modules support T1/E1 data streams and T3/E3 data

streams

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FPGA

Processor Boards

Resource Guide 2008-09

Jacyl Technology 3909 Fourier Drive, Suite B • Fort Wayne, IN 46818 800-590-6067

www.jacyl.com XG-5000K

The XG-5000K, the 5 million gate PC/104-Plus FPGA board Centered around a 5 million gate Spartan-3 FPGA, the XG-5000K is the ultimate PC/104-Plus FPGA board that is ready to meet the most demanding of system designs. The board features a 5 million gate Spartan-3 FPGA, 256 MB of onboard Micron SRAM, 32 MB of onboard Intel flash, 264 user-programmable I/O, Type 1 CompactFlash connector, a secondary 500 Kgate Spartan-3 FPGA, 10/100BASE-T Ethernet interface, two RS-232 interfaces, PC/104 connector, PC/104-Plus connector, 0-25 MHz programmable DDS master clock source, 8 MB of secondary DataFlash, and a 25 MHz initial master clock. The XG-5000K has the advanced feature of allowing the user to remotely reconfigure the entire board through the onboard JTAG connector, PC/104 connector, PC/104-Plus connector, 10/100BASE-T Ethernet interface, or any external interface connected to the XG-5000K. The XG-5000K has been developed with Xilinx’s advanced design revisioning technology. This allows the XG-5000K to retain onboard as many as 16 partial or up to 4 complete design revisions for the 5 million gate Spartan-3 FPGA. Any one of these design revisions can be remotely programmed into the 5 million gate Spartan-3 FPGA, or the XG-5000K can be programmed to reconfigure itself based upon external or internal events. The XG-5000K also incorporates a secondary 500,000 Kgate Spartan-3 FPGA. This second FPGA is initially configured to control remote reprogramming and control of the design revisioning features of the XG-5000K. But the secondary Spartan-3 FPGA can be reconfigured by the user to meet the requirements of a particular system design. The XG-5000K can be powered from the PC/104 bus or can be powered from a single 5 VDC external source allowing the board to be utilized as a stacked module in PC/104 applications or as a stand-alone product design platform. This allows the board to be ideal in embedded PC/104 applications or to be utilized in development platforms, design prototypes, or production products.

For more information, contact: sales@jacyl.com

2008-09 Annual Resource Guide

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FEATURES ›› 5 million gate Xilinx Spartan-3 FPGA on a PC/104-Plus platform ›› Onboard 256 MB of Micron SRAM and 32 MB of Intel flash ›› Four 66-pin VHDC connector banks providing a total of 264 user

programmable I/O

›› CompactFlash Type 1 connector ›› A secondary 500 Kgate Spartan-3 FPGA for remote reconfiguration

and design revisioning of the XG-5000K or custom user configuration

›› 10/100BASE-T Ethernet interface and two RS-232 interfaces ›› Can be used in a PC/104 stack or as a stand-alone product design

platform

›› 0-25 MHz user-programmable DDS FPGA master clock source, along

with a fixed 25 MHz FPGA master clock source

›› Incorporates Xilinx’s design revisioning technology and can retain

onboard as many as 16 partial or up to 4 complete design BIT files

›› Can be reconfigured through the configuration PROMs,

JTAG,10/100BASE-T Ethernet, PC/104, PC/104-Plus connectors, or the user I/O ›› Available in industrial temperature range ›› Can be powered from the PC/104 connector or an external 5 VDC source

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Resource Guide 2008-09

Processor Bsoards

FPGA

Nallatech 1010 Liberty Road • Eldersburg, MD 21784 410-552-3352

www.nallatech.com

VXS-610™ – Dual FPGA and PowerPC® multiprocessor The VXS-610™ PowerPC® and dual FPGA multiprocessor is designed to meet the signal processing needs of modern signal intelligence, software defined radio, and radar applications. Two Xilinx® Virtex™-5 FPGAs enable high-performance DSP applications to be implemented with low levels of power consumption. Either DSP-optimized SX95T or logic-optimized LX155T FPGAs are available, supporting a broad range of user applications. The onboard Freescale MPC8548E PowerPC provides high performance with a relatively low level of power consumption and makes it ideal for implementing card management and data handling functionality. Inter-card communications can be implemented using the VME64 interface, or using Serial RapidIO® across the VXS P0 connector. VME communications are handled by the PowerPC via a Tundra PCI-VME bridge. Serial RapidIO provides a fully featured high performance communications mechanism between the PowerPCs and FPGAs across multiple cards. Serial RapidIO is handled on-card by a dedicated Tundra switch which interfaces to the PowerPC via a dedicated port, and to the FPGAs via high performance IP cores that are provided as standard with the VXS-610. VXS-610 maximizes sensor I/O density with two PMC/ XMC sites. These enable multi-channel signal digitization schemes to be implemented on-card, or pre-digitized signals to be brought onboard using digital I/O. Network I/O such as Ethernet® or 1553 can also be implemented using mezzanine cards.

FEATURES ›› Single-Slot VXS card ›› PowerPC node with MPC8548E processor ›› Two FPGA nodes with Xilinx Virtex-5 LX155T or SX95T ›› Serial RapidIO interconnect with dedicated onboard switch ›› Front panel and backplane Ethernet and RS-232 ports ›› Two hybrid PMC/XMC sites ›› Linux and VxWorks OS support packages ›› FPGA Development Kit provides IP cores for all FPGA peripherals

including Serial RapidIO endpoints

›› Supports industry standard development tools ›› Supported in Nallatech EA Builder development software ›› Supports industry standard development tools ›› Commercial (air-cooled) and rugged (air-cooled or conduction-

cooled) versions

Comprehensive software and FPGA IP core support is available for the VXS-610. The VXS-610 FPGA Development Kit (FDK) includes high-performance FPGA IP cores for all FPGA interfaces and peripherals. Software Board Support Packages (BSPs) are available for VxWorks and Linux operating systems. As part of the scalable Rugged Embedded VME and XMC series of products from Nallatech, the VXS-610 is complemented by further PMC/XMC mezzanines, processing engines, and application development tools.

For more information, contact: contact@nallatech.com

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FPGA

Software and development tools

DSP-FPGA.com

Resource Guide 2008-09

Annapolis Micro Systems, Inc. 190 Admiral Cochrane Drive, Suite 130 • Annapolis, MD 21401 410-841-2514

www.annapmicro.com CoreFire

Develop your application very quickly and easily with our CoreFire™ FPGA Application Builder, which transforms the FPGA development process, making it possible for theoreticians to easily and quickly build and test their algorithms on the real hardware that will be used in the field. Use CoreFire’s graphical interface to drag and drop library elements onto the design window. Modify your input and output types, numbers of bits, and other core variables by changing module parameters with pull-down menus. The modules automatically provide correct timing and clock control. Insert debug modules to report actual hardware values for hardware-in-the-loop debugging. Hit the Build button to check for errors and as-built core sizes and to build an encrypted EDIF file. Use the Xilinx ISE tool to place and route each FPGA design. Modify and use the jar file or the C program created by the CoreFire Build to load your new file into your WILDSTAR and I/O card hardware. Use the CoreFire Debugger to view and modify register and memory contents in the FPGA and to step through the dataflow of your design running in the real physical hardware. Our extensive IP and board support libraries contain more than 1,000 proven, reusable high-performance cores, including FIR and CIC filters, a channelizer, and the world’s fastest FFT. We support conversion between data types: bit, signed and unsigned integers, single precision floating point, integer and floating point complex, and arrays. A few of the newly added array cores include array composition and decomposition; slice, parallelize, serialize, repack, split, merge, reorder, rotate, and concatenate transformations; matrix math, sliding windows, and convolutions. The combination of our COTS hardware and CoreFire enables our customers to make massive improvements in processing speed while achieving significant savings in size, weight, power, person-hours, dollars, and calendar time to deployment.

For more information, contact: wfinfo@annapmicro.com

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FEATURES ›› Dataflow-based – automatically generates intermodule control

fabric

›› Drag-and-drop graphical interface ›› Work at high conceptual level – concentrate on solving algorithmic

problems

›› Hardware-in-the-loop debugging ›› More than 1,000 modules incorporate years of application experience ›› Reduce risk with COTS boards and software ›› Save time to market ›› Save development dollars ›› Easily port completed applications to new technology chips ›› and boards ›› Training and custom application development available ›› Achieve world-class performance; WILD solutions outperform the

competition

›› Annual node locked or networked license; includes customer sup-

port and updates

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Resource Guide 2008-09

Software and development tools

FPGA

Synopsys 600 West California Avenue • Sunnyvale, CA 94086 408-215-6000

www.synopsys.com Synplify Premier

Synopsys' Synplify Premier software is the ultimate FPGA implementation environment. It provides a comprehensive suite of tools and technologies for advanced FPGA designers as well as ASIC prototypers targeting a single FPGAbased prototype. The Synplify Premier solution addresses the most challenging aspects of FPGA design including timing closure, logic verification, IP usage, ASIC compatibility, DSP implementation, debug, and tight integration with FPGA vendor backend tools. DSP functionality within FPGAs continues to rise. Synplify Premier has DSP-aware mapping technology to take full advantage of the dedicated DSP structures and memories built into today's modern FPGAs. Synplify Premier is designed to work seamlessly with Synplicity's ESL synthesis tool (Synplify DSP).

FEATURES ›› Graph-based physical synthesis – fast timing closure and a push-

button performance boost of up to 20 percent

›› RTL-based Verification Technology – offers the fastest method of

finding functional errors in a design thanks to simulator-like visibility into a live, running FPGA with real-world stimulus ›› Automatic handling of DSP functions – infers DSP functions from RTL and maps into vendor’s DSP hardware (such as MAC) ›› ASIC Design-style support – built-in gated clock conversion and a DesignWare® compatible library enables ASIC code to be implemented into an FPGA without modification ›› Lightning-fast compile times – synthesizes even the largest design in a fraction of the time of other tools

For more information, contact: info@synplicity.com

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SP-FPGA.com Resource Guide 2008-09 DSP-FPGA.com

Data Acquisition

Hardware

Lyrtech

2800 Louis-Lumière Street, Suite 100 • Quebec City Canada G1P 0A4 418-877-4644

www.lyrtech.com VHS-ADC

The VHS-ADC is a high-speed, multichannel acquisition platform. It is equipped with eight phase-synchronous 105 MHz ADCs and a high-capacity LX or SX Virtex-4 FPGA. It comes with SDRAM for data storage and an expansion connector to add eight input or output channels, or several gigabytes of DDR2 SDRAM for simultaneous recording. Combined with additional DSP-FPGA processing platforms such as the SignalMaster Quad/Dual, the VHS-ADC becomes a complete and very high-performance IF/baseband solution. It can also be combined with the VHS-DAC to provide an end-to-end chain for high-speed processing on up to 16 channels (or more with additional platforms). Two coupling options (AC/DC) are offered to better fit with your MIMO, medical imaging and other applications.

For more information, contact: info@lyrtech.com

FEATURES ›› 6U CompactPCI, eight-channel 14-bit ADCs at 105 MSps ›› Mezzanine expansion site to support more channels or memory,

allowing multichannel recording

›› Outstanding clock synchronization allowing phase-synchronous

acquisition

›› Onboard, high-speed LX/SX Virtex-4 FPGA ›› Sustained 8-Gbps raw data RX/TX RapidCHANNEL ports for

expansion

›› Support for model-based design flow (MATLAB and Simulink)

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Hardware

Data Acquisition

Resource Guide 2008-09

Annapolis Micro Systems 190 Admiral Cochrane Drive, Suite 130 • Annapolis, MD 21401 410-841-2514

www.annapmicro.com

WILDSTAR 5 for IBM Blade Perfect Blend of Processors and Xilinx Virtex-5 FPGAs. Eleventh Annapolis Generation. Direct Seamless Connections – No data reduction between: external sensors and FPGAs, FPGAs and processors over IB or 10 Gb Ethernet backplane, FPGAs and standard output modules. Ultimate Modularity – From zero to six Virtex-5 processing FPGA/memory modules, and two Virtex-5 I/O FPGAs. Accepts one or two standard Annapolis WILDSTAR 4/5 I/O mezzanines: Quad 130 MSps through Quad 500 MSps A/D, 1.5 GSps through 2.2 GSps A/D, Quad 600 MSps DAC, InfiniBand, 10 Gb Ethernet, SFPDP. Fully Integrated into the IBM Blade Management System – Abundant power and cooling to ensure maximum performance. Annapolis Micro Systems, Inc. is a world leader in high- performance COTS FPGA-based processing for radar, sonar, SIGINT, ELINT, Digital Signal Processing, FFTs, communications, software radio, encryption, image processing, prototyping, text processing, and other processing intensive applications. We support our board products with a standardized set of drivers, APIs, and VHDL simulation models. Develop your application very quickly with our CoreFire™ FPGA Application Builder, which transforms the FPGA development process, making it possible for theoreticians to easily build and test their algorithms on the real hardware that will be used in the field. CoreFire, based on dataflow, automatically generates distributed control fabric between cores. Our extensive IP and board support libraries contain more than 1,000 cores, including floating point and the world’s fastest FFT. A graphical user interface for design entry supports hardware-in-the-loop debugging, and provides proven, reusable, high-performance IP modules. WILDSTAR 5 for IBM Blade, with its associated I/O cards, provides extremely high overall throughput and processing performance. The combination of our COTS hardware and CoreFire allows our customers to make massive improvements in processing speed, while achieving significant savings in size, weight, power, person-hours, dollars, and calendar time to deployment.

FEATURES ›› From two to eight Virtex-5 FPGA processing elements – LX110T,

LX220T, LX330T, FX100T, FX130T, or FX200T. Six are pluggable with power module and memory ›› Up to 10.7 GB DDR2 DRAM per WILDSTAR 5 for IBM Blade Board ›› 144 x 144 crossbar. 3.2 Gb per line. Two external PPC 440s – 1 per each I/O FPGA ›› Full CoreFire Board Support Package for fast, easy application development ›› VHDL model, including source code for hardware interfaces and ChipScope access ›› Available in both commercial and industrial temperature grades ›› Proactive thermal management system – board level current measurement and FPGA temperature monitor, accessible through Host API ›› Includes one-year hardware warranty, software updates, and customer support ›› Blade management controller. USB, RS-485, Ethernet, KVM, 16 RIO, Switch to 1 GbE over backplane ›› Save time and effort. Reduce risk with COTS boards and software ›› We offer training and exceptional special application development support, as well as more conventional support ›› Famous for the high quality of our products and our unparalleled dedication to ensuring that the customer’s applications succeed

Achieve world-class performance; WILDSTAR solutions outperform the competition. For more information, contact: wfinfo@annapmicro.com

2008-09 Annual Resource Guide

DSP-FPGA.com

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Data Acquisition

Hardware

Jacyl Technology 3909 Fourier Drive, Suite B • Fort Wayne, IN 46818 800-590-6067

www.jacyl.com

Mission Workstation The Mission Workstation is a multi-computer ruggedized workstation for applications that demand the best. The Mission Workstation features 4 completely independent computer systems housed in a single 19" 6U rack mount enclosure. The Mission Workstation can be ordered with a standard set of options for each computer, or each individual computer within the Mission Workstation can be custom configured from our factory for CPU processing capability, video processing capability, I/O capabilities, and/ or OS configurations to meet your system requirements. The Mission Workstation can also be factory configured as a single cluster computer, harnessing the full potential of up to 16, 3 GHz Intel processors and 32 GB of DDR2 RAM. This parallel processing capability is available to meet the most demanding applications. The Mission Workstation has been specially designed to be a ruggedized multi-computer system with unique features such as custom air filters located on all air cooling inlets, specially designed internal dual ball bearing fan cooling system for each individual computer, steel reinforced internal structure, anodized aluminum enclosure, removable ruggedized hard-drive caddies, full access to all CPU, video, and I/O ports from the front of the unit, and reinforced internal cable routing.

FEATURES ›› All CPU, video, and I/O connectors are located on the front of the

unit for convenient access

›› All air cooling intakes incorporate a ruggedized air/EMI filter system ›› Every system is production tested to a fully powered 3G NAVMAT

vibration test and Environmental Stress Screening (ESS) test

›› Can be factory configured to be powered from a DC or AC input

source

›› All hard drives are removable and are enclosed within ruggedized

The Mission Workstation is designed to be utilized in the most demanding applications. Every production Mission Workstation is tested to a 3G NAVMAT vibration profile with the unit fully powered and subjected to full temperature range Environmental Stress Screening (ESS) with the unit fully powered. Other production testing is performed on each Mission Workstation such as 100 percent loaded CPU duration testing, 100 percent video processor duration test, performance verification testing, and burn-in testing all to ensure that the Mission Workstation is the most ruggedized and reliable multi-computer workstation available. Jacyl Technology is the OEM of the Mission Workstation and provides an off-the-shelf or custom configuration of the Mission Workstation to meet the requirements of your system design.

For more information, contact: sales@jacyl.com

caddies

›› Each Mission Workstation is functionally tested from -10 °C to +60 °C ›› Each computer can be independently configured with a Core 2 Dual or

Core 2 Quad Intel processor and processor clock speeds up to 3 GHz

›› Each individual computer has 2 PCI, 1 PCI x6 or 2 PCI x8, 2 GbE, 4

SATA, up to 2 ESATA, up to 12 USB 2.0 ports and up to 32 GB RAM

›› Each of the 4 individual computers supports 32- or 64-bit and

operating system configurations

›› Can be factory configured as 4 individual computer systems or one

cluster/parallel computer

›› When factory configured as a cluster computer, the processing

power would include 16, 3 GHz processors, 32 GB RAM, and 5.7 TB HDD space ›› Each individual computer supports SATA II 300 (dependent upon CPU selection) and RAID 0, 1, 5, 10 controller implementations

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Hardware

Test and Instrumentation

DSP-FPGA.com

Resource Guide 2008-09

ITCN, Inc. 591 Congress Park Drive • Dayton, OH 45459 800-439-4039

www.itcn-test.com SystemTrace Applications:

• Software Test and Evaluation • System Integration • Maintenance • Performance Monitoring • Operational Test (Land, Sea, Air) • Diagnostics and Prognostics Now there is an easier way to monitor, analyze and troubleshoot complex embedded systems. SystemTrace from ITCN provides a complete instrumentation system for acquiring data from an embedded system. It includes modules that monitor data on various types of media such as computer backplanes, serial data buses, parallel data buses and discrete signal lines. Current modules monitor VME backplanes and MIL-STD-1553 embedded systems. SystemTrace is a scalable, reconfigurable platform for instrumentation of data buses. It combines unified controls, timing, and trigger features to provide seamless integration of multiple instrumentation modules. SystemTrace uses Real-Time Non-Intrusive (RTNI) techniques so that the act of monitoring does not affect the system's operation. SystemTrace architecture consists of a PC workstation, a communications network, and one or more instrumentation modules. Instrumentation modules are the central component of SystemTrace. Multiple modules can be distributed throughout the system under test. When multiple data streams are being monitored simultaneously, the modules' Trigger Sync Logic allows precise time-correlation of collected data and complex triggering across multiple monitors and data streams. SystemTrace can help software developers and system integrators dramatically save time and reduce costs. Users can incorporate mission and performance monitoring for real-time or post-run analysis. By collecting data across a system of multiple heterogeneous data streams, SystemTrace can provide insight into complex embedded systems unlike any other product available today.

For more information, contact: sales@itcninc.com

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FEATURES ›› A system-wide view of operations correlated in time aids analysis ›› RTNI monitoring does not affect system operation during measure-

ments, thereby giving accurate results

›› Supports the entire life-cycle of the instrumented embedded system,

reducing instrumentation costs

›› Common GUI for dissimilar targets saves time and training invest-

ment

›› Programmable data collection scenarios for user controlled param-

eters

›› Collection of only "data of interest" increases length of observation

time and decreases analysis time

›› Scalable architecture supports changing requirements ›› Remote monitoring capability saves time and money ›› Simultaneous monitoring of multiple data streams gives a system-

wide view of data

›› Complex state machine, filters, and triggers for in-depth testing and

analysis

›› Long-term, large volume data storage ›› Easy to use software has flexible viewing and reporting options ›› View data collection and analyze it in real-time ›› Supports entire life-cycle of the instrumented embedded system,

reducing instrumentation expense

›› Time-correlated data collection across up to 64 Probes (32 modules) ›› Up to 256 Data Element Filters for each channel ›› Cross module triggers provide internal and external triggering of

state machine and events

›› Programmable and reusable data collection scenarios

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Resource Guide 2008-09

I/O: Analog

Hardware

Annapolis Micro Systems, Inc. 190 Admiral Cochrane Drive, Suite 130 • Annapolis, MD 21401 410-841-2514

www.annapmicro.com 2.0 GSps 10-bit A/D

The Annapolis Single Channel 2.0 GSps A/D I/O Card provides one 2.0 GHz A/D input with a resolution of 10 bits. The board has one e2v AT84AS004 that is fed by an onboard analog input circuit, which converts the single ended 50 ohm SMA input into differential signals for the ADC. There is a universal single ended 50 ohm SMA clock input and a high-precision trigger input allowing multiple A/D I/O cards to be synchronized together. Synchronization of A/D I/O cards can be facilitated by the Annapolis 4 or 8 Channel Clock Distribution Boards. In concert with the WILDSTAR 4 or WILDSTAR 5 FPGA processing main boards, this mezzanine board supplies userconfigurable real-time continuous sustained processing of the full data stream. Up to two A/D and up to two Serial I/O cards can reside on each WILDSTAR 4 or WILDSTAR 5 VME/VXS or IBM Blade main board or up to one A/D and up to one Serial I/O card on each PCI-X or PCI Express main board. Our boards run on many different operating systems. We support our board products with a standardized set of drivers, APIs, and VHDL simulation models. VHDL source is provided for the interfaces to A/Ds, D/As, DRAM/SRAM, LAD bus, I/O bus, and PPC Flash. CoreFire™ users will have the usual CoreFire Board Support Package. The combination of our COTS hardware and our CoreFire FPGA Application Development tool allows our customers to make massive improvements in processing speed, while achieving significant savings in size, weight, power, person-hours, dollars, and calendar time to deployment. Annapolis Micro Systems, Inc. is a world leader in highperformance COTS FPGA-based processing for radar, sonar, SIGINT, ELINT, Digital Signal Processing, FFTs, communications, software radio, encryption, image processing, prototyping, text processing, and other processing intensive applications.

FEATURES ›› One e2v AT84AS004 (2.0 GHz, 10-bit) A/D ›› Four SMA front panel connectors: one 50 ohm analog input, one

single ended 50 ohm clock input, or differential 1.65 V LVPECL clock input ›› One high-precision trigger input with Fs precision. High-precision trigger input – 1.65 V LVPECL, 2.5 V LVPECL, 3.3 V LVPECL ›› Analog input bandwidth is 100 KHz-3.0 GHz ›› I/O card plugs onto WILDSTAR 4 or 5 VME/VXS/PCI-X/PCI Express/ IBM Blade main boards ›› JTAG, ChipScope, and Serial Port access ›› Full CoreFire Board Support Package for fast, easy application development ›› VHDL model, including source code for board level interfaces ›› Proactive thermal management system ›› Includes one-year hardware warranty, software updates, and customer support ›› We offer training and exceptional special application development support, as well as more conventional customer support ›› Designed and manufactured in the USA

Annapolis is famous for the high quality of our products and for our unparalleled dedication to ensuring that the customer’s applications succeed.

For more information, contact: wfinfo@annapmicro.com

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Hardware

I/O: Analog

Resource Guide 2008-09

Annapolis Micro Systems, Inc. 190 Admiral Cochrane Drive, Suite 130 • Annapolis, MD 21401 410-841-2514

www.annapmicro.com

Quad 600 MSps 16-bit DAC The Annapolis Quad 600 MSps 16-bit DAC I/O Card provides up to four 16-bit output streams at up to 600 MSps each. The board has four Max 5891 16-bit DACs. Use the high precision trigger to synchronize the four onboard DAC channels or to synchronize DACs between multiple boards (<1 Fs period). The Quad 600 MSps board has six SMA front panel connectors: four single-ended DAC outputs, a high precision trigger input with Fs precision, and a universal single ended 50 ohm clock input. It has excellent SFDR and IMD performance, ultra low skew and jitter saw based clock distributions, and mainboard PCLK sourcing capability. In concert with the WILDSTAR 4 or WILDSTAR 5 FPGA processing main boards, this mezzanine board supplies userconfigurable real-time Analog to Digital conversion and digital output. Up to two A/D or D/A and up to two Serial I/O cards can reside on each WILDSTAR 4 or WILDSTAR 5 VME/VXS or IBM Blade main board, or up to one A/D or D/A and up to one Serial I/O card on each PCI-X or PCI Express main board. Our boards run on many different operating systems. We support our board products with a standardized set of drivers, APIs, and VHDL simulation models. VHDL source is provided for the interfaces to A/Ds, D/As, DRAM/SRAM, LAD bus, I/O bus, and PPC Flash. CoreFire users will have the usual CoreFire Board Support Package. The combination of our COTS hardware and our CoreFire FPGA Application Development tool allows our customers to make massive improvements in processing speed, while achieving significant savings in size, weight, power, person-hours, dollars, and calendar time to deployment. Annapolis Micro Systems, Inc. is a world leader in highperformance COTS FPGA-based processing for radar, sonar, SIGINT, ELINT, Digital Signal Processing, FFTs, communications, software radio, encryption, image processing, prototyping, text processing, and other processing intensive applications.

FEATURES ›› Four 16-bit Analog to Digital Converters: Max 5891 ›› Six SMA front panel connectors: four single ended DAC outputs,

one high-precision trigger input with Fs precision, and one universal single ended 50 ohm clock input ›› High-precision trigger input manufacturing options – 1.65 V LVPECL, 2.5 V LVPECL, 3.3 V LVPECL ›› I/O card plugs onto WILDSTAR 4 or 5 VME/VXS/PCI-X/PCI Express/ IBM Blade main boards ›› JTAG, ChipScope, and Serial Port access ›› Full CoreFire Board Support Package for fast, easy application development ›› VHDL model, including source code for hardware interfaces and ChipScope access ›› Industrial temperature range ›› Proactive thermal management system ›› Save time and effort. Reduce risk with COTS boards and software ›› Achieve world-class performance; WILD solutions outperform the competition ›› Includes one-year hardware warranty, software updates, and customer support; training available

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I/O: Analog

Hardware

Annapolis Micro Systems, Inc. 190 Admiral Cochrane Drive, Suite 130 • Annapolis, MD 21401 410-841-2514

www.annapmicro.com

WS4 1.5/2.3/4.0 GSps 12-bit DAC The Annapolis Dual Channel 1.5/2.3/4.0 GSps D/A I/O Card provides one or two 12-bit digital output streams at up to 4.0 GSps. The board has one or two Max 19693 for 4.0 GSps, Max 19692 for 2.3 GSps, or Max 5859 for 1.5 GSps. The Dual Channel DAC board has five SMA front panel connectors: two single ended DAC outputs, a high-precision trigger input with Fs precision, and a universal single or double ended 50 ohm clock input. It has excellent gain flatness in the first three Nyquist zones, ultra-low skew and jitter saw based clock distributions, and main board PCLK sourcing capability. In concert with the WILDSTAR 4 or WILDSTAR 5 FPGA processing main boards, this mezzanine board supplies user-configurable real-time Analog to Digital conversion and digital output. Up to two A/D or D/A and up to two Serial I/O cards can reside on each WILDSTAR 4 or WILDSTAR 5 VME/VXS or IBM Blade main board, or up to one A/D or D/A and up to one Serial I/O card on each PCI-X or PCI Express main board.

FEATURES ›› One or two 12-bit Analog to Digital Converters: Max 19693 for

4.0 GSps, Max 19692 for 2.3 GSps, or Max 5859 for 1.5 GSps

Our boards run on many different operating systems. We support our board products with a standardized set of drivers, APIs, and VHDL simulation models. VHDL source is provided for the interfaces to A/Ds, D/As, DRAM/SRAM, LAD bus, I/O bus, and PPC Flash. CoreFire™ users will have the usual CoreFire Board Support Package. The combination of our COTS hardware and our CoreFire FPGA Application Development tool allows our customers to make massive improvements in processing speed, while achieving significant savings in size, weight, power, person-hours, dollars, and calendar time to deployment. Annapolis Micro Systems, Inc. is a world leader in highperformance COTS FPGA-based processing for radar, sonar, SIGINT, ELINT, Digital Signal Processing, FFTs, communications, software radio, encryption, image processing, prototyping, text processing, and other processing intensive applications.

›› Five SMA front panel connectors: two single ended DAC outputs,

one high precision trigger input with Fs precision, and one universal single or double ended 50 ohm clock input ›› High-precision trigger input manufacturing options – 1.65 V LVPECL, 2.5 V LVPECL, 3.3 V LVPECL ›› I/O card plugs onto WILDSTAR 4 or 5 VME/VXS/PCI-X/PCI Express/ IBM Blade main boards ›› JTAG, ChipScope, and Serial Port access ›› Proactive thermal management system. Available in industrial temperature range ›› Full CoreFire Board Support Package for fast, easy application development and technology refresh ›› VHDL model, including source code for hardware interfaces ›› Includes one-year hardware warranty, software updates, and customer support. Reduce risk with COTS ›› We offer training and exceptional special application development support, as well as more conventional customer support ›› Annapolis is famous for the high quality of our products and for our unparalleled dedication to ensuring that customers’ applications succeed

For more information, contact: wfinfo@annapmicro.com

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Hardware

I/O: Analog

Resource Guide 2008-09

Annapolis Micro Systems, Inc. 190 Admiral Cochrane Drive, Suite 130 • Annapolis, MD 21401 410-841-2514

www.annapmicro.com

WS4 Quad 250/400/500 MSps A/D The Annapolis Quad Channel 250/400/500 MSps A/D I/O Card provides four A/D inputs with converter speeds of up to 250, 400, or 500 MHz and resolutions of 13, 14, or 12 bits respectively. The board has four A/D converters from TI (ADS5444, ADS5474, or ADS5463) fed by onboard analog input circuits that convert the single ended 50 ohm SMA input into differential signals for the ADC. There is an onboard ultra-low jitter and skew clock distribution circuit to allow all four channels on a single A/D I/O board to be synchronized together. There is also an external clock input and a trigger input allowing multiple A/D I/O cards to be synchronized together. Synchronization of A/D I/O cards can be facilitated by the Annapolis 4 or 8 Channel Clock Distribution Boards. In concert with the WILDSTAR 4 or WILDSTAR 5 FPGA processing main boards, this mezzanine board supplies userconfigurable real-time continuous sustained processing of the full data stream. Up to two A/D I/O cards can reside on each WILDSTAR 4 or WILDSTAR 5 VME/VXS or IBM Blade main board or reside on one A/D I/O card on each PCI-X or PCI Express main board. Annapolis Micro Systems, Inc. is a world leader in highperformance COTS FPGA-based processing for radar, sonar, SIGINT, ELINT, Digital Signal Processing, FFTs, communications, software radio, encryption, image processing, prototyping, text processing, and other processing intensive applications. Our boards run on many different operating systems. We support our board products with a standardized set of drivers, APIs, and VHDL simulation models. VHDL source is provided for the interfaces to A/Ds, D/As, DRAM/SRAM, LAD bus, I/O bus, and PPC Flash. CoreFire™ users will have the usual CoreFire Board Support Package. The combination of our COTS hardware and our CoreFire FPGA Application Development tool allows our customers to make massive improvements in processing speed, while achieving significant savings in size, weight, power, person-hours, dollars, and calendar time to deployment.

For more information, contact: wfinfo@annapmicro.com

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FEATURES ›› Four TI A/D converters of one of the speed and bit size types:

ADS5444 250 MSps 13-bits, ADS5474 400 MSps 14-bits, ADS5463, 500 MSps 12-bits ›› Analog input bandwidths of up to: 500 MHz for the 250 MSps A/D board, 1,400 MHz for the 400 MSps A/D board, 2,000 MHz for the 500 MSps A/D ›› Six SMA front panel connectors: four 50 ohm analog inputs, one single ended 50 ohm clock input, one trigger input ›› Onboard ultra-low jitter and skew clock distribution circuit to allow synchronization of all four channels on a single I/O card ›› I/O card plugs onto WILDSTAR 4 or 5 VME/VXS/PCI-X/PCI Express/ IBM Blade main boards ›› JTAG, ChipScope, and Serial Port access ›› Proactive thermal management system. Available in both commercial and industrial temperature ranges ›› Full CoreFire Board Support Package for fast, easy application development and technology refresh ›› VHDL model, including source code for hardware interfaces ›› Includes one-year hardware warranty, software updates, and customer support. Reduce risk with COTS ›› We offer training and exceptional special application development support, as well as more conventional customer support ›› Annapolis is famous for the high quality of our products and for our unparalleled dedication to ensuring that customers’ applications succeed

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Resource Guide 2008-09

I/O: Digital

Hardware

Annapolis Micro Systems, Inc. 190 Admiral Cochrane Drive, Suite 130 • Annapolis, MD 21401 410-841-2514

www.annapmicro.com SFPDP UNI6 I/O

Annapolis Micro Systems Inc.’s FPGA-based WILDSTAR family provides 24 SFPDP channels per VME slot. The Annapolis SFPDP cards (UNI3 or UNI6) come with an easy to use Serial FPDP interface supporting up to 12 lanes of 2.5 Gb full duplex data. Three frame types are supported: Normal Data Fiber Frame, Sync Without Data Fiber Frame, and Sync with Data Fiber Frame in Point-to-Point Mode. The card has three individually configurable, industry- standard 4X connectors, providing four lanes per connector, with dedicated signal conditioners to ensure clean communication. It supports up to 7.5 GB full duplex per I/O card and a wide variety of readily available copper and fiber cables. Up to two serial I/O cards and two LVDS I/O cards can reside on each WILDSTAR 4 or WILDSTAR 5 VME/VXS main board, with half that number for the PCI-X or PCIe. The SFPDP card (UNI6) supports RocketIO protocol at up to 75 Gb full duplex per I/O card, three ports of 10G full duplex InfiniBand per I/O card, or 10G full duplex Ethernet per I/O card. No other FPGA board vendor can match the volume of data we can send straight into the heart of the processing elements and then straight back out again.

FEATURES ›› Three individually configurable 4X connectors – four lanes per

connector ›› Up to four 2.5 Gb full duplex Serial FPDP ports per connector ›› Up to 25 Gb full duplex RocketIO per connector ›› Up to 10 Gb full duplex InfiniBand per connector

An FPGA-based high-performance processing engine thrives on data streaming in and out at high rates of speed. The FPGAs should be part of a balanced and unified system architecture, providing maximum performance, with memory, processing power, and I/O speeds designed and integrated for performance, scalability, and growth.

›› Up to 10 Gb full duplex Ethernet per connector

Annapolis Micro Systems, Inc.’s WILDSTAR 4 (Xilinx Virtex-4 based) and WILDSTAR 5 (Xilinx Virtex-5 based) families of FPGA-based processing boards also support an extensive set of extremely high-quality A/D and D/A boards.

›› Includes one-year hardware warranty, software updates, and

›› Optional onboard oscillators for other line rates like Fibre Channel ›› I/O card plugs onto WILDSTAR 4 or 5 VME/VXS/IBM Blade Chassis/

PCI-X/PCI Express main board ›› JTAG, ChipScope, and Serial Port access ›› Proactive thermal management system. Available in both

commercial and industrial temperature grades

Annapolis Micro Systems, Inc. is a world leader in highperformance COTS FPGA-based processing for radar, sonar, SIGINT, ELINT, Digital Signal Processing, FFTs, communications, software radio, encryption, image processing, prototyping, text processing, and other processing intensive applications.

customer support ›› We offer training and exceptional special application development

support, as well as more conventional customer support ›› Full CoreFire Board Support Package for fast, easy application

development ›› VHDL model, including source code for hardware interfaces

Annapolis is famous for the high quality of our products and for our unparalleled dedication to ensuring that the customer’s applications succeed.

For more information, contact: wfinfo@annapmicro.com

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Hardware

Image Processing

Resource Guide 2008-09

Xilinx, Inc. 2100 Logic Drive • San Jose, CA 95124 408-559-7778

www.xilinx.com

The XtremeDSP™ Video Starter Kit – Spartan®-3A DSP FPGA Edition The XtremeDSP Video Starter Kit supplies you with everything you need to accelerate your video designs using reconfigurable hardware without requiring existing knowledge of VHDL/Verilog design flows. Build Fast and Flexible Video Systems This programmable platform provides you with just the right balance of hardware resources to enable you to craft the optimal combination of performance, flexibility, and cost for video applications. You can create custom accelerators for your existing video system that interface to digital media processors. Platform FPGAs for Video The kit helps you to meet all of your video system performance requirements. Hardware architectures can be tailored to meet your specific needs while fully leveraging the system features of the device. Processor Friendly Design Flow That Does Not Require RTL Complete video systems can be quickly constructed without requiring existing knowledge of VHDL/Verilog design flows. An embedded base system provides a familiar starting point from which existing processor-based video applications can be ported, or new designs created. Custom video accelerator blocks can also be created using the popular Simulink® modeling environment from The Mathworks.™

FEATURES ›› Spartan®-3A DSP 3400A FPGA development board ›› FMC-Video I/O daughter card, a Micron VGA CMOS Camera Module,

and a comprehensive set of Xilinx Tools

›› One year entitlement to Xilinx EDK and System Generator ›› The Spartan-3A DSP platform consists of two devices, the

XC3SD3400A and the XC3SD1800A

›› The XC3SD3400A device featured in the XtremeDSP Video Starter

Kit delivers over 30 GMACps

To learn more and order your XtremeDSP Video Starter Kit, visit www.xilinx.com/vsk_s3.

For more information, contact: lisa.hartman@xilinx.com

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Data Acquisition

Hardware

Sheldon Instruments 10393 San Diego Mission Road, Suite 202 • San Diego, CA 92108 619-282-6700

www.sheldoninst.com

SI-MOD6600 Multifunction IO Modules The SI-MOD66xx is a family of compact, high resolution, multi-function data acquisition and control modules that plug into any SI-DSP carrier processor card. Multiple I/Os include a 16-bit resolution and high channel count analog I/O section, and a reconfigurable digital I/O section with bidirectional ports, quadrature encoders, and pulse I/O lines. An XC3S500E Spartan-3E FPGA contains a timing and control unit that houses a crossbar switch for routing timing sources (counters/timers/DDS/clocks) to any section, and performs auto-zeroing of AC/DC errors stored in EEPROM. For custom development, comprehensive APIs/driver libraries and examples are supplied with all projects and related source code. For turnkey development of real time applications, QuVIEW and QuBASE are sets of DSP resident libraries for LabVIEW and Visual Basic.

FEATURES ›› Up to 64 Analog Inputs, 4 ADCs x 250 KHz sampling, 16-bit, 1-100

gains, ±10 VIN

›› Up to 32 analog outputs, 180 KHz update rates, 16-bit, ±10 VOUT ›› 40 digital I/Os: 2 x 16-bit ports, 2 quadrature encoders, 2 pulse I/Os ›› Flexible timing: 2 DDSes, 4 event counters, and routing matrix allow-

ing a myriad of clocking schemes

›› Small size: 3.7" x 3.7" (94 cm x 94 cm) mates to all SI-DSP carriers

(PCI-104/PCIe-104, PCI/PCI Express, Ethernet/USB standalone)

›› Turnkey software development with QuVIEw/QuBASE libraries to

accelerate LabVIEW/Visual Basic; custom application support with comprehensive APIs/driver libraries and examples supplied with all projects and related source

For more information, contact: info@sheldoninst.com

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SP-FPGA.com Resource Guide 2008-09 DSP-FPGA.com

Design

Services

Fidus Systems Inc. 900 Morrison Drive, Suite 203 • Ottawa, Ontario K2H 8K7 Canada 866-883-4387

www.fidus.com

Electronic Product Development Fidus Systems develops electronic products for a wide range of industries including aerospace, defense, consumer, medical, industrial, semiconductors, and telecommunications. Whether it is turnkey product development or targeted assistance on a project, Fidus has the bench strength to offer highly qualified and experienced engineers. As a design partner, Fidus offers companies greater flexibility and capability in their product development with access to the expertise, process, and tools to successfully move their concepts to revenue-generating products. Fidus uses proven product development and design methodologies combined with a comprehensive suite of tools and equipment. Fidus has delivered on more than 600 products and projects for 125 customers across North America.

For more information, contact: info@fidus.com

CAPABILITIES ›› System design and architecture ›› Hardware design ›› DSP/FPGA/ASIC design ›› Software/firmware design ›› Wireless/RF design ›› PCB layout ›› Signal integrity/EMC ›› Prototype design and testing ›› Regulatory compliance ›› Environmental and reliability ›› RoHS compliance/component obsolescence RSC# 38782 @ www.dsp-fpga.com/rsc

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Software

Software and development tools

DSP-FPGA.com

Resource Guide 2008-09

Altera Corporation 101 Innovation Drive • San Jose, CA 95134 408-544-7000

www.altera.com

Altera DSP Builder Digital Signal Processing (DSP) system design in Altera® FPGAs requires both high-level algorithm development and HDL development tools. Altera’s DSP Builder integrates these tools by taking the algorithm development, simulation, and verification capabilities of The MathWorks MATLAB/Simulink system-level design tools and combining them with VHDL synthesis, simulation, and Altera’s Quartus® II development tool. Using DSP Builder, you can target your design to any Altera FPGA – including the latest device architectures such as the 40 nm Stratix® IV family – and effortlessly retarget it if your needs change. Altera’s DSP Builder technology shortens DSP design cycles by helping you create the hardware representation of a DSP design in an algorithm-friendly development environment. With this tool, you can quickly go from system definition and simulation using industry-standard MATLAB/Simulink tools to system implementation. The DSP Builder Signal Compiler block reads Simulink Model Files (.mdl) that are built using DSP Builder and MegaCore® blocks and generates VHDL files and Tcl scripts for synthesis, hardware implementation, and simulation. DSP Builder features the Advanced Blockset capability supporting timing-driven Simulink synthesis, which is critical for designing multi-channel signal processing data paths in applications such as RF processing in wireless applications and SDR for military applications. This technology lets you achieve high-performance design implementations running at near-peak FPGA performance in a matter of minutes compared to the hours, if not days, required to hand-optimize HDL code.

FEATURES ›› Industry’s premier DSP design tool based on The MathWorks

MATLAB/Simulink design flow

›› Creates a seamless bridge between the MATLAB/Simulink environ-

ment and the Altera Quartus II software

›› Only design tool that generates timing-optimized HDL from a high-

level Simulink description of the system

›› Automates the tedious part of DSP design: control plane logic and

pipeline stage generation

›› Optimized for multi-channel DSP data paths ›› Effortless device retargeting, for example, from Stratix series FPGAs

to Cyclone® series FPGAs, including the latest 40 nm Stratix IV family

›› Comes with a suite of reference designs for digital up/down conver-

sion and multi-channel filters

The underlying high-level synthesis technology optimizes the untimed Simulink description into low-level, pipelined hardware targeted to your chosen FPGA and clock rate. The hardware is written out as plaintext VHDL, along with scripts that integrate with the Quartus II software and the ModelSim simulator. These features allow you to generate a high-quality implementation of your design without requiring intimate knowledge of the device architecture. The DSP Builder tool is available at www.altera.com/dsp. The tool comes with reference designs for WiMAX and WCDMA digital up/down converter designs as well as designs for multi-channel complex filters.

For more information, go to: www.altera.com/dsp

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Resource Guide 2008-09

DSP algorithm

Software

Synopsys 600 West California Avenue • Sunnyvale, CA 94086 408-215-6041

www.synplicity.com Synplify DSP

The Synplify DSP solution offers DSP algorithm designers and hardware engineers the most efficient way to get their algorithms into silicon. System and algorithm designers can quickly capture complex algorithmic behavior using the Synplify DSP library, which includes powerful modeling features such as vector arithmetic, fixed-point precision up to 128 bits, and a rich set of IP cores. Additionally, you can target FPGA or ASIC hardware from a single Simulink model. The Synplify DSP synthesis engine allows designers to automatically implement and explore area/speed-optimized RTL implementations from a single model. This eliminates the burden of hand-coding functions and architectural optimizations, achieves significantly faster design capture, speeds time to market, and enables rapid design exploration that results in improved quality and lower cost.

FEATURES ›› Unique Synplify DSP synthesis engine – Automatically creates

optimized algorithm RTL architectures from your DSP model

›› Powerful DSP synthesis optimizations – Exploration of speed/area/

device technology trade-offs without changing your DSP model

›› Comprehensive DSP library – With full multi-rate support and

advanced fixed-point quantization analysis

›› M-Control feature – Enables use of M-language for concise expres-

sion of complex state machine and control logic functionality

›› Vector support – Enables concise expression of parallel and multi-

channel algorithms common in wireless and video applications

›› Extensible IP – Easily create your own reusable, optimizable custom

DSP functions using Synplicity’s core IP library (blockset)

For more information, contact: info@synplicity.com

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Resource Guide 2008-09

Development tools

Altia, Inc.

7222 Commerce Center Drive, Suite 240 Colorado Springs, CO 80919 719-598-4299

www.altia.com

Altia DeepScreen Altia DeepScreen is a graphics code generator that converts Altia Design prototype graphics into deployable graphics code. By simply selecting the design objects that represent the display portion of a product and clicking on the “Generate Code” menu, ANSI C code is generated in seconds. This code can be generated for any RTOS that DeepScreen supports (Windows, Windows CE and .NET, UNIX, Linux, QNX, and more). DeepScreen will also generate code for a proprietary or limited RTOS and quickly integrate with an existing graphics library. Changes to interfaces can be accomplished quickly. Graphics code can be used on both high- and low-end targets – from Windows machines to FPGAs to 8-bit micros. DeepScreen saves programmers from the grunt work of graphics coding and allows developers to meet aggressive schedules. DeepScreen supports 8-, 16-, and 32-bit processors with fixed point or floating point arithmetic.

For more information, contact: info@altia.com

FEATURES ›› Easily try different targets – dialog driven choice of target RTOS ›› DeepScreen for Altera’s Nios® II Soft Core Processor is available in

two different versions. Contact Altia for details

›› Choice of code generation optimizations ›› Generates code for graphics, animation, stimulus, and control ›› From Altia Design select items for code generation ›› No limit to combination or number of objects that can be selected ›› Link in your application code and use your own main loop ›› Porting kit to generate code for currently unsupported OSs or GLs ›› Supports 8-, 16-, and 32-bit processors ›› Supports fixed point and floating point processors RSC# 32775 @ www.dsp-fpga.com/rsc

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Software

Development tools

Resource Guide 2008-09

Xilinx, Inc. 2100 Logic Drive • San Jose, CA 95124 408-559-7778

www.xilinx.com

ISE Design Suite 10.1 The ISE® Design Suite 10.1, the latest release of the industry-leading design tools from Xilinx, delivers the perfect combination of design performance and productivity. Whether your design requires a flexible embedded processing solution, a specialized flow for DSP development, or just optimal high-performance logic, the ISE Design Suite 10.1 can be configured to help you achieve your design goals quickly. Integrated Environment for Embedded Design The Embedded Development Kit (EDK) bundle is an integrated software solution for designing embedded processing systems. This pre-configured kit includes the award winning Platform Studio tool suite as well as all the documentation and IP that you require for designing Xilinx Platform FPGAs with embedded PowerPC® hard processor and/or MicroBlaze™ soft processor cores. Integrated Environment for DSP Design The ISE Design Suite 10.1 includes the XtremeDSP™ Development Tools Package as an option. Developers with little FPGA design experience can quickly create production quality FPGA implementations of DSP algorithms in a fraction of traditional RTL development times.

FEATURES ›› Meet your Deisgn Goals Faster:

–– One integrated front-to-back FPGA IP catalog and design tool suite with unified interoperability –– Domain specific design capture for DSP, embedded and logical design –– Accelerated system development via customization and integrated libraries of optimized IP ›› Achieve Optimal System Performance:

–– Design tools optimized to minimize area while maximizing performance for Virtex-5 and Spartan-3 family Platform FPGAs –– Designer control to streamline every component of your application, throughout the development process –– An integrated design environment delivering performance without compromising power ›› Access World Class FPGA Design Solutions

–– Logic design tools delivering optimal timing closure for higher performance, lower power designs –– Automated embedded design wizards to accelerate processing development and time-to-market –– DSP design flows and IP tailored for algorithm, system, and hardware developer

For more information, contact: lisa.hartman@xilinx.com

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Development tools

Software

Innovative Integration 2390-A Ward Avenue • Simi Valley, CA 93065 805-578-4260

www.innovative-dsp.com FrameWork Logic

Innovative’s powerful FrameWork Logic tools provide comprehensive support for FPGA signal processing development in MATLAB and RTL for Innovative Integration FPGA-equipped products. Experience dramatically-shortened development schedules while developing complex signal processing algorithms. Real-time “hardware-in-theloop” simulation brings your product to market faster! Experience the power of FrameWork Logic! See our Family of X5 & X3 modules within this guide. Download data sheets and pricing now!

FEATURES ›› MATLAB and VHDL board support packages ›› Comprehensive hardware support and tools for signal processing ›› Hardware interface layer design structure allows rapid integration

of application-specific code

›› Designed to support real-time signal processing and data acquisition ›› Reference designs illustrating hardware use

For more information, contact: sales@innovative-dsp.com

RSC# 33601 @ www.dsp-fpga.com/rsc

SP-FPGA.com Resource Guide 2008-09 DSP-FPGA.com

Integrated Systems

Software-Defined Radio

Lyrtech

2800 Louis-Lumière Street, Suite 10 • Quebec City Canada G1P 0A4 418-877-4644

www.lyrtech.com

SFF SDR Development Platform The Small Form Factor (SFF) Software-Defined Radio (SDR) Development Platform is a unique product that addresses the special portable SDR needs of the military, public safety, and commercial markets. It is designed around some of the latest DSP (DM6446) and FPGA (Virtex-4 SX35) technology – Lyrtech's area of expertise – as a low-cost, off-the-shelf, integrated hardware and software development solution.

FEATURES ›› Small form factor for easy portability with independent power moni-

Two optional high-level software development tools are offered with the SFF SDR: a model-based design kit, which gives access to Lyrtech development board interfaces from within the MATLAB/Simulink model-based design environment, and an SCA core framework. An optional GSM Wireless Base Transceiver Station (BTS) reference design, ideal for femto BTS prototyping, is also offered.

toring for each processor

›› Seamless hardware and software integration from baseband to

antenna

›› Supports model-based design tools, accelerating prototyping ›› Integrates troubleshooting and hardware-in-the-loop co-simulation

capabilities

›› Programmable mixed DSP-FPGA architecture using a DM6446 DSP

and a Virtex-4 SX35 FPGA

›› Tunable RF section: 200 MHz to 930 MHz, full-duplex transceiver, and

selectable bandwidth (5/20 MHz)

For more information, contact: info@lyrtech.com

RSC# 33135 @ www.dsp-fpga.com/rsc

DSP-FPGA.com

2008-09 Annual Resource Guide

TI targets portable, connected, floating point, and low cost Any old microcontroller or FPGA can string together ALUs or multipliers and call itself an algorithm processor while crunching fixed point arithmetic. But real world signals are unpredictable and can create wildly varying extremes such that only wide dynamic range can process them. In this realm, only Floating Point (FP) math will suffice. So Texas Instruments added high precision floating point to the company’s TMS320C6745 DSP, TMS320C6747DSP, and the signature OMAP-L137 DSP-plus-ARM processor. All three combine FP math, a wealth of peripherals, and low power at low cost. All three have USB 2.0/1.1, 10/100 Ethernet, and MMC/SD peripherals for desktop, network, and portable connectivity or storage. On-chip integration saves board real estate and simplifies programming and data routing. The C6745 runs at up to 300 MHz, boasts a bevy of serial ports for McASP audio (16 serializers and FIFOs), and can talk directly to 8-bit wide NAND/NOR flash and 16-bit wide SDRAM. The C6747 is similar to the ’45 but has 128 KB of RAM, talks to 16-bit Flash and 32-bit SDRAM, and includes an LCD controller to drive QVGA displays. Lastly, the OMAP-L137 includes the C674x FP DSP core plus an ARM9 at up to 300 MHz per core. Best of all, the OMAP-L137 is pin-to-pin compatible with the C6747 DSP allowing a single design to meet different end-product feature levels.

Texas Instruments • www.ti.com/OMAPL137 • RSC# 39356

FPGA development kit for VMETRO’s DSP The good news: FPGAs do a great job at signal processing due to their vast resources and inherent parallelism. The bad news: ever programmed an FPGA and integrated it into the rest of your system? That’s right: it’s pretty difficult. Designers need to code in HDL for chip-level functions, need to worry about on-chip system design data flows, and then need to assure that the FPGA plays nice with the rest of the system. It’s a wonder anyone uses FPGAs at all. But VMETRO, a board- and system-level COTS provider, aims to make the job of programming their products a lot easier via the FusionXF FPGA development kit. FusionXF includes FPGA HDL functions, software APIs, drivers, utilities, example designs, documentation, and Power Bars (just kidding) to ease the designer’s task of integrating FPGAs into multiple FPGA and PowerPC-based systems, or x86-based host platforms. Features include auto discovery and FPGA resource configuration; extensive HDL libraries for processing and data streaming; easy-to-use API; source code and example functions; and a standardized tool chain for use with industry-standard tools. FusionXF is designed to consume minimal FPGA logic and resources, and glue logic for function blocks via libraries is built in. The tool is supported on VMETRO’s VPF2 (VME VXS), HPE640 (VME VPX), FPE650 (VME VPX), and AD1500 and AD3000 (XMC/PMC) boards.

VMETRO • www.vmetro.com • RSC# 39357

Rugged Xilinx V5 for streaming sensors on VME To borrow a drag-racing analogy: horsepower’s no good unless you can plant it on the road. A gearhead knows that this means getting the power to the wheels. Same thing with DSP boards. Having 2 or 3 FPGAs isn’t jack unless you can get data in and out of them. TEK Micro’s latest VME VXS board, the Neptune-V5 6U, is all about planting that power on the road (so to speak). 3 Xilinx Virtex-5s, DDR3 SDRAM, and flexible I/O move the data into and around this module. Two FPGAs are dedicated to front-end I/O, while the third handles outbound communications to the front panel or to VXS and VME’s P2. There are two 10-bit A/D input channels at 2.2 GSps, and 6 front panel serial ports screaming at 3.75 Gbps each. Each FPGA has its own gigabyte of SDRAM, and two full duplex VITA 41.6 Ethernet links plus two 4x VXS links route data to the rest of the VME Switched Serial (VXS) backplane. The FPGAs can be ordered as SXT (DSP/serial), LXT (logic/serial), or FXT (embedded/serial) variants. As well, TEK Micro’s not-so-easy-to-pronounce QuiXstart FPGA configuration system harkens to the company’s relationship with British defense algorithm expert Qinetic (formerly DERA). Software support for GbE, Serial FPDP, Fibre Channel, and so much more make this board a real tire shredder.

TEK Microsystems • www.tekmicro.com • RSC# 37678 78

2008-09 Annual Resource Guide

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