Winter02 coverstory defect mangement for 300mm 130mm

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Defect Management for 300 mm and 130 nm Technologies Part 3: Another Day, Another Yield Learning Cycle

Kurt Weiner, Todd Henry, Akella Satya, Gaurav Verma, Richard Wu, KLA-Tencor Corporation Oliver Patterson, Brian Crevasse, Kris Cauffman, William Cauffman, Agere Systems

The back-end-of-line (BEOL) interconnect process increasingly poses a formidable challenge for yield groups striving to attain high yields and profitability in today’s competitive market. The combination of smaller design rules and vastly more complex processes highlights the need for a radically new approach to yield learning. This article, the third in a series focused on effective defect management, discusses a revolutionary new methodology for yield learning that significantly shortens the yield learning cycle and offers the ability to exclusively capture yield limiting defects. Through its special design, the method combines non-contact electrical test with inline physical defect inspection, significantly reducing the engineering resources required to identify the problematic defect type and establish root cause, and the time it takes to validate a successful fix. This new methodology, which enables unprecedented breakthroughs in yield learning, gives manufacturers tremendous advantages in productivity and substantial cost savings, ultimately speeding the development of future integrated circuit innovations.

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by speeding the yield learning process, especially in the critical development and early ramp phases.

For IC manufacturers and their customers, time-to-market and timeto-profit are limited by the yield learning cycle time and quality of electrical defect data as reflected in its ability to drive learning.

Introduction

Several years ago KLA-Tencor recognized a critical gap in a fab’s ability to minimize the time-to-market for a new technology: the speed and effectiveness of the yield learning methodology for the back-end-of-line. In response, KLA-Tencor developed a new approach based on its powerful e-beam inspection and defect review technologies.

KLA-Tencor’s µLoop technology, which enables faster yield learning, leverages existing engineering resources to allow earlier technology introduction at significantly higher yields. Effective use of this technology also results in an accelerated yield ramp and higher, mature technology yields.

This earlier introduction of technology, coupled with an accelerated yield ramp, results in increased profitability, as semiconductor manufacturers are able to take advantage of the higher margins that are available early in the life of new leading edge technologies.

What are the underlying market and technology factors driving the transition to this new method?

The Value of Accelerated Yield Learning In Figure 1, a typical BEOL interconnect for quarter-micron technologies is compared with a sub-180 nm process to show the qualitative difference in the number of vital connections necessary to produce a working product. The number of interconnect levels—as well as the design complexities—within the sub-180 nm node increases significantly. Compounding the problem, each successive technology generation requires faster time-to-yield to remain profitable. The value of accelerated yield learning is clear: a three-month reduction in the timeto-yield of a process means hundreds of millions of dollars in increased profitability, with the added benefit of the higher selling prices associated 16

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BEOL Challenges at Sub-180 nm Technology Nodes

Figure 1. The number and complexity of interconnects increases significantly in a sub-0.18 µm process compared to a 0.25 µm process.

with leading-edge product versus trailing-edge product. In comparison, the same improvement in yield learning applied to the manufacturing phase equates to only millions of dollars. This difference reflects the philosophy of basic quality improvement processes: namely, trying to fix the defects during the design phase—where it is more cost-effective—rather than waiting to doing this in the production phase. Greater complexity combined with faster time-to-yield can only be achieved

The problem of speeding time-toyield is non-trivial. In current and future deep-submicrometer technology nodes, kilometers of wiring are required at each metal level to interconnect the millions of transistors in an advanced integrated circuit design. For acceptable yields, an electrical defect density (D0) of less than 0.15 defects/cm2 is required.

Achieving and maintaining this D0 necessitates the capture, analysis, and understanding of virtually every yield limiting defect type in the process line. Unfortunately, the critical size of killer defects is decreasing (scaling with the CD of the process) and reaching the size of materials defects such as metal grains and line edge roughness. Finding and eliminating the electrical “short” and “open” defects while ignoring the non-relevant defects induced by material anomalies is particularly

Voltage Contrast Inspection Physical Characterization

Figure 2. Critical subsurface via defects such as this can be detected using e-beam inspection.

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difficult in the BEOL, and yet essential to attaining profitable production yields in a semiconductor manufacturing line.

at which engineers can negotiate through the various sections of this path will directly impact how quickly yield problems can be solved.

A second and equally daunting challenge concerns the 10s to 100s of millions of vias that provide connections between each level of metal interconnect. The vast majority of these vias are not redundant, resulting in a dramatic hit to yield if more than a few vias per billion are electrically defective within a given layer. Some via failures are caused by surface defects that can be detected using conventional inspection techniques. However, a rapidly increasing number are subsurface, as shown in Figure 2, and can only be detected effectively using electrical measurements. Capturing this buried type of via defect has been a major driver for the implementation of e-beam inspection in recent years.

Step 1: Yield Limiting Defect Identification

These new challenges place a burden on the yield and process groups to implement the fastest and most effective BEOL yield learning method possible.

The yield learning cycle

Today, as in the past, all defect issues are resolved through yield improvement methods organized in repetitive sets of steps or yield learning “cycles.” The start of the cycle is typically triggered when yields are running below a target goal. The methodology to resolve most yield problems follows a common path, which includes identification, engagement, hypothesis testing, and implementation (Figure 3). The rate Low yields

Problem identification “what to fix”

Engagement of processing & integration

In this step, a Pareto of the defect types contributing to the yield problem is established. This Pareto of yield limiting defects is used to prioritize yield improvement efforts to insure resources are placed where they will have maximum impact on improving yield performance.

Step 2: Engagement As soon as the yield limiting defect Pareto has been established, the key to success will now hinge on developing a solution that will eliminate the problematic defect type from the overall population. Process and/or integration engineers must be “engaged” in the activity of developing ideas for changes to fix the problem.

Step 3: Hypothesis Testing The impact of the proposed changes are then evaluated through carefully controlled studies designed to assess if the independent variables, which could be process or integration changes, quantitatively reduce the yield limiting defect type and/or improve the electrical performance.

In total, the elimination of the yielddetracting defect requires at least two iterations of these hypothesis-testing experiments (cycles of learning).

Step 4: Implementation Timely introduction of the new process or integration fix is also Hypothesis testing

Implementation of solution

Figure 3. A typical yield learning cycle.

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necessary to accelerate the yield improvement rate.

Current yield learning methods

Currently, three methods dominate the industry for BEOL yield learning: the product loop, the memory (or SRAM) loop, and the short loop.

These are typically applied in steps 1 and 3 of the yield learning cycle.

Product Loop The advantage of using real product for the yield learning cycle is that the output statistic is the one that is of most interest. Engineers want to understand if the proposed changes will result in improved yield performance. Using product for yield learning has several obvious disadvantages: long learning cycle times; difficulty in isolating the yield limiting defect types; and, the fact that large sample sizes are necessary to assess the impact of the process change on improving the product yield. Creation of an accurate yield loss Pareto on product wafers is a difficult and time-consuming—if not impossible—task on logic technologies. First, electrical testing to evaluate the experiment cannot occur until the product is complete, which can take several months, depending on the complexity of the process. Fault identification, which is much more difficult on nonbitmappable devices, is extremely time consuming and may not result in an accurate yield loss Pareto.

Aside from difficulties with fault isolation, product yield performance does not provide an ideal metric for hypothesis testing. While the yield metric is the one that ultimately is needed to validate improved processes, it often does not provide the level of granularity that is needed to assess the effectiveness of proposed process changes. Yield distributions tend to be highly variable,

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due to the impact of many different factors; the influence of the independent variable under test on yield is often hidden by the “noise” created by all these other environmental factors.

The large variation in the distribution necessitates the use of larger sample sizes to validate a quantitative difference between defect populations.

Memory Loop The memory or SRAM cycle functions in a similar manner as the product cycle, except that a chip with bitmappable memory structures is used. The advantage of this cycle is that it provides an approximate location for each of the electrical defects.

The yield limiting defects can be isolated to a specific layer with classic de-processing techniques. Accurate yield loss Paretos can be developed using this procedure if given enough time. Engineers can use this information to “identify” what defect types need to be reduced to improve yield performance.

However, the bitmap information, while useful in problem identification, cannot be used effectively to gauge statistical differences between populations in hypothesis testing experiments. The labor-intensive nature of the de-processing makes it impractical for assessment of hypothesis testing experiments. Therefore, memory loop improvement experiments use yield as the dependent metric to assess improvement, and suffer the same sample size problems and long time to solution as the product loop.

Short Loop Short loops, in contrast, do not include front-end processing and, so, require only 1 to 2 weeks of processing before reaching electrical test.

These loops use defectivity test chips instead of product devices and are typically limited to three lithography layers (two interconnect and one via).

The learning cycle time is much better 18

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than what can be obtained from product wafers (2 to 3 weeks versus 30 to 60 days). Here as with the bitmap loop, the electrical test data may be overlaid with inspection data so that images of potential killer defects may be collected with a SEM review tool. The effectiveness of this process is limited by the sensitivity of the inline inspection tools to capture the yield limiting defect types.

If the spatial correlation between the inline inspection and electrical data is good, an accurate yield loss Pareto can be developed to drive yield improvement efforts and quantitatively assess the improvement at the yield limiting defect level in hypothesis-testing experiments. If the correlation is poor, the technique does not provide the needed information to determine what needs to be fixed. The second problem with this approach is that the short loop process does not capture all problems that arise during the full flow process.

Finally, if the short loop vehicles are not designed with product-like structures, many of the systematic defect mechanisms that are related to layout will not be captured.

A new method for yield learning

Several years ago, KLA-Tencor began design of a new methodology to address many of the issues that limit the efficacy of the commonly used yield learning methods. In particular, the R&D group focused on developing a much faster system that would quickly identify and quantify the killer defects, allowing more time to be spent on fixing the problem than trying to find the source. The following underlying problems were the key drivers: 1. Obtaining the inspection tool sensitivity necessary to capture sub minimum space and high aspect ratio defects;

Yield Management Solutions

2. Separating the yield limiting defects from the total defect population; and, 3. Capturing both the random and systematic defects that are created when the full process flow is run.

KLA-Tencor’s µLoop methodology addresses all of these issues by combining non-contact electrical test with inline physical defect inspection to produce the fastest root-cause analysis method available in the industry today.

This new approach represents an integrated turnkey solution to electrical inspection that increases the speed and effectiveness of root-cause analysis by detecting and imaging electrical defects quickly, while minimizing the engineering resources required to gather and assimilate the root-cause data.

The components and overall process The integrated approach comprises these components: 1. Proprietary test chip designs 2. eS20XP e-beam inspection system 3. µLoop Controller integrated defect characterization, analysis, and reporting system The patented test structures for the chip are designed to meet the customer’s design rule and chip size requirements. Through close interaction with the customer’s design, module, integration, yield, and test engineers, the test chip can be made to address many defect issues related to product layout, as well as specific process-related problems and process window limitations. As a result, the layout and composition of the chip is tailored to the types and densities of random and systematic defect mechanisms of interest to the customer.

The chip can then be included as desired on either test wafers or product wafers, and may be as large as an entire die or small enough to fit within the scribe lines.

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Figure 4. µLoop uses custom test structures, e-beam inspection and an integrated defect characterization and yield analysis system to complete the yield learning cycle.

Figure 4 shows a general schematic of the µLoop cycle. The test chips are manufactured with the standard BEOL wafer processing. Upon completion of the fabrication of each interconnect layer, the eS20XP e-beam inspection system first captures the critical defects, and then the µLoop Controller characterizes the defects and provides customized defect and yield summary reports. These reports either help identify what defect problem needs to be fixed, or help assess the effectiveness of a process and/or integration change on eliminating the problematic defect type (steps 1 and 3 in the yield learning cycle described earlier). Experiments using the µLoop vehicle continue until the yield problem is resolved. Upon resolution of the current problem, resources are refocused on the next item on the Pareto.

of test structures optimized for performance and speed-of-inspection using KLA-Tencor’s e-beam technology (see the sidebar on voltage contrast inspection). By using a set of proprietary Area-Accelerated™ test structures, throughput enhancements of 10 to 25 times that of standard area-based e-beam inspections are available. A simplified example of this new class of test structure is shown in Figure 5. In this structure,

Intralayer Shorts/Opens Interlayer Shorts

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which addresses interconnect opens and shorts, grounded and floating tines are inter-digitated similar to a comb.

Leveraging the properties of voltage contrast inspection discussed in the sidebar, these new test structures require inspection of only a small region at the bottom of the test structure. Electrical defects present along the length of the tine are transmitted down the tine and sensed through a large voltage contrast defect that appears as a deviation in the normal alternating grounded/floating tine pattern. Through this patented design both shorts and opens can be detected. The CD of the process sets the minimum sensitivity of the test structure measurement. Therefore, the test structures provide high throughput (through sampling) at high sensitivity (through voltage contrast defect amplification).

Grounded via chains are an alternate type of test structure that include large numbers of individual vias, offering a quantitative measurement of any systematic issue that causes a buried open in the via structure (also see the sidebar on random and systematic defect types). These structures are advantageous in that probing of each individual via is not required; again a voltage contrast defect will be detected at the bottom of the test structure if any via is open.

Via Opens (chains)

Via Opens (single)

The test structures and e-beam inspection The µLoop solution is based on the concept of voltage contrast inspection

Figure 5. This new class of test structure takes advantage of the properties inherent to voltage contrast inspection.

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Voltage contrast inspection

Step 1) Assess

Voltage contrast is inherent to all e-beam inspection technologies, but is only created under specific kinds of conditions. During inspection, a conductive material is exposed to a beam of electrons, and a number of the incident electrons collide with the atoms of the metal. A certain fraction of the collisions (depending on the type of metal) produce “secondary” electrons, which are re-emitted from the surface of the conductor at a much lower energy than that of the incident beam. This fraction of secondary electrons is also a function of the incident or “landing” energy of the primary electron beam and can be controlled to be less than or greater than one. If the conductor is isolated or “floating,” the difference in secondary electrons emitted versus primary electrons absorbed produces a net charge over the entire conducting node. When the landing energy is set so that the charge accumulated on the floating conductor is positive (more secondary electrons emitted than primary electrons absorbed), the node builds up a charge until the potential is large enough to inhibit the emission of more secondary electrons, and the node attains a static voltage. Secondary electrons can comprise up to 80 percent of the imaged electrons so, in this situation, the node can appear dark when imaged. In contrast, if the node is connected to a source of electrons (such as a grounded substrate), electrons from the source can flow to neutralize the charge build-up. This “grounded” node never builds a positive potential and so appears brighter than the floating node when imaged. This brightness difference between adjacent nodes can be used to indicate the relative voltage difference between the nodes, and can indicate the presence of an electrical defect.

The assess step is an AreaAccelerated e-beam inspection that quickly identifies the electrical defects across the entire wafer. The throughput of this inspection is maximized through the design of the test chip; due to the nature of voltage contrast, a high-sensitivity inspection is not required, and all of the VC signatures for a particular type of structure can be seen by sampling a small area of the chip. Because the test structure is divided into thousands of individual tines, rather than a large-area comb, the exact location of the defect in one dimension can be quickly identified. During this scan, both electrical and any type of physical defect in the inspected area are detected. Because physical defects are considered non-relevant in this step of the µLoop methodology, they are filtered out by the µLoop Controller, and the final result is a list of the electrical defects and their locations.

Typically, voltage contrast detection is used to complement physical defect detection in an e-beam inspector by providing some electrical information on the product defectivity. Use of voltage contrast defect detection alone to analyze overall product electrical yield is a complex process. However, voltage contrast can be used effectively with specially designed test structures to preferentially detect electrical defects, while rejecting physical defects that do not cause electrical failures. In this mode, voltage contrast defect detection has two important advantages: first, the presence of voltage contrast is an accurate indicator of an electrical failure on the node, providing a means for electrical inspection. Second, because a conductive node assumes the same potential across the entire node very quickly, regardless of size, voltage contrast can be used to both amplify very small physical defects into very large voltage contrast defects and to transmit the defect signature to a common region within the test structure. Using the defect amplification and transmission traits of voltage contrast, a class of test structures that is highly optimized for throughput and sensitivity can be designed.

Another key advantage of this methodology is that it is non-contact. Because there is no need for actual probing, there is less risk of contamination induced by the measurement, and thus the same wafer can be probed at all levels of the interconnect process.

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µLoop Inspection Methodology The complete µLoop inspection uses a three-step process: 1. Assess 2. Identify 3. Classify

Yield Management Solutions

Step 2) Identify The identify step finds the associated physical defects (see Figure 6). The previous step provided the x-coordinate of the physical defect, and although the y-location is not exact, it is bounded by the test structure height.

Using this information, a custom recipe is automatically generated for each wafer that is assessed. To facilitate the identify inspection, the wafer is rotated 90 degrees. This custom recipe provides an inspection test plan that includes only a small region around each defect detected during the assessment scan. Because the number of electrical defects is usually quite low, the total area inspected is very small (typically much less than 1 percent of the total wafer). The small inspected area helps to offset the impact on the throughput of the higher sensitivity conditions required for determining the exact location of the physical defects causing the critical electrical failures.

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types of analyses that quantify the yield killers. µLoop enables the generation of useful Pareto information in a much shorter time than with the conventional loops. The methodology also identifies and classifies 100 percent of the electrical defects on the test wafers. Obtaining comparable information would take prohibitively long using the standard loops and required failure analysis.

Outputs 251.00

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Integrated Analysis and Reporting LW=0.24/LS=0.72

LW=0.24/LS=0.48

Critical to the success of any yield learning cycle is the ability to quickly generate useful information for improving yield. Upon completion of the assess, identify, and classify steps, the µLoop Controller automatically generates a defect Pareto and data reports. In this way, the critical defect types and their quantitative

Figure 6. µLoop finds the physical defect associated with the electrical failure.

Step 3) Classify The classify step uses the information from the previous two steps for confirmation and classification of the electrical and physical defects. The

µLoop Controller takes images of each defect, and the user classifies the defects using an image gallery. All the data is stored and tracked by the µLoop Controller, enabling various

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Summaries by Wafer Process Margin

Yield Summaries

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Figure 7. Various yield analyses provide information to characterize the defect and determine its root cause.

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Root-cause analysis

In some situations, images of a defect are all that are required to know its source. Some yield and process groups have built up expertise over a period of time that allows them to determine root cause accurately based only on a defect Pareto. But in many situations, particularly with new processes and processing equipment, that luxury is not available.

Using the µLoop methodology in conjunction with inline inspections can accurately identify the specific layer at which the killer physical defects occur.

All critical layers of the test wafer are inspected with KLA-Tencor optical and/or e-beam tools, and then µLoop defect locations are overlaid with the inline inspection defect locations to determine the root cause. contributions to yield loss are immediately known, eliminating days, or even months, from the standard yield learning cycle. Analyses are also prepared based on the data stored by the system, including yield summaries, defect densities, defect images, defect size distributions, wafer maps (for spatial signature study), and defect type summaries for multiple wafers (see Figure 7).

These reports are configurable and can be automatically e-mailed to a distribution list if desired.

Application to yield improvement efforts

How should a fab use the powerful data provided by µLoop?

Providing Focus A typical problem less-experienced yield groups run into is having too much data and not being sure which problems to focus on in order to maximize the rate of yield improvement. Other groups become ineffective when they try to resolve all yield problems. The data from µLoop can be used to bring a more systematic and structured approach to yield improvement problems. This new methodology results in a defect type yield loss Pareto that quantifies the largest contributors to yield loss.

The best way to proceed is to use the information and systematically focus on the defects that are causing the 22

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greatest percentage of yield loss. As problems are resolved, the engineer refocuses on the next largest contributors on the yield loss Pareto.

Yield Learning The main use for µLoop (and the one primarily discussed in this article) is the yield learning application, where the goal is to rapidly identify and fix problems. Here, all three steps (assess, identify, classify) are used, along with a full report including the D0, Pareto, images, etc. The case studies in the subsequent sections of this article are all examples of using µLoop for the yield learning application.

Yield Monitoring Inline yield monitoring is another application of µLoop. The other short loop methods do not provide inline electrical testing information; their testing comes at the end of the line, when processing is complete.

The non-contact nature of µLoop allows electrical testing after each complete interconnect level. In this application, the three-step methodology is abbreviated to only the first step—the assess step—which gives the density of electrical failures. If this density is below a certain value, no further action is needed, and a simple inline monitoring report is generated. If there is an excursion of electrical failures, then the other two steps can be completed, generating the full set of information, with a

Yield Management Solutions

Pareto and images to help find the source of the excursion.

Providing Evidence to Help Engage Process Groups The yield group can use the information from µLoop to thoroughly characterize the primary killer defect type, with the ultimate goal of persuading the appropriate process and/or integration group(s) to engage and dedicate resources to fix the problem. The difficulty of convincing the process groups to assist should not be underestimated as a potential hurdle in the yield improvement process.

Often, the only way to accomplish it is to have thorough and quantitative characterization data showing specifically what percentage of the yieldlimiting defects came from that group’s process or equipment. The main results from the µLoop methodology (number of physical defects causing electrical failure, and a Pareto of those defect types) provide the convincing evidence needed.

Tuning Inline Inspections Another use for the uLoop data is to evaluate inline optical inspection recipes for their ability to capture yield-limiting defects. The defects, captured with inline optical and laser inspections can be characterized and compared with the yield limiting defects captured with the µLoop process. Inspection recipes can be optimized for use on product wafers to maximize the capture of top yield limiting defects capture with the µLoop process.

(See the sidebar on root cause analysis for further information about the integration of µLoop with inline inspection techniques.)

Comparison of the new method to previous methods

Agere Systems in Orlando, Florida, participated in a joint development

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project with KLA-Tencor to help develop the µLoop technology. The work was initiated because of the long cycle times the yield group had experienced with the standard methods it had used for BEOL yield learning.1 These methods included: • Product wafers used with bitmapping and failure analysis de-processing • Short loop comb and serpentine structures used with electrical testing, manual SEM review to locate the defects, and failure analysis de-processing • Short loop zone tester vehicles with combs and stitch test structures where killer defects were identified by overlaying electrical test and inspection data Two goals of the development project were to selectively capture only the yield limiting defects, and to minimize the yield learning cycle time. The first goal would speed the creation of an accurate defect Pareto pointing to the areas that need work, and the second goal would speed the hypothesis testing time, allowing for faster implementation of a fix.

Table 1 summarizes how effective each of the methods were in the identification of what problem to fix and the amount of time that was required to generate the information. The preµLoop methods required anywhere from 16 days to over two months to develop the initial Pareto due to deprocessing or data analysis time requirements. For some of the longer and more labor-intensive methods, the Pareto was built using only one or two wafers. The fastest of the preµLoop methods based the Pareto on a much larger sample of 25 wafers, but only captured 5–60 percent of the yield limiting defect population. In contrast, the µLoop method required only four days to create the yield loss

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Random versus systematic defects

Random defects are caused by the environment—the people and the processing equipment. A systematic defect, however, occurs because the process window is too small or isn’t centered correctly. Certain features will be the first to show a systematic layout marginality, so when the problem occurs it will show up in the same place. Historically, these problems have been hard to create and measure on anything but product, but now they can be captured by turning these features into test structures on the µLoop test chip. These systematic or “instance-based” test structures include many individually measurable replications of the feature. The advantage with µLoop is that these large areas of repeated features (for example, an array of vias or line/space features) are not limited in their layout by probe pads.

Another example of a systematic feature is a repetitive SRAM metallization structure. SRAM test vehicles are commonly used by fabs to assess back-endof-line process problems because they provide word and bit address locations of the electrical failures through bit mapping. The disadvantage of these BEOL test vehicles is that they require full processing of the front-end logic to support the bitmap testing. The advantage of using KLA-Tencor’s new methodology is that the same BEOL SRAM metallization structures can be designed into the µLoop test chip and then tested for systematic or random electrical failures without the need for the front-end-of-line (FEOL) processing, significantly reducing the time needed to get results. This is powerful, particularly in development, because often the SRAM vehicles experience FEOL-related yield problems, defeating their usefulness for assessing BEOL yield issues.

The systematic features on the µLoop test chip are beneficial for both current production processes and processes in development. If a current process is experiencing a systematic problem, the test chip features can be designed to simulate that issue. To speed development of a new process, the µLoop systematic structures can be used to project the effect of a design rule change on a worst-case feature set, testing the process window boundaries.

This testing can be made easier with the help of KLA-Tencor’s lithography simulation experts and software (PROLITH™). Utilizing this expertise in conjunction with the µLoop methodology simplifies the complex process of developing a high-yielding process integration module. Simulations allow investigations of the effects of process parameter settings and process errors on CD-limited yield, while the µLoop short loop methodology provides fast yield verification of the simulated results.

Pareto on 25 wafers. Because of µLoop’s use of e-beam inspection and voltage contrast techniques, 95–100 percent of all the yield limiting defects on the wafers were captured.

Further comparison of the different methods can be seen in Table 2, where the goal was minimizing the cycle time for the hypothesis-testing loop.

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The use of product for hypothesis testing was the worst option.

Product cycle times are relatively short but, by the time probing and testing are factored in and results are fed back to the engineer, can result in a 60-day cycle of learning and only provide probe yield results as a metric. The other methods provided

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were performed, and the µLoop Controller was used to characterize the yield limiting defects. The resulting yield loss Pareto, shown in Figure 8a, indicated that two primary defect types—“particles with extra” and “metal stack defects”—were responsible for the majority of the test structure shorts. Several additional repetitions were made with the µLoop process and the true dominant killer defect—“particle with extra”—was singled out. The defect characterization information, including defect images, composition information, and spatial correlation with inline inspection data, pointed to the metal etch process.

Implementation of solution

What needs to be fixed?

Approach

Time to Develop Pareto

Sample Size for Pareto Development

% of Yield Limiters Isolated

Bitmap

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Electrical Comb/Serp Testers

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90%

Zone Tester Overlay

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25 wafers

5-60%

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25 wafers

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Table 1. Comparison of the performance of various yield learning cycles for creating the initial killer defect Pareto.

metrics more relevant to the defect under study in the form of defect densities and short/open information. The µLoop methodology’s throughput was again far better than that of the other methods, and it was the only method to provide information on 95-100 percent of the defects causing electrical failures.

Overall, the µLoop method provided the capability that was desired and that was deficient in the previouslyused techniques. The µLoop method enables rapid construction of a yield limiting defect Pareto based on a large sample size and containing virtually all the killer electrical defects on the test chip. This technology also enables faster hypothesis testing, and provides a superior quantitative yield limiting defect metric that can be used to assess the success or failure of hypothesis testing studies.

Engagement:

Case study 1: Hypothesis testing on an aluminum process Introduction: One of Agere’s aluminum processes was yielding below the track goal. The problem was isolated to the BEOL using electrical tester data. The tester data, while indicating that the problem was localized to the interconnect level, did not provide information on the yield limiting defects contributing to the overall yield loss.

Problem Identification: One lot of µLoop test wafers were run through the metal 2 process. At the completion of the process sequence, e-beam inspection scans using the eS20XP Yield problem

The quantity of yield limiting defect data, coupled with the characterization information (images and compositional analysis), provided the evidence needed to engage the appropriate metal etch module process engineer.

Hypothesis Testing: This engineer proposed studying the effect of a new type of tool clean on the level of the “particle with extra” yield-limiting defect type. The µLoop data was used to provide the dependent metric for the studies.

An experiment was designed comparing the process of record, which

Yield Engagement learning of processing defect & integration identification

Hypothesis testing

Implementation of solution

Minimize cycle of learning time Case studies

Early versions of µLoop have been used to great advantage in over a year of practical application at Agere Systems. Three case studies of how µLoop was used for yield learning at Agere Systems follow.

Vehicle

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No

Short loop (electrical/overlay)

10 days

D0, Shorts, Opens

Yes (5-60%)

Yes

µLoop

4 days

D0, Shorts, Opens

Yes (100%)

Yes

Table 2. Comparison of the performance of the various yield learning cycles for hypothesis testing.

24

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Yield Management Solutions

O

V

E

S

R

T

O

R

300

18 Process Variable X PWE's

Defect Density (cm2)

Process Variable X (Watt)

250

150

9

100

6

50

3 0 2

4

6

8

10

12

Wafer # (Etch Sequence)

Figure 8d. By-wafer correlation between “particles with extra” and a process variable.

Stack

Extra

W Puddle

Not Found

Figure 8a. Results from µLoop showing the initial yield loss Pareto.

ran on tool A, with the new “in-situ” cleaning process, which ran on tool B. The metric for quantifying the results was the density of “particle with extra” defects on the µLoop test chips. Initially, one lot was split, with the wafer processing spread out over a period of time to evaluate the effect of “chamber time since last major tool clean” on the level of yield limiting “particle with extra” defects.

In contrast, the tool with the experimental new clean did not show any increase over time. The same lot was used again with the µLoop methodology at the next metal layer; and, the additional data confirmed the initial results. Paretos were generated using µLoop before and after this process change was implemented. Figure 8c shows how the density killer defects changed over this time period. The improvement was very clear.

The results in Figure 8b showed degradation in the standard clean tool as more wafers were processed through it, leading to an increase in the “particle with extra” defect density.

Subsequently, “particles with extra” were still the dominant killer defect type on the Pareto, though at a much lower level, but now only a few wafers per lot showed high counts of this defect type. Additional µLoop experiments led to the discovery of a strong correlation between a certain

Particle with Extra Density

12

0

Defect Class

In-situ Clean No Clean

Etch Particle With Extra* W puddles Deep or Litho Particle With Extra Stack Other * Defect of Interest

Defect Density (cm2)

0.2 0.18 0.16 0.14 0.12

No In-situ Clean

In-situ Clean

0.1 0.08 0.06 0.04 0.02

100

15

200

0

Particle With Extra

0

Y

eS20 Particle with Extra (PWE)

C

200

300

Wafer Count

0

1

2

3 4

5

April/May

6

7

8

9 10 11 12 13 14 15 16

Lot

June/July

Figure 8b. Results from µLoop showing the

Figure 8c. Results from µLoop showing the

degradation of the standard clean process

decrease in the critical killer defect type after

compared with the new clean.

the implementation of the new clean.

Winter 2002

process variable and the “particle with extra” defect count as illustrated in Figure 8d. Note, that for the data shown in Figure 8d, the correlation between the total number of killer defects and this process variable was not significant because of an excursion of tungsten puddles; this demonstrates the value of being able to break down the yield loss by defect type. A process adjustment to keep the level of this certain process variable down was devised and proven in using µLoop.

Implementation:

The decision was made to modify the process of record to include the in-situ clean based primarily on the results obtained using the uLoop technology. At the time of the change, the results from product data were inconclusive. µLoop greatly accelerated the implementation phase for this first process change. The second change did not require board approval and was implemented soon after the compelling results from µLoop were obtained.

Summary: µLoop was used to quan-

tify the contributions of the various defect types to the overall yield loss and to pinpoint the area needing the most work. Next, it was used to test several process improvements and their ability to reduce the level of yield limiting defects, and to track their effectiveness over time. This study highlights how the use of the µLoop process offers a cycle of learning at

Yield Management Solutions

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O

V

E

R

S

T

each interconnect level for a particular lot. It led to a 4x improvement in the time needed to implement these process changes. With µLoop, these changes were implemented in only one and a half months; using the conventional methods they would have taken at least six months.

Case study 2: Capture of a systematic problem on an aluminum process Introduction: The practice of periodically running µLoops for a number of technologies to track and characterize the BEOL yield loss Pareto was instituted early in 2001 at Agere Systems. Often, these same wafers are also used for hypothesis testing experiments. The ability of the µLoop methodology to break down yield loss by defect type allows the same lot of data to be used for both purposes.

In this example, a systematic problem was detected on the outer periphery of the wafers in an aluminum process for the latter metal levels.

Problem Identification:

The initial full flow µLoop lots for this technology detected significant yield loss at the wafer edge for the metal 4 interconnect level. A wide line, minimum space comb test structure had been placed on the chip in order to test the extreme limits of the design rules. All metal lines tended to be wider at the wafer edge and this particular structure was shorting in what appeared to be random places in this zone. Soon after this discovery, significant product yield drop-out was observed at the wafer edge.

Routine inline inspection of product had not provided evidence of any type of problem; many of these shorts were very difficult to pick up even with a SEM. Cross-section and other characterization work indicated that there was a large variation in the wafer topography around the outer edge of the wafer. This variation, coupled with the limited lithography 26

Winter 2002

O

R

Y

depth-of-focus, was enough to cause a printing problem and subsequent metal line shorts.

Summary:

In summary, µLoop provided an inline vehicle to capture a problem that was not captured with inline defect inspection tools and that would typically require time-intensive failure analysis techniques to characterize. The issue was a systematic problem captured with a systematic test structure specifically included to test for it. The only reason this problem had not been detected earlier with µLoop was that the µLoop test chip had only recently been developed.

Secondly, the µLoop wafers, which were processed with the entire process sequence, captured a problem that would not have been captured on a short loop (1- or 2-level) process sequence. The problem also would not have been captured on the normal, nominal line and space test structures. The problem was confined to the wide line/narrow space structures.

Engagement: The wafer topography problem could be caused by one or more process steps used to complete the interconnect process. A team was formed, including process and integration engineers, to develop a solution to the problem.

Hypothesis Testing Experiments:

The team ran several studies to minimize the topography variation across the wafer surface. The µLoop methodology was made available for hypothesis testing and was utilized to evaluate one idea. The ultimate solution was not initially tested with the µLoop methodology since direct measurements of the wafer topography were more appropriate. Once the team had developed an acceptable solution, the µLoop wafer results indicated that the problem of metal line shorts no longer existed around the outer periphery of the wafer.

Case study 3: Early yield learning on a copper process Introduction: Yield learning on new

technologies is especially challenging due to the large number of defects present on wafers as new processes are being developed. Attacking all of the different defect types at the same time diffuses the available resources and results in slow yield improvement.

The key to success is to obtain a yield

Implementation:

The process change, which was a CMP hardware modification, was implemented.

The ensuing yield data from µLoop was one of a number of validations that the outer edge systematic yield problem was eliminated.

Outer edge spatial signature

Defect Density (cm-2)

C

Narrowing W Puddle Particle with Extra

Extra

Defect Class Figure 9. Results from µLoop showing the narrowing space defect and signature.

Yield Management Solutions

Count

C

9 8 7 6 5 4 3 2 1 0

Distortion PR Bubble

Flake

Not Found

Extra

Smudge

Defect Class

Scratch

Falling Walls

Particle

Removed Dielectric Particle

O

V

Missing Copper

Figure 10. Results from µLoop showing the yield loss Pareto for the copper process in development.

loss Pareto that allows one to focus improvement efforts on the defect types that contribute the most to yield loss. In this example, a yield loss Pareto was developed for wafers processed early in the development phase.

Problem Identification:

A short loop tester containing the µLoop test chip was processed through the metal 1 copper interconnect process.

The µLoop structures were scanned on the eS20XP and the defects were characterized using the µLoop Controller. The Pareto showed that the majority of the wafers had more shorts than opens—an unexpected result—and the most common defects were distortions of the oxide trenches, photo resist bubbles, and flakes.

Based on this information, the yield group was able to prioritize their future improvement efforts to maximize yield learning.

Here the µLoop methodology was used to overcome the common problem of defect noise in the development phase, and enabled the fast separation of the yield killers from the general defect population. µLoop Summary

Fast yield learning for the back-end-ofline has become even more challenging and essential with the introduction of increasingly complex interconnect processes and smaller design rules.

The efficiency of the BEOL yield

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R

S

T

O

R

Y

learning process has improved significantly with the introduction of µLoop, which enables (1) a reduction in the time to complete a learning cycle from weeks or months down to days; (2) multiple cycles of learning to be obtained from each µLoop lot; (3) the construction of a yield limiting defect Pareto that provides a quantitative assessment of the yieldloss contributors; (4) characterization of the yield limiting defect with compositional analysis; and (5) the capture and identification of systematic defects that are created by integration issues or are exacerbated by multi-layer topography.

Yield groups can take advantage of KLA-Tencor’s expertise and revolutionary BEOL yield management technology, requiring them to invest fewer resources and less time and money in the complex and difficult process of developing BEOL test chips and yield learning methods.

The benefits they receive in return are tremendous: reaching yield goals faster, getting to market faster, and reaping potentially hundreds of millions of dollars in increased profit.

References 1. Henry, Todd, “Application of eD 0 to Accelerate BEOL Yield Improvement Activities,” KLA-Tencor Yield Management Seminar, October 2001.

Yield Management Solutions

27

YIELD

There are many paths to yield.

But these days, only the fastest route will do. That’s

in optimizing your manufacturing process. All strategically

why we focus relentlessly on shortening your journey.

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With best-of-breed solutions designed to let process

the most efficient road to yield. For more information,

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please visit us on the Web

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