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Strained Silicon Substrate Technology: Commercialization Fundamentals Mayank Bulsara, AmberWave Systems Corporation
Strained silicon substrate technology, encompassing bulk strained silicon and strained silicon-on-insulator, has made the ascent from laboratory-scale experimentation to evaluation by leading wafer and device manufacturers for commercial implementation. The rapid commercialization climb has expanded and modified the requirements for strained silicon technology; however, the underpinnings of strained silicon substrate and transistor manufacture are closely related to fundamental innovations that were established early during strained silicon technology research. This article highlights the essential bulk strained silicon and strained silicon-on-insulator technology developments that have placed them on the forefront of materials innovations for the semiconductor industry.
Introduction
The 2003 International Technology Roadmap for Semiconductors (ITRS) for the first time forecasted the necessity of mobility/transconductance improvement for nearterm high performance logic application1. With mobility enhancement techniques forging into fundamental transistor architectures, strained silicon (Si), which is practically synonomous with mobility improvement, is being investigated by many manufacturers. Although strained Si generically refers to a Si crystal that is elastically deformed, the techniques for straining Si generally comprise three methods: (1) strain induced during transistor processing2,3,4, (2) mechanical or packaging-level strain5, and (3) substrate-level strain induced by relaxed silicon-germanium (SiGe) alloys6,7,8,9,10,11. Of the three methods, substrate-level strain is by far the best researched and characterized in terms of technological benefits and key economic factors for commercialization. Substrate-level strained Si technology is addressed by the 2003 ITRS section on Emerging Materials, which outlines key substrate design criteria for strained Si and its
embodiments. A schematic of these three embodiments is shown in Figure 1: (a) bulk strained Si, (b) strained Si on insulator with an intermediate relaxed silicongermanium (SiGe) layer (SGOI), and (c) strained silicon on insulator without a relaxed SiGe layer (sSOI). Among the key criteria listed for consideration are: strained Si film thickness, germanium (Ge) content in relaxed SiGe layer, threading dislocation density (TDD), dislocation pile-up density (DPD), and short- and long-range surface roughness. All of these criteria can be addressed adequately by innovations that are already being implemented. The remaining questions must be answered by full-scale transistor and chip developments and the qualification of economic wafer manufacturing methodologies that have the requisite inline metrology to ensure the highest quality. Strained Si Strained Si
Relaxed SiGe
Strained Si
Relaxed SiGe
SiO2
SiO2
Si Substrate
Si Substrate
Si Substrate
(a) Bulk Strained Si
(b) SGOI
(c) sSOI
Figure 1. Strained Si embodiments in the 2003 ITRS Emerging Materials section.
Summer 2004
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