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Improved Etch and CMP Process Control Using Inline AFM Thomas Trenkler, Thomas Kraiss, Ulrich Mantz, and Peter Weidner, Infineon Technologies Rebecca Howland Pinto, KLA-Tencor Corporation

As aspect ratios become higher, features become smaller, and requirements for planarity tighten, atomic force microscopy (AFM) has begun to replace profilometry for topographic measurements, such as trench and via depths, step height, and micro-planarity measurements, both in development and in production. In this paper we describe the application of a new, high-throughput AFM for line monitoring in the STI and trench capacitor modules. We focus on two key applications: the post-CMP height difference between the active area and the isolation area in the STI module, and the post-etch depth of a DRAM trench capacitor.

After describing the two initial AFM applications, we introduce a statistical approach for determining optimal lot sampling for these applications. The optimal lot sampling reveals a gap between the throughput of our conventional AFM, and statistically determined sampling requirements; thus we validate the need for a high-throughput AFM. Next, we describe the design of such an AFM, recently developed by KLA-Tencor, and present our early results. Finally, we discuss the economic benefit to Infineon of detecting metrology problems inline, without the delay and cost of cross-sectional SEM analysis.

Introduction

Atomic force microscopy (AFM) has become an indispensable technology for monitoring trench depths and chemical-mechanical planarization (CMP) processes on the production floor, especially at the front-end of the line, for the 90 nm node and below. Smaller critical dimensions and tighter planarity requirements limit the ability of traditional profilers to monitor the shallow trench isolation (STI) process in-die after CMP. Shrinking critical dimensions and increasing aspect ratios of trench capacitor structures have also made post-etch depth measurements inaccessible to traditional stylus profilers. Using proxy structures with stylus profilers or other technologies works only when in-die variation is minimal or benign. Infineon Technologies, Dresden, now uses AFM to monitor their DRAM devices at STI and trench capacitor levels in production.

Process control by AFM has been limited in the past because of the AFM’s relatively slow throughput and poor reliability. Additionally, AFM operation has required a high-level engineer, trained to separate AFM artifacts from real process issues. AFM line monitoring has often been capacity-limited for these reasons.

Implementation of optimal sampling based on statistical models of the maturity of the process has not been feasible because the throughput of the AFM has been so limited. Placing multiple, redundant AFMs in the fab was not an option at Infineon for reasons of cleanroom space and cost of ownership.

In this paper we discuss statistical sampling models that predict that additional AFM measurements will result in superior process control. We describe a joint development program (JDP) between Infineon Technologies and KLA-Tencor to provide a highthroughput AFM, capable of supporting development, ramp, and inline process control of Infineon’s STI and trench capacitor processes, for the 90 nm node and Summer 2004

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beyond. We present early results from the JDP. Finally, we discuss the time and cost saved by using AFM for failure analysis, rather than cleaving product wafers for cross-sectional scanning electron microscope (SEM) analysis.

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silicon Surface metrology process control: STI CMP

The purpose of STI is to electrically isolate active device regions. Infineon/SIEMENS began replacing LOCOS isolation technology with STI at the 0.35 µm node; beyond the 180 nm node, many manufacturers had made the change to STI. The use of STI enables an active area with higher device density.

After etch, STI features are typically filled with silicon dioxide deposited by a high-density plasma. CMP is used to planarize the device in preparation for subsequent process steps, and then the nitride hard mask is stripped. Figure 1 shows the resulting structure.

Figure 1. SEM cross section of STI region, after CMP and nitride strip.

In this case the isolated area (oxide) extends 17 nm above the active area (silicon).

Metrology issues post-CMP are illustrated in Figure 2 and include: • Height difference between active area and dielectric • Erosion at interfaces between active area and dielectric By far the most critical metrology issue at STI CMP is the step height between the active and isolated regions after CMP and nitride strip. If this step exceeds a few nanometers, transistor parametric performance may be 58

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Figure 2. Schematic representation of post-CMP isolation trench showing active silicon and isolated oxide areas. The step height, h, of the active versus isolated area is an important parameter to control after STI CMP.

affected. If the oxide protrudes, it can interact with the polysilicon for the gate. Excessive active-isolated step height can also cause problems for implant and contacts. The step height can introduce difficulties for resist coverage and stepper focus, cutting into the depth-of-focus budget for the lithography step that forms the gate.

The isolation trench (IT) step is influenced by trench depth, high-density plasma oxide deposition thickness, nitride thickness, CMP process parameters, and the process parameters for wet-chemical removal of residuals.

Different tool combinations can generate lot-to-lot variation. Furthermore, wafers within a lot may be exposed to a variety of process chambers and CMP heads. Depending upon the matching conditions between these tools, a high number of wafers per lot and a high number of lots, may need to be measured to ensure adequate process control. If the step height is out of specification and is not detected within the STI module, the consequences will not be seen until electrical test, when the transistor is finished, and many other similar wafers have been processed.

Erosion at the interfaces between active and isolated areas can affect the threshold voltage, Vt, and thus have an impact on device performance. However, erosion is not monitored at this time—all of the AFM capacity currently reserved for IT-step is devoted to post-CMP step height control.

Sub-nm noise performance—noise floor and sampling algorithm—of the AFM is important for monitoring IT step height, to identify step heights that exceed the stringent control limits. In addition to noise considerations, only an AFM with a sharp tip (terminal radius

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~10 nm) can gather sufficient data points on the surface of each region to determine an accurate step height. Optical profilers are limited by their spot size and their inability to distinguish which side of the step is higher. Furthermore, monitoring STI step height using any technique that relies on proxy structures is not recommended, because even small deviations of the shallow step height can lead to erroneous interpretation of the results. AFM alone constitutes the practical solution for this application.

At Infineon, AFMs have been successfully employed as CMP tool monitors; however, the sampling plan has been limited by the throughput of the AFM. (Cleanroom space is limited; thus the number of tools is limited.) One of the driving motivations for the JDP with KLA-Tencor was Infineon’s expectation that the 110 nm and 90 nm STI processes could be monitored more effectively by measuring a larger number of wafers.

A higher throughput AFM also enables the option of denser sampling for development of future nodes, and for in-line monitoring of those nodes with higher sampling frequency, as the devices enter production.

Surface metrology process control: trench capacitor etch recess

The requirement to have a large capacitor in a small space with low leakage is a main driver of DRAM technology. At the transition from 1 Mb to 4 Mb technology, planar capacitors failed to provide enough cell capacitance, and were replaced by three-dimensional capacitors throughout the industry. These took the form of either trench capacitors buried within etched holes in the silicon, or stacked capacitors built above the silicon in the region of the interconnect-level films.

For the trench capacitors considered here, a succession of polysilicon and insulator deposition and etch steps define the capacitor plates. A simplified version of Infineon’s proprietary structure is given in Figure 3.

The first silicon etch step that defines the deep trench can be monitored using infra-red metrology, as can the first polysilicon recess. The last two polysilicon recess depths, Ra and Rb in Figure 3, are monitored closely during production by AFM because their variation strongly affects the device performance.

Infineon has been using AFM for measuring the two key recess steps since the 0.25 µm process was introduced.

However, analysis of the process maturity suggests that trench-capacitor process control would benefit from a

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Figure 3. Schematic representation of trench capacitor, showing potential metrology issues. The polysilicon recesses R a and R b comprise the set of parameters important to control at the trenchcapacitor level, as they define how the capacitor connects to the gate.

denser sampling plan (see discussion below). As with the STI module, the capacitor recess measurements have been limited by the throughput of the AFM. Better process control of trench-capacitor recess represents another main driver of Infineon’s JDP with KLA-Tencor for a high throughput AFM. Other AFM measurements

AFM has unexploited capability for many high resolution, local measurements in the fab. Having AFMs loaded to capacity for reasons of limited throughput has precluded most unscheduled small-lot or split-lot investigations of process issues that arise. On the other hand, having a high-throughput AFM that is not fully loaded would enable Infineon to address some of these issues and decrease the number of expensive and timeconsuming SEM measurements on cleaved wafers.

The feedback time for the unit process results would be much shorter, if an AFM could be used.

One example of an unexploited AFM application within the STI module is measuring the topography of the deposited oxide film before CMP. Monitoring the film topography post-CMP can help identify planarity issues and consequent leakage, if the deposited oxide is too thin. Another potential set of post-CMP AFM measurements within the STI module is to monitor microroughness or erosion at the interfaces. Such measurements will be of higher value at future technology nodes, when topographic requirements are tighter.

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Another possible post-CMP AFM application is defect review, specifically for microscratches. Microscratches continue to be a problem for yield management post-CMP. Shallow scratches are nuisance defects, while deeper scratches can cause reliability problems after they are filled. With current optical and e-beam review methods, it can be difficult to distinguish shallow, nuisance scratches from killer defects. AFM may be able to differentiate nuisance from killer microscratches by measuring their size. However, a key barrier to using AFM for microscratch review is matching the coordinate system of the defect inspection system with that of the AFM.

sLS_rel = σ 2LS_rel = σ 2wafer-wafer + σ 2random within-wafer = σ 2total – σ 2systematic within-wafer

The process capability index relevant to lot sampling, CpkLS_rel is then defined as:

CpkLS_rel = Cpk *

stotal sLS_rel

Note that CpkLS_rel ≥ Cpk.

These examples are confined within the STI module. Many other issues may arise during process development or production that could benefit from AFM measurements.

s LS_rel/ s total = 0.47 ~ 2* Cpk Cpk LS_rel ~

Sampling Frequency and Process Control

When the sampling strategy within a module is not limited by the throughput of the measurement system, accepted statistical methods can be applied to determine the optimal sampling strategy for process control. Infineon has a release board that reviews process parameters and approves sampling strategies based on the method described below.

s LS_rel/ s total = 0.92 ~ 1.1*Cpk Cpk LS_rel ~

Figure 4. Examples of SPC charts from the capacitor recess processes demonstrating high (top chart) and low (bottom chart) systematic within-wafer process variance.

Note that the wafer-to-wafer variance is lower in the top chart than in the bottom chart.

The process capability index Cpk is measured.

This standard index is a function of the upper and lower control limits, as well as the standard deviation of the process parameter—for example, the trench depth. Developed in Japan in the 1970s, Cpk is a measure of how well the process is centered within the control limits, as well as how tightly the data are distributed around the center. When Cpk > 1 the process is under control; moreover, a Cpk of 1.33 or better is usually considered a “good” process.

The variance components that contribute to Cpk can be broken down into three terms: stotal = σ 2total = 2 2 σ wafer-wafer + σ random within-wafer + σ 2systematic within-wafer

Examples showing high and low systematic within-wafer variance are given in Figure 4.

Apart from process capability, as measured above, it is useful to define process stability. For this a desirability index, DI, is used, which is an integrated assessment of process stability and control limit adjustment. The desirability index has three components: d1 gives the number of outliers, d2 represents the process variance change, and d3 captures the shift or trend in the process mean. They are defined as follows: d1 = 1 – istab, where istab = % samples violating control limit d2 =

The third term, representing systematic within-wafer variance, is not relevant to lot sampling; only random sources of error are of interest. Thus we define sLS_rel as the variance relevant to lot sampling: 60

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meanold - meanold d3 = snew

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The desirability index, then, is the geometric mean of their sum: 3

DI = √ d1* d2 * d3 However, we have found it useful to design a desirability index more sensitive to outliers: d1_5% = max(1 – 20*istab, 0) Note that when no outliers are present, istab = 0 and d1_5% = 1. When more than 5% of the data are outliers, d1_5% = 0. Then the modified desirability index can be written as: 3

DI_5% = √ d1_5% * d2 * d3 Bringing the process capability and desirability indices together, we define the process maturity, PM, as follows:

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BLF = 9e -1.5*PM + 1 Thus the sampling plan, the number of lots per week sampled, is a function of the process maturity.

Example values of Cpk, PM and BLF are given in Figure 6 for Ra, Rb, and the STI step measurements. These values are representative of the statistics of the three measurements during ramp of Infineon’s 110 nm process.

Production values are expected to be significantly better; however, the relationship among the values is expected to be preserved. The Cpk and PM values for the recess measurements will likely lie below that of the STI step measurement, and the BLF values for Ra and Rb should remain higher than that of the STI step measurement.

What these results indicate is that, for 100 lots starts per week, 100% of all lots should be sampled for the

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Figure 5. The baseload factor (BLF) and its dependence upon process maturity (PM). 1: PM = 0 and BLF = 10; 2: PM = high and BLF = 1; 3: PM = 1.5 and BLF ~ 2.

CPK PM BLF

Arbitrary Units

The baseload, BL, is the minimum number of lots per week sampled, for a given process and product group.

BL is determined by various fab-wide parameters. The baseload factor, BLF, is a multiplier for the baseload, and determines the sampling frequency, in lots per week, for a given metrology point. The baseload factor lies between 1 and 10 (see Figure 5), and is given by:

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PM = CpkLS_rel + (0.5 + 0.5*DI_5%) Note that the second term is constructed to allow the desirability index to be weighted more heavily than the process capability index.

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Figure 6. Relative values of Cpk, PM and BLF for the trench capacitor recess measurements R a and R b and the STI CMP step measurement.

These are representative values during ramp of the 110 nm process.

Production values of BLF are expected to be lower, as Cpk and PM improve.

Rb measurement; 90% of all lots should be sampled for the Ra measurement; and 73% of all lots should be sampled for the STI CMP step measurement. With this level of sampling, Infineon would need to add AFM capacity. Because the fab’s floor space is limited, the best solution is to replace the current AFMs with high-throughput systems.

Better process control using new AFM

Infineon, Dresden, entered a Joint Development Program with KLA-Tencor to evaluate a new AFM designed for higher throughput. Infineon was primarily motivated by interest in achieving greater control of the STI and Summer 2004

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The target throughput improvement for the JDP is three times that of currently available AFM systems, under conditions which include wafer loading and unloading, alignment and pattern recognition on 200 mm or 300 mm wafers, and a 5-site measurement on each wafer. Under these conditions the new AFM also must meet certain targets for repeatability, tip lifetime and uptime. At the time of writing this paper, the system has achieved a greater than twofold throughput increase while meeting repeatability, uptime, and tip lifetime targets. We anticipate meeting the JDP goals in tandem with the general product release.

AFM Linearity measured value (nm)

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VSLI certified value (nm) Figure 7. Linearity of VCM scanner in the verticle (z) direction is demonstrated by measuring the step height of six certified standards, ranging in height from 18 nm to 1.8 µm, and plotting the nominal (measured) value versus the certified value.

trench-capacitor processes by sampling the processes more frequently. The new AFM, released to KLA-Tencor’s general customer base in the middle of calendar year 2004, includes several design aspects targeted at throughput. These include: • A platform derived from KLA-Tencor’s Archer 10, an established optical overlay system demonstrating excellent stage speed and accuracy, a highly effective active vibration isolation system, and top industry reliability statistics • An AFM head featuring a voice coil motor-driven scanning system that is fast, as well as inherently more linear and less prone to hysteresis than traditional piezoelectric scanners (Figure 7) • Rapid, accurate, proven pattern recognition based on a combination optical bright field and white-light interferometer system (Linnik), with proprietary image-enhancement algorithms • Rapid AFM approach enabled by feed-forward of the tip-to-sample distance from the Linnik interferometer • Proprietary “smart” non-Cartesian sampling within the AFM data set • Fully automatic tip exchange using pre-qualified, self-sensing cantilevers that eliminate the requirement for aligning a secondary deflection-sensing subsystem

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Using an AFM having a greater than twofold throughput increase, our statistical modeling justifies increasing the sampling frequency of our post-CMP STI and trench-capacitor etch process monitoring as indicated in the previous section, without increasing the number of tools. This increased sample plan should result in tighter control of STI step heights and trench-capacitor etch depths during volume production. Potentially, better STI and trench-capacitor control may contribute, along with many other factors, to dispositioning a larger fraction of our completed DRAM devices to the highest quality bins. Under normal market conditions the quality of the DRAM relates directly to its selling price.

Early Results

An efficient methodology was developed for monitoring the depth of the trench-capacitor recess that contributes to acceleration in time-to-results. After the AFM tip lands in a field of capacitors, it takes a small number of sparsely distributed scans, until a trench is located.

A single, short line scan in the perpendicular direction completes the location of the center of a given trench.

Knowledge of the layout of the trenches enables us to set up the final recipe, which consists of five line scans, traveling across ten trenches. An example is given in Figure 8.

Figure 9 shows a three-dimensional image of a small capacitor field, though such data would not be collected in production, when only the line scans are needed to control trench depth. Finally, Figure 10 demonstrates measurement repeatability. The new AFM has been able to achieve 3σ dynamic repeatability and long-term stability values of ≤ 2% for the trench capacitor recess process. In addition, the tool has demonstrated gage repeatability and reproducibility (Gr&R) of better than 4% on a 450 nm step-height standard wafer at the Infineon site.

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Using this simple model, our estimates are that PFA costs 100x to 300x as much as AFM. Exact figures depend strongly upon detailed costs of each of these items, and these will vary by country and by fab.

However, in any country and in any fab, the time to results will be at least a factor of 10 shorter for AFM than for SEM cross section. During the hours necessary to obtain an acceptable SEM result, many lots of bad wafers may be processed and have to be scrapped.

Summary Figure 9. Threedimensional rendering of trench capacitor array.

Figure 8. Multiple trench scans.

More efficient PFA using new AFM

histogram depth (nm)

As an added benefit, higher throughput can create opportunity for additional engineering measurements.

In many cases, cross-section SEM measurements, or physical failure analysis (PFA), could be replaced by AFM scans. Removing a wafer from the lot for PFA incurs costs above that of diverting it for AFM analysis.

Incremental PFA costs include the cost of the wafer lost from the lot plus incremental operator time, while incremental AFM cost is limited to the cost of the tip.

The AFM result is available in a few minutes, whereas the cross section results are not available until some hours later, in the best case. Furthermore, from the AFM data set, many different measurements can be derived by any engineer or operator using offline analysis software.

In comparison, to get a new measurement using SEM cross section, a specially trained PFA person must resection the wafer. Even a slight modification to the cross section to create a different view takes additional hours.

At Infineon, atomic force microscopy has become a necessary technology for monitoring trench depths and CMP processes at the 90 nm node and below. Infineon has developed statistical models that show that their STI etch and trench-capacitor etch processes would benefit from more frequent sampling. A joint development program is underway with KLA-Tencor (validation phase) to develop an AFM having throughput high enough to meet our needs for more frequent sampling without having to commit more floor space and operating budget to additional AFMs. KLA-Tencor will introduce a new AFM in mid-2004 designed for >20 wph throughput. Its stage, active vibration-isolation system and Linnik bright-field/ interferometer pattern-recognition system are based on their successful optical overlay system. The AFM head uses voice coil motor scanners, self-sensing cantilevers, fully automatic tip exchange, communication between the interferometer and AFM, and proprietary "smart" AFM data sampling to accomplish its throughput specifications. The system also provides increased ease of use, repeatability, and uptime.

Using this new AFM, Infineon anticipates 1) better process control using the same number of tools; 2) the ability to respond more effectively to new process issues that may require small-lot or split-lot experiments; and 3) reduced operating costs when compared to physical failure analysis.

Acknowledgements

time Figure 10. Example of measurement repeatability: histogram depth vs. time. The new AFM was able to achieve 3 Ďƒ dynamic repeatability and long-term stability values of 2% or better – including process variation.

The authors would like to acknowledge Jeff Reichert and Wolfram Pitschke of KLA-Tencor for collecting data on the AF-LM 300 system. This paper first appeared in similar form in the March 2004 meeting of SPIE Microlithography.

This article is based on an original article published in the July 2004 issue of Solid State Technology.

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