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A successful selective epitaxial Si1-xGex deposition process for HBT-BiCMOS and high-mobility heterojunction pMOS applications R. Loo, M. Caymax, I. Peytier, S. Decoutere, N. Collaert, IMEC P. Verheyen, W. Vandervorst, and K. De Meyer, K.U. Leuven, ESAT-INSYS

Si1-xGex/Si heterostructures are useful for a wide variety of device applications where device performance is improved by band offsets and/or increased carrier mobility. The use of selective epitaxial growth for the implementation of Si1-xGex has some advantages compared to a non-selective growth process. However, some issues such as thickness non-uniformity (micro-loading on a µm scale and gas depletion on wafer scale) and facet formation have to be solved. In this paper, we give a detailed overview of our selective Si1-xGex growth process in a standard production-oriented chemical vapor deposition system for Ge contents between 0 and 32%. Our process allows layer deposition with no pattern dependence of the growth rate and Ge content (no micro-loading), and with a wafer scale layer non-uniformity better then the accuracy of the measurement techniques (~2%). Facet formation was avoided by choosing the correct growth conditions, and by preventing lateral growth over the mask material. Selective epitaxial layers did not show a degradation of photoluminescence characteristics. The layer quality is further demonstrated by the performance of Si1-xGex heterojunction bipolar transistors (0.35 µm and 0.25 µm technology), and p-type Si1-xGex heterojunction MOS devices (effective gate length down to 70 nm).

Introduction

The implementation of Si1-xGex layers in active device structures is nowadays recognized as an efficient way to improve device characteristics. Currently, chip manufacturers focus mainly on the integration of Si1-xGex in heterojunction bipolar transistors (HBT) in Bi complementary metal oxide semiconductor (BiCMOS) technology1-15. In the next phase, attention will go to the fabrication of Si/Si1-xGex heterojunction CMOS devices to improve the performance of the p-type MOS device16-24, and to elevated Si1-xGex source/drain contacts to reduce short channel effects in CMOS technology 25-29.

For the first two applications, both selective 64

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and non-selective epitaxial growth by means of chemical vapor deposition (CVD) can be used. In the case of non-selective epitaxial growth on patterned wafers, deposition occurs simultaneously in the Si windows (epitaxial growth) and on the mask material (polycrystalline growth)1,6,30. In the case of selective epitaxial growth (SEG), deposition on the mask material is prevented by adding HCl to the gas mixture in appropriate deposition conditions1,29-33. The top layer of the mask material can be oxide or nitride. For BiCMOS applications, SEG has the advantage of replacing the existing implanted base by a grown, in-situ doped boxlike boron profile, which avoids the generation of interstitials. In the case of heterojunction MOS devices, the SEG technique allows the deposition of the required channel material for the active region of the pMOS

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without negatively affecting the nMOS, which is especially important for full CMOS integration.

Elevated Si1-xGex source/drain contacts evidently require a selective growth process.

So, the importance of the availability of a Si1-xGex SEG process for the industrial market is evident. However, the applications mentioned above require good thickness and composition control of the epitaxial layers. Despite the fact that Si1-xGex has successfully been integrated in device structures, there is still a need to improve the growth process. Several groups, who use epitaxial CVD systems for production applications, reported the influence of the mask layout on layer deposition (micro-loading on a µm scale and macro loading (gas depletion) effects on wafer scale4,29-34. Pattern dependence of both growth rate and Ge incorporation are reduced by reducing the total pressure29,31, and by increasing the HCl flow in the gas mixture31,32. Increase of the HCl flow is not an optimal solution for the BiCMOS, because the link-up of the intrinsic epitaxial base with the extrinsic polycrystalline base becomes troublesome2. Other issues, which have to be solved before SEG processes are usable, are facet growth, void formation and defect generation at the sidewalls of the epitaxial layer.

As we report in this paper, we succeeded in the development of Si1-xGex SEG processes which do not suffer from loading effects. The discussion is focused on Si1-xGex layers, grown by reduced pressure (RP) CVD, with Ge contents up to 32%. These high Ge contents are needed for the fabrication of Si/Si1-xGex heterojunction CMOS devices. A change in the mask layout, or of the wafer architecture, may lead to a change of the optical wafer emissivity. This causes a change of the surface temperature during epitaxial growth and, as a result, a change of the growth rate and layer composition30. This thermal loading effect has to be taken into account for both selective and non-selective growth processes at low temperatures and reduced pressures where the growth is kinetically controlled. However, non-selective growth processes on patterned wafers are the most sensitive for those thermal loading effects.

After a short description of our growth and characterization procedures we will first motivate our growth temperature choice. Next, the influence of the growth conditions on loading effects will be discussed. In the section “Avoiding facet growth”, we describe the observed correlations between the facet generation on one hand, and the pattern geometry and different growth conditions on the other hand. Finally, the success of our

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SEG process is demonstrated by the performance of Si1-xGex HBT (both 0.35 µm and 0.25 µm technology) and p-type Si1-xGex heterojunction MOS devices with an effective gate length down to 70 nm.

Growth and characterization procedures

The reduced pressure chemical vapor deposition (RP-CVD) system used in this work is a standard ASM Epsilon 2000 production epi reactor. This tool is a horizontal, cold wall, single wafer, load-locked reactor with a lamp-heated graphite susceptor in a quartz tube. Epitaxial layers were deposited on blanket or patterned 200 mm (001) Si wafers. Before deposition, the wafers received an IMEC clean35,36. The native oxide was removed by a HF dip, followed by a DI rinse and Marangoni dry37. The in-situ bake at 850-900ºC removes all traces of O. The epitaxial layers are defect free with C and O contamination levels below the detection limits of secondary ion mass spectroscopy (SIMS)38.

Epitaxial growth was carried out at reduced pressure (between 10 and 80 Torr). A H2 gas flow in the range of 30 to 40 standard liters per minute was used as carrier gas. Dichlorosilane (SiH2Cl2) and germane (GeH4, 1% diluted in H2) were used as Si and Ge source gases, respectively. Diborane (B2H6, 50 ppm in H2) was used as boron doping gas. Deposition on the mask material has been avoided by adding a carefully chosen amount of HCl to the SiH2Cl2/GeH4 gas mixture during the growth. As an example, Figure 1a shows the HCl flow ensuring selectivity as function of GeH4-gas flow and for a constant SiH2Cl2-gas flow at a temperature of 750°C and a pressure of 10 Torr. The resulting Ge incorporation and growth-rates are shown in Figure 1b.

The development of the SEG Si1-xGex process was focused on 2 applications. The first one is deposition of the base layer for BiCMOS applications where Ge contents between 0 and 15% are required. The second application is the heterojunction pMOS device with Ge contents up to 32%. Process tuning was done on patterned wafers with mask layouts as designed for each application. The wafer architectures are the complicated full BiCMOS and CMOS architectures, respectively, including shallow trench isolation. Their fabrication is described in Reference 2 and 3 (BiCMOS) and in Reference 39 (CMOS).

Thickness and thickness uniformity of thicker epitaxial layers, with a constant Ge concentration, were measured by means of conventional step profilometry as well as by spectroscopic ellipsometry (SE). SE was also used to Summer 2004

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throughput in a manufacturing environment. So, we increased the deposition temperature to 750°C for Si1-xGex and to 750–810°C for Si. These temperatures still are low enough to meet the specifications for Ge and B depth profiles. SIMS profiles of a full BiCMOS stack demonstrate the perfect control of Ge incorporation and growth rate are shown in Figure 2. The wafer-to-wafer repeatability of the epitaxial layer thickness, as obtained for the same growth recipe and identical wafers, is better than 2.0% (Table I, series II).

This is less than the thickness variations of the different layers that build the wafer architecture.

750°C, pressure: 10 Torr, H 2 -gas flow: 40 slm, and SiCl 2 H 2 gas flow: 100 sccm.

Choice of the growth temperature

The HBT base layer consists of an epitaxial layer stack with a linearly graded Ge profile from 15% (substrate side) down to 0%, followed by a Si cap layer of 20-40 nm.

“Standard” Si1-xGex process temperatures are in the 600–650°C range. Our growth conditions include a HCl gas flow high enough to maintain selectivity but low enough to guarantee a good linking between the epitaxial layer with the polycrystalline base (see section “Avoiding facet growth”). The addition of HCl to ensure selectivity makes the growth rate decrease.

However, because the epsilon is a single wafer reactor, high growth rates are mandatory to ensure sufficient 66

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extract the Ge content. The technique allows a fast, accurate, inline and non-destructive analysis, including fast wafer mapping facilities40,41. For the SE measurements Si substrate we used a commercial ASET-F5 (advanced spectroscopic ellipsometry technology) system from KLA-Tencor, which is a production-oriented, completely automated system. The small spot size (28x14 µm2) permits analysis of epitaxial Si1-xGex layers grown in isolated structures with dimensions down to 50x50 µm2. Such window size prevents measurements by Rutherford backscattering spectroscopy (RBS). SIMS was used to extract the Ge profile of more complicated layer stacks, as used in HBT and heterojunction-MOS devices. Scanning electron microscopy (SEM), Plan-view and cross-sectional transmission electron microscopy (TEM) were used to visualize the structural properties. Photoluminescence (PL) measurements were used to study the optical material properties. PL was carried out with a Fourier transform spectrometer equipped with an N2-cooled Ge detector.

The samples were mounted in a continuous-flow He cryostat and excited by an Ar ion laser with a wavelength of 488 nm.

Si/Si1-xGex heterojunction pMOS devices require much higher Ge contents (25–32%) and thinner layers. It is well known that the Ge incorporation increases with decreasing process temperature. In order to avoid layer relaxation, we took a growth temperature of 650°C for the heterojunction pMOS device structure. 650°C allows deposition of smooth, strained, and defect-free 8 nm thick Si0.68Ge0.32 layers.

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Depth [nm] Figure 2. SIMS profile of an HBT base layer, grown at 750°C and 10 Torr.

Loading effects

Definition and causes The term “loading effect” refers to variable deposition rates and layer compositions over the wafer, which are not seen during blanket layer growth, but which are related to variations in the surface topology. The surface topology is composed of fields of Si and of other materials (oxide, nitride, and so on), which can be arranged in features with different sizes and density. The arrangement of these features (form, size and area) is called mask layout. The composition of these features, which are typically made up of layers of different materials (thermal oxide, TEOS oxide, nitride, polycrystalline

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density29,31-34. Furthermore, the growth rate is higher at the edge of open Si windows. Macrosingle Si0.92Ge0.08 20 118.5±3.1 848.1±1.7 Fig 2b I 1/417/2 loading, on the other 20 81.5±3.2 287.5±1.0 Fig 2a single Si0.92Ge0.08 1/417/5 hand, is a non-uniformity 20 112.3±4.8 845.9±3.6 Fig 2b II full HBT 1/387/3 in growth rate and/or 20 113.3±3.1 844.4±1.9 Fig 2b full HBT 1/388/5 composition over larger 20 114.0±4.2 846.1±1.7 Fig 2b full HBT 1/395/3 distances on wafer scale.

20 98.1±2.8 808.9±2.8 Fig 2c full HBT 1/395/4 This is caused by gas 10 102.3±2.9 187.3±3.0 Fig 2a full HBT III 1/476/3 depletion, which occurs 10 98.4±2.6 289.2±1.3 Fig 2a full HBT 1/479/2 in a horizontal reactor 10 143.3±3.0 852.0±2.0 Fig 2b full HBT 1/476/4 chamber and is due to 10 143.9±4.3 834.7±1.2 Fig 2c full HBT 1/479/1 consumption of the Si precursor while the reac10 103.6±1.3 756.3±1.7 Fig 2c full HBT 1/971/1 IV 10 94.1±2.9 288.7±1.2 Fig 2a full HBT 1/971/3 tion mixture flows over the wafer. Gas depletion Table I. Epitaxial layer thickness for different mask architectures, as schematically drawn in Figure 1. The epitaxial happens on both blanket layer thickness has been calculated from step height measurements over the Si surface in the open window and the and patterned wafers, and nitride surface of the mask (see Figure 2) before and after deposition. Within one series, identical growth recipes it leads to a decreasing were used for all experiments. The growth temperature was 750°C, except for series II, where we used 750°C for growth rate along the the Si 1-x Ge x layer and 810°C for the Si-cap layer. The agreement in layer thickness within series II, as observed reactor. Fortunately, the for samples with the same mask architecture and mask thickness, shows the reproducibility of the SEG process. P is effect can be compensatthe growth pressure. ed in different ways: by tilting the susceptor, Si, and so on) with different thicknesses is called the applying temperature gradients, wafer rotation, optiwafer architecture (Figure 3). Both mask layout and mizing the symmetry of the gas flow in the reactor or wafer architecture can influence the loading effect as a combination of these42. In this work, we obtained will be shown (see section “Study of the thermal and excellent thickness uniformity by using wafer rotation chemical loading effect”).

(35 rpm) during processing, a careful fine-tuning of the gas flow distribution in the tube and of the temperaTwo different types of loading effects are often defined ture profile. (see section “Avoiding microloading”.) in literature: micro-loading and macro-loading. Microloading takes place at the microscopic level of individual Several groups, using epi systems for large scale profeatures (islands, windows, and so on). The term refers duction applications, found a strong correlation between to a local variation in layer thickness and composition the filling ratio (defined as the fraction of exposed Si area as function of the structure size and the structure on the mask) on one hand and the growth rate and Ge incorporation on the other hand31-33.

TEOS 20 nm Depending on the growth conditions b) a) Si N 200 nm (especially the HCl flow), the Si1-xGex Poly-Si 250 nm growth rate can both increase and Si N 200 nm Si N 20 nm TEOS 100 nm decrease with increasing filling factor.

TEOS 20 nm Field SiO 100 nm In the section “Identical wafer archiField SiO 450 nm Si substrate Si substrate tecture and different mask layouts,” we will show that this phenomenon TEOS 20 nm c) is related to gas depletion too. We Si N 200 nm will discuss the correlation between Poly-Si 250 nm Poly-Si total gas consumption over the wafer Si N 20 nm TEOS 100 nm 250 nm TEOS 20 nm and the fraction of exposed Si on the Field SiO 450 nm wafer. Because gas depletion happens Si substrate on both blanket and patterned Figure 3. Architecture of BiCMOS integration wafers. a) Simple test structure, b) and c) complete wafers, we prefer the term gas deplearchitecture with small variations in the layout. tion rather than macro-loading. run-nr.

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There are two different causes for micro-loading, although they can interfere with each other. The first cause is due to local variations in gas phase concentration of the precursors for Si, Ge, or the dopants (“chemical loading”). Chemical loading is due to desorption of Siand Ge-bearing species from the mask surface. These species either diffuse away into the gas phase or readsorb on neighbouring Si surfaces. In this way, they give rise to an additional flux of Si species, and thus to locally increased growth rate, depending on local structure size and the structure density.

Avoiding micro-loading We studied the influence of the process pressure on micro-loading by measuring the thickness uniformity of the epitaxial layer in isolated windows (Figure 4a).

A reduction of the growth pressure leads to a strong improvement of the thickness uniformity within a single window. For a growth pressure of 20 Torr or below, the local epitaxial layer thickness variation is reduced to zero (Figures 4b and 4c). This is easy to understand: lower pressures favor gas phase diffusion. This counteracts

The second cause for loading is a temperature effect (“thermal loading”) due to variations in surface temperature. Thermal loading has been described by W. De Boer et al.30,34. During epitaxial growth the wafer is located on a SiC-coated graphite susceptor, which is heated by the radiation of two banks of tungsten-halogen lamps. The wafer is heated by the susceptor (thermal conduction) and by direct radiation from the upper lamps30. The process temperature is well controlled by thermocouples placed in the susceptor. However, light absorption and emission at the wafer surface are defined by the mask layout and the wafer architecture. A change in mask layout or wafer architecture leads to a change of the optical wafer properties and therefore to a change of the surface temperature during epitaxial growth, in spite of careful temperature control. The consequence is a change of the growth rate and layer composition as function of the wafer architecture and mask layout, because the growth rate is an exponential function of the growth temperature. This is the thermal loading effect.

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Both causes for loading effects can be important, as deposition rate is dependent on gas phase concentration as well as on temperature43. Furthermore, the chemical and thermal loading effects can interfere with each other. Thermal loading, for example, leads to a modification of the growth temperature. This results in modifications of the reaction kinetics. These modifications of the reaction kinetics are different for each precursor in the gas phase, because their activation energies are different44. So, the thermal loading effect leads to precursor dependent variations in gas phase concentration over the isolating surface, and therefore to a chemical loading effect. In this view, it has to be taken into account that during Si/Ge co-deposition the Si deposition is enhanced by the deposition of Ge. The increase of the Si deposition rate is expected, because the Ge-H and Ge-Cl binding energies are lower compared to the Si-H and Si-Cl binding energies. Furthermore, an autocatalytic growth effect occurs during the kinetically limited Si1-xGex deposition44.

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Pressure [Torr] Figure 4. a) Schematic view of the thickness non-uniformity within a single window in case of micro-loading, b) SEM view graph of a full HBT base layer. The perfect thickness uniformity shows the absence of a micro-loading effect. c) Thickness non-uniformity in a single window (right scale) and on the full wafer (left scale) as function of growth pressure and for a deposition temperature of 750°C, as obtained from step height measurements.

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the local increase in precursor concentration due to desorption from the mask areas. Local layer thickness and composition variations as function of the structure size and the structure density are not observed for a growth pressure of 20 Torr or below. The reduction of the growth pressure also improves the layer uniformity on wafer scale (Figure 4c), because the concentration gradient along the reactor induced by gas depletion is counteracted by the higher gas phase diffusion.

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The uniformity on wafer scale has been further improved by careful fine-tuning of the gas injectors and the temperature profile, as measured by the thermocouples.

This results in excellent wafer uniformity in both thickness and Ge content over 200 mm patterned wafers as shown in Figure 5 for single Si1-xGex layers (Figures 5a and b) as well as for the more complicated full HBT stacks (Figure 5c). The wafer scale uniformity in layer thickness and in Ge content (the variation in Ge content is less then 0.5 atomic percent Ge) is important, because non-uniformities are directly reflected in the electrical device parameters4. W. De Boer et al. proposed

Figure 5. Layer thickness and deviation from the average value as mea2

sured on patterned 200 mm wafers. The window size is 200x200 µm . a) Si 0.85 Ge 0.15 grown at 750°C and 10 Torr, b) Si 0.72 Ge 028 grown at 650°C and 20 Torr, and c) full Si/Si 1-x Ge x base layer as used for BiCMOS applications, grown at 750°C and 10 Torr.

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to improve the wafer scale uniformity issue by using a sacrificial polycrystalline Si layer on top of the mask material33. Apparently, this is not necessary. The thickness uniformities have been obtained on evenly patterned wafers, with mask layouts as defined by the BiCMOS and CMOS layout rules. It has to be remarked, however, that we use higher H2-gas flows (at least 30 slm) than commonly reported. The higher carrier gas flow increases the gas velocity in the reactor tube, which further reduces the variation in gas concentration for the different species.

Study of the thermal and chemical loading effect Identical mask layout: thermal loading by variations in wafer architecture. We tried to separate the influence

of the thermal and chemical parts of the loading effect.

The influence of the wafer architecture on thermal loading has been studied by processing both single Si1-xGex layers and full HBT stacks on wafers with identical mask layout (i.e., same patterning and same filling ratios), but with different architectures (Figure 3). The first architecture consists of a simple 100 nm oxide/200 nm nitride-cap stack (Figure 3a). The second architecture was the complicated full BiCMOS architecture. Small variations in the architecture (Figures 3b and c) were used to study the importance of the optical wafer properties on thermal loading.

We observed a clear influence of the wafer architecture on the growth rate (Table I). On the other hand, the wafer-to-wafer repeatability in the epitaxial layer thickness, as obtained for the same growth recipe and identical wafers-is better than 2.0% (first three runs of series II). The differences in layer thickness for identical growth recipes processed on different wafer architectures demonstrate the presence of the thermal loading effect.

The variation in growth rate can be explained by a variation in surface temperature, caused by varying wafer emissivity. Even for the simplest architecture, a change in thickness of the mask stack (± 100 nm), leads to a measurable thickness variation of the epitaxial layer (#1/476/3 and #1/479/2). It is striking, however, that we did not observe a measurable correlation between the measured Ge content and the wafer architecture.

Identical wafer architecture: limited thermal loading for different mask layouts. According to W. B. De

Boer et al., thermal loading does not only depend on wafer architecture but also on mask layout30,34. In order to study the influence of the mask layout on thermal loading, we did two other series of experiments. For this purpose, we used wafers with different mask

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geometries but with identical wafer architectures as drawn in Figure 3a (simple oxide/ nitride stack). Different mask levels of our HBT process flow were used for wafer patterning of these specific test wafers. In this way, the filling ratio was varied between 0.2% and 7.35%.

In the first experiments patterned and blanket wafers received a BF2 implantation (dose: 5x1013 cm-2, energy: 20 keV), which gives a gaussian doping profile with a boron peak 190 Å below the Si surface. Next, the wafers were annealed in the Epsilon 2000 system for 60 minutes Variations in light absorption and wafer emissivity will influence surface temperature and cause differences in the boron profile, which are measured by high resolution SIMS. Indeed, 60 minute anneals at 780°C and 800°C lead to differences in full width at half maximum (FWHM) of the boron profile, which are 250 Å and 285 Å, respectively. However, the variations in surface temperature as function of mask layout and for blanket versus patterned wafers are much lower. After 60 minute anneal at 800°C, no measurable differences in FWHM can be seen by high-resolution SIMS on the different wafers, indicating negligible temperature differences (or thermal loading effects) for this series of filling ratios.

The second series of experiments consists of the deposition of a thin non-selective continuous Si film all over the wafer surface, by using SiH4 as Si source gas. Next, a Si1-xGex layer with x ~ 0.14 was grown under selective conditions and at a growth temperature of 750°C. The film grows epitaxially in the Si windows and, because of the presence of the Si nucleation layer, polycrystalline on the nitride. The growth rates for epitaxial and polycrystalline deposition are similar for the given growth conditions, as confirmed by a combination of SE and stepheight measurements. In this way, we could minimize possible chemical loading effects. A possible variation in the optical wafer properties during growth due to the growing polycrystalline layer is neglected.

If it would appear, it would be similar for all wafers.

Figure 6 shows the correlation between the growth rate and the filling ratio of the mask, in case of epitaxial growth in the open Si windows and polycrystalline growth on the mask area. For higher filling ratios, we observed a slight increase in growth rate: from 16.3 nm/min for a filling ratio of 0.2% to 17.3 nm/min for a filling ratio of 7.35%. This corresponds to a temperature difference of approximately 2°C, as estimated from a temperature dependence study of the growth rate for the given growth conditions.

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A comparison of those two results with the results of the previous section of this article shows that variations of the wafer architecture (layer thickness, material) have a much more pronounced influence on the surface temperature than variations of the mask layout.

Identical wafer architecture and different mask layouts: Influence of gas depletion on growth rate. We studied

the influence of the mask layout on the selective epitaxial growth kinetics for a deposition temperature of 750ºC and pressures of 20 Torr and 10 Torr. Again, wafers with identical wafer architectures (simple oxide/nitride stack, see Figure 3a) but with different mask geometries were used. It was our purpose to study the influence of the filling ratios on the growth rate and Ge incorporation while maintaining patterning and pattern density over the wafers. As shown, variations in mask layout have only a limited influence on thermal loading. Earlier, we explained that for a pressure of 20 Torr or below, we do not suffer from local micro-loading (pattern dependency on the growth conditions on the wafer), nor from wafer scale non-uniformities in thickness or Ge content. So, with this experiment gas depletion effects can be studied.

For selective growth at 20 and 10 Torr, strong differences between the correlation of the mask layout and the growth characteristics are observed (Figure 7). At 20 Torr, both growth rate and Ge incorporation show a strong decrease if the total open Si area on a wafer is increased (Figure 7a). The trend is similar to the results published in References 31-33. The growth rate behavior is opposite

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the growth rate is strongly reduced on blanket layers (Figure 7b). In this case a strong temperature effect cannot be excluded due to the absence of the oxide/nitride stack and also gas depletion may become important again.

The influence of the filling ratio on the growth dependence is different for epi0.0 0.0 0.0 20.0 taxial layers with a higher Ge content, 0 25 50 75 100 0 25 50 75 100 which are grown at lower temperatures.

Area Si [%] Area Si [%] At 650ºC the growth rate for selective Figure 7. Growth rate and Ge incorporation as function of the total open Si area, as obtained growth at 10 Torr (~25% Ge) and 20 for selective Si 1-x Ge x growth at 750 °C. a) 20 Torr (H 2 gas flow = 30 slm, SiCl 2 H 2 gas Torr (~32% Ge) is slightly higher on flow = 100 sccm, GeH 4 gas flow = 20 sccm, HCl gas flow = 49.5 sccm) and b) 10 Torr blanket wafers compared to patterned (H 2 gas flow = 40 slm, SiCl 2 H 2 gas flow = 100 sccm, GeH 4 gas flow = 200 sccm, HCl STI wafers. This behavior is opposite to gas flow = 67.6 sccm). the one observed at 750ºC. We did not yet study the loading effect in more to the behavior as expected from thermal loading detail for these growth conditions, but it is evident (Figure 6). Furthermore, a temperature decrease that at 650ºC mass-transport in the gas phase is of less (increase) would lead to a decreased (increased) growth importance, because of the reduced absolute temperarate together with an increased (decreased) Ge incorpoture. As a result gas depletion will also be of less ration. Because we do not suffer from micro-loading importance. effects, we explain the obtained correlation between the filling ratio on one hand and the growth rate and Ge Solving the problems of micro-loading and gas depletion incorporation on the other hand by gas depletion. Gas The presence of thermal loading effects makes it necesconsumption of each component over the wafer is sary to do the fine-tuning of the SEG process on wafers reduced for patterned wafers, and it scales with the with the same wafer architecture as used for the final filling ratio. This explains the increased growth rate for device structures. On the other hand, the influence of the reduced filling ratio. A change in gas consumption mask layout on growth conditions is limited and also of leads to higher partial pressures of all components. less importance for device applications. This is because Because the incorporation of one component is influenced the mask layout is fixed for each specific application and by all other components, a correlation between the Ge defined by the corresponding layout rules (contacting content and the filling ratio might be expected. The scheme, etc.). For a growth pressure of 20 Torr or below, local thickness uniformity is not affected by the filling the local epitaxial layer thickness variation (micro-loading) factor, and wafer scale uniformity can be maintained is reduced to zero as shown in Figures 4b and 4c. The by a slight modification of the temperature profile. wafer scale uniformity can be improved by a careful fine-tuning of the gas injectors and the temperature At 10 Torr, the influence of the filling ratio on growth profile (Figure 5). For a growth pressure of 10 Torr, gas rate and Ge incorporation is much less pronounced. depletion is not considered an issue.

An increase of the filling ratio from 0.2% to 7.35% leads to a small enhancement in growth rate. The Ge Avoiding facet growth incorporation goes down with increasing filling ratio.

Once the conditions for selective epitaxial growth are Apparently, the gas depletion effect is strongly reduced. tuned, to prevent nucleation on the mask material and As mentioned earlier, the concentration gradient induced to obtain the required layer uniformities (in thickness by gas depletion is counteracted by the higher gas phase and in composition), the issue of layer morphology diffusion for lower growth pressures. Further-more, gas becomes important. A well-known problem is facet velocity is enhanced at reduced pressure and unchanged generation29,45,46. Facets are slower growing planes, gas flows. In fact the growth rate enhancement (3.8%) which cause a thinning of the epitaxial layer near the is close to the value due to thermal loading (6%). The pattern edge area. In general, facets are undesirable small reduction in Ge incorporation (Figure 7b) can also for technological applications, because they result in be explained by a temperature enhancement. At 10 Torr, 74

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insuperable issues during further device processing.

Despite the fact that facet growth has been studied for quite some years, facet formation is still an important issue for the complicated layer stacks (which are part of the devices) discussed in this paper.

We studied the facet formation on simple test wafers with oxide or nitride patterning and with sidewalls oriented along the <110> direction. Facet formation is related to both the pattern geometry and to the growth conditions. We observed two different types of facets. {111} facets are correlated with a lateral growth over the mask material. This explains their existence in case of epitaxial growth in windows with a sloping sidewall geometry (Figure 8a). For sharp vertical sidewalls, no {111} facets appear as long as lateral growth over the mask material is prevented (Figure 8b). In the case of lateral overgrowth, defects are observed at the Si/mask interface, together with the {111} facets. {311} facets are correlated to the epitaxial growth conditions, especially the growth temperature, as long as the vertical sidewalls of the mask are sharp (Figure 8b and Figure 9).

In this case, {311} facets are only seen for high deposition temperatures (Figure 8b). They do not appear at lower temperatures, which allows facet-free epitaxial growth (Figure 9). The critical temperature for facet-free layer growth (~825ºC in case of Si), depends only to a small extent on the mask material.

Figure 8. Correlation between the mask geometry and facet formation. a) A sloping mask geometry leads to lateral overgrowth over the mask material. As a consequence, {111} facets are generated. b) The generation of {111} facets is avoided by the preparation of mask windows with sharp sidewalls. (The deposition temperature of the Si layer was 850°C, the growth pressure 40 Torr.)

Figure 9. Cross-sectional SEM view graph, showing a facet-free epitaxial Si layer, grown at 700°C and 20 Torr.

The growth conditions as used for the full HBT base layer allow a facet-free growth of the full layer stack (Figure 4b). Growth appears simultaneously on the open Si surface and on the polycrystalline base contact.

Facet formation is avoided by defining a negative slope in the lateral undercut of the TEOS layer, which avoids lateral growth over the TEOS sidewall. The use of an optimized HCl flow permits a perfect linking to the base contact2. No voids are seen between the base polycrystalline base contact and the monocrystalline Si/Si1-xGex base layer.

The situation is somewhat different for wafers with shallow trench isolation (STI), as used for Si/Si1-xGex pMOS devices. Figure 10a shows a SEM cross-section micrograph of a standard STI wafer. Epitaxial growth happens on all open Si surfaces. It is clear that lateral growth over the SiO2 cannot be avoided for this surface geometry. Furthermore, the Si surface has a corner at the edge. It is not a planar (001) surface.

Epitaxial growth happens on all Si surfaces, which creates further distortions from the ideal planar surface, with a multi-faceted epitaxial layer as a result (Figure 11a). Furthermore, defects are detected in the faceted area, laterally grown over the oxide. To avoid lateral growth over the mask layer, we need a highquality smooth Si surface with a well-defined and sharp vertical oxide or nitride sidewall at the edge of the open window. On standard STI wafers, we can reach this by uniform etch of the Si layer. A conventional dry etch is not an option, because this degrades the surface quality. Figure 10b shows a STI wafer after an in-situ etch back of the Si surface executed in the ASM Epsilon 2000 tool. Vapor HCl diluted in the H2 carrier gas was used to etch the Si at a temperature of 850ºC. Again, good wafer-scale uniformity can be reached by a Summer 2004

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careful fine-tuning of the temperature profile. The measured non-uniformity of the etch rate over the wafer is within the accuracy of the step height measurement.

The etch rate is high enough for production applications (~15 nm/min) and permits nanometer control of the removed Si. The etch uniformity within single windows is also excellent. Therefore, lateral overgrowth can be avoided by using the developed in-situ vapor etch before the epitaxial growth. This allows deposition of facet-free and defect-free epitaxial layers, as shown in Figure 11b for the full Si/Si0.68Ge0.32/Si layer stack used in heterojunction-MOS devices.

Successful SEG Si1-xGex process implementation

The integration of Si1-xGex SEG processes in production lines requires the fabrication of high-quality material.

TEM images of all epitaxial layers show a high degree of perfection, characterized by smooth surfaces and planar interfaces between the sublayers. Defects or dislocations were not detected within the resolution limit of the measurement. Another very sensitive technique to study

Si0.85Ge0.15

Figure 10. Cross-sectional SEM view graphs of patterned STI wafers

Si

without epitaxial layer. a) After standard processing, and b) after a

TO

controlled Si etch back.

NP

PL-Intensity [a.u]

TO+O

Figure 11. Influence of mask geometry

TA

blanket

STI wafer single window (230x230Âľm2)

Si0.68Ge0.32 NP TO

Si

on facet formation. blanket

a) Cross-sectional TEM micrograph of

STI wafer array of dots with a Si area of ~ 38%

a Si/Si 0.68 Ge 0.32 layer stack, selectively grown on standard

700

STI wafers (shown in

800

900

1000

1100

1200

Energy [meV]

Figure 8a). Facets are formed at the edges of the window. b) Cross-sectional TEM micro-

Figure 12. 10 K photoluminescence spectra of Si/Si 1-x Ge x /Si layers

graph at the edge of a window of a facet-free Si/Si 0.68 Ge 0.32 /Si

measured at a laser excitation power of 50 mW/mm 2 . The deposition

layer. Facet formation on the STI wafer is avoided by an in-situ vapor

conditions are similar as for the active layers in HBT devices (15% Ge),

back etch of the Si surface.

and heterojunction CMOS structures (32% Ge), respectively.

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in the energetic position of the Si1-xGex luminescence.

The position of the Si1-xGex NP-luminescence is in agreement with the bandgap as calculated for the measured Ge contents. No degradation of the PL spectra is observed for the epitaxial layers grown on the patterned structures. The small peak around 820 meV is correlated to the mask material and not to the epitaxial structure.

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Figure 13. HBT current gain as function of the collector current I C and for different effective emitter lengths.

the material quality is the measurement of photoluminescence (PL) characteristics. Si/Si1-xGex quantum well structures have been grown on both blanket and patterned wafers with STI isolation. Deposition conditions as used for the HBT and heterojunction CMOS structures were tested. The PL spectra as measured at 10 K (Figure 12) are typical for high-quality, two-dimensional Si/Si1-xGex/Si heterostructures47,48. High-intensity, well-resolved NoPhonon (NP) transitions and their phonon replicas (transversal acoustic TA, transversal optical TO and two phonon replica TO+OΓ with OΓ the optical zone center replica) arising from the two-dimensional Si1-xGex layers were observed. The small differences in Ge incorporation between the patterned and blanket wafers as observed for a growth temperature of 750ºC is reflected

Ic(at Vbe=0.55 Volt) [A]

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6 10

Nevertheless, the final argument to implement epitaxial Si/Si1-xGex layers in active device structures is given by the device performance. As mentioned above, IMEC developed 0.35 µm and 0.25 µm Si1-xGex BiCMOS technologies, including a selectively grown Si/Si1-xGex base layer. Furthermore, Si/Si1-xGex layer stacks, with x up to 32%, have been implemented in our standard CMOS process (effective gate length down to 70 nm) to improve the p-channel MOS devices. Device fabrication and a full overview of device characteristics are described in References 2 and 3 (BiCMOS) and in 18-20 (heterojunction pMOS), respectively.

HBT devices with an effective emitter area of 0.3 x 5.5 µm2 show maximum FT and Fmax values at VCE = 3V of 50 GHz and 80 GHz, respectively.

Pattern dependence after full device processing has been investigated by measuring HBT devices with different emitter lengths (Figure 13). The current gain plots show that the peak current is unaffected by the reduction of the emitter length, down to device 160 140

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Percent

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VGS[V] Figure 15. Extracted hole mobilities for Si/Si 1-xGe x heterojunction pMOS devices and a Si reference device as measured at V DS = 20 mV (top), 50 mV (middle), and 100 mV (bottom). 30/15: 2 nm Si-cap/8 nm

Figure 14. Normalized collector current ( I C ) from an isolated npn HBT

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device and arrays with 1000 npn devices.

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geometries of 0.35 x 0.35 µm2. The absence of any micro-loading effects during epitaxial growth is further confirmed by the independence of the collector current from the transistor density. This is shown in Figure 14, where the collector current of isolated devices and of an array of 1000 devices are compared.

The long channel hole mobilities as extracted from Si/Si1-xGex and Si reference pMOS devices are shown in Figure 15. Compared to Si-only devices the Si/Si1-xGex devices exhibit strongly enhanced mobilities (up to a factor 2.5). The enhanced hole mobility is a direct indication for the high material quality after full device processing. Any imperfections in the Si1-xGex layer or at the Si/Si1-xGex interfaces would lead to scatter center, and, as a consequence, to a reduced hole mobility. The enhanced hole mobility results in a strong enhancement of the drive current of Si/Si1-xGex pMOS devices compared to Si reference devices (Figure 16). The drive current enhancement has been observed for the entire channel length range from 10 µm (55%) down to 70 nm (13%, at gate-source voltage minus threshold voltage Vgs-VT = -1 V, and a drain-source voltage of -1.5 V).

The improved on-state characteristics have been obtained ref. A Struct. C Struct. B Struct. A

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600 500

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Increase of about 10%

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0

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Vgs-VT [V]

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0

0.5

Vgs [V] Figure 16. Drain current-gate voltage characteristics of Si 1-x Ge x heterojunction pMOS devices and a conventional pMOS as measured at two different drain-source voltages (V DS = -0.1 V and V DS = -1.2 V).

The channel length L mask is 70 nm. Structure A: 3 nm Si-cap/8 nm Si 0.85 Ge 0.15 /5 nm Si/8 nm Si 0.68Ge 0.32/5 nm Si, structure B: 3 nm Si-cap/8 nm Si 0.68 Ge 0.32 /5 nm Si/8 nm Si 0.85 Ge 0.15 /5 nm Si, and structure C: 3 nm Si-cap/8 nm Si 0.68 Ge 0.32 /15 nm Si. I DS : drain-source current, V GS : gate-source voltage, V T : threshold voltage.

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without degrading leakage current, short channel and drain induced barrier lowering behavior18-20. The drive current enhancement is less pronounced for shorter channel lengths, which is due to velocity saturation.

According to literature, a higher current enhancement is expected for ultra-short channel lengths, which has been correlated to velocity overshoot22.

Conclusions

We reported a selective epitaxial Si1-xGex growth process with controllable and reproducible Ge incorporation and growth rates. The epitaxial layers show a high degree of perfection, characterized by smooth surfaces, planar interfaces between the sublayers, and the absence of defects, which has been verified by PL measurements.

Local pattern dependency of the growth rate and Ge content (micro-loading) has been avoided by reducing the growth pressure to 20 Torr or below. Furthermore, a wafer scale layer non-uniformity within the accuracy of the measurement techniques has been reached after fine-tuning of the temperature uniformity and the gas flows. On the other hand, thermal loading cannot be excluded and makes it necessary to perform the final fine-tuning of the deposition process on integration wafers with the exact device architecture. The discussed influence of the mask layout on the growth conditions is of less importance for device applications. This is because the feature size is fixed and defined by the layout rules of the specific application (contacting scheme, etc.)

Facet formation is related to both pattern geometry and growth conditions. {311} facets appear only at high deposition temperatures (above ~ 825ºC in case of Si deposition), while the generation of {111} facets is correlated with a lateral growth of the growing surface over the mask material. A controllable in-situ HCl chemical vapor-etch has been developed in order to modify the height of the Si surface relative to the mask material. This pre-epi surface modification has been applied on wafers with STI isolation to deposit facetfree Si/Si1-xGex layer stack as used in p-type heterojunction MOS devices. The avoidance of facet growth, together with the obtained layer uniformities permit a successful implementation of Si1-xGex in device technologies. This is demonstrated by the excellent performance of Si1-xGex BiCMOS and p-type heterojunction MOS devices. Electrical test results of finished BiCMOS transistors do not only express the layer quality but also confirm the layer uniformity. The epitaxial layer quality is further expressed by the hole mobility as extracted from p-type Si/Si1-xGex heterojunction-MOS,

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which is clearly higher compared to the universal mobility curve of Si pMOS devices. The up to 2.5 times higher hole mobility results in a 55% and 13% higher on-state current for long and short channel devices, respectively.

Acknowledgement

The authors wish to thank Dirk Rondas for technical assistance and Frank Vleugels (SEM), Luc Geenen (SIMS), and Olivier Richard (TEM) for analytical measurements.

Furthermore, we wish to thank the Institut für Schichten und Grenzflächen, Forschungszentrum Jülich for the use of their PL set-up. Parts of this work have been financed by the EU SIGMUND Project nr. IST-199910444, and by the EU Medea T555 Project.

This paper first appeared in similar form in the Journal of the Electrochemical Society Vol 4 150 (no 10), pp.

638-647 (2003).

References 1. A. Gruhle, Proceedings of the 2001 BIPOLAR/BiCMOS Circuits and Technology Meeting (BCTM), p. 19 (2001) 2. R. Kuhn, S. Decoutere, M. Caymax, F. Vleugels, E. Verschooten, R. Loo, and J-L. Loheac, Proceedings of the 29th European Solid-State Device Research Conference (ESSDERC99), p. 436 (1999) 3. S. Decoutere, F. Vleugels, R. Kuhn, R. Loo, M. Caymax, S. Jenei, J. Croon, S. Van Huylenbroeck, M. Da Rold, E. Rosseel, P. Chevalier, and P. Coppens, Proceedings of the 2000 BIPOLAR/BiCMOS Circuits and Technology Meeting (BCTM), 2000, p. 106 4. K. Wolf, W. Klein, A. Berthold, S. Gröndahl, T. Huttner, S. Drexl, M. Seck, and R. Lachner, Proceedings of the 31st European Solid-State Device Research Conference, Frontier Group, 2001, p. 447 5. J. Böck, T.F. Meister, H. Knapp, D. Zöschg, H. Schäfer, K. Aufinger, M. Wurzer, S. Boguth, M. Franosch, R. Stengl, R. Schreiter, M. Rest, L. Treitinger, Proc. of the International Electron Devices Meeting 2000, p. 745 6. J. L. Regolini, J. Pejnefors, T. Baffert, C. Morin, P. Ribot, S. Jouan, M. Marty, A. Chantre, Materials Science in Semiconductor Processing 1, 317 (1998) 7. T. Hashimoto, F. Sato, T. Aoyama, H. Suziki, H. Yoshida, H. Fuji, and T. Yamazaki, Proc. of the International Electron Devices Meeting 2000, p. 149 8. E. Ohue, R. Hayami, K. Oda, H. Shimamoto, and K. Washio, Proceedings of the 2001 BIPOLAR/BiCMOS Circuits and Technology Meeting (BCTM), 2001, p. 26 9. R. Tang, C. Leung, D. Nguygen, T. Hsu, L. Fritzinger, S. Molloy, T. Esry, T. Ivanov, J. Chu, M. Carroll, J. Huang,

U

B

S

T

R

A

T

E

S

W. Moller, T. Campbell, W. Cochran, C. King, M. Frei, M. Mastrapasqua, K. Ng, C. Chen, R. Johnson, R. Pullela, V. Archer, J. Krska, S. Moinian, and H. Cong, Proceedings of the 2001 BIPOLAR/BiCMOS Circuits and Technology Meeting (BCTM), 2001, p. 102 10. P. Deixler, H.G.A. Huizing, J.J.T.M. Donkers, J.H. Klootwijk, D. Hartskeerl, W.B. De Boer, R.J. Havens, R. van der Toorn, J.C.J. Paasschens, W.J. Kloosterman, J.G.M. van Berkum, D. Terpstra, and J.W. Slotboom, Proceedings of the 2001 BIPOLAR/BiCMOS Circuits and Technology Meeting (BCTM), 2001, p. 30 11. H. Baudr y, B. Martinet, C. Fellous, O. Kermarrec, Y. Campidelli, M. Laurens, M. Mar ty, J. Mourier, G. Troillard, A. Monroy, D. Dutartre, D. Bensahel, G. Vincent, and A. Chantre, Proceedings of the 2001 BIPOLAR/BiCMOS Circuits and Technology Meeting (BCTM), 2001, p. 52 12. F.S. Johnson, J. Ai, S. Dunn, B. El Kareh, J. Erdeljac, S. John, K. Benaissa, A. Bellaour, B. Benna, L. Hodgson, G. Hoffleisch, L. Hutter, M. Jaumann, R. Jumpertz, M. Mercer, M. Nair, J. Seitchik, C. Shen, M. Schiekofer, T. Scharnagl, K. Schimpf, U. Schulz, B. Staufer, L. Stroth, D. Tatman, M. Thopson, B. Williams, and K. Violette, Proceedings of the 2001 BIPOLAR/BiCMOS Circuits and Technology Meeting (BCTM), 2001, p. 56 13. A. Schuppen, J. Berntgen, P. Maier, M. Tortschanoff, W. Kraus, and M. Averweg, III-Vs-Review. 14, 42 (2001) 14. D. Knoll, B. Heinemann, R. Barth, K. Blum, J. Drews, A. Wolff, P. Schley, D. Bolze, B. Tillack, G. Kissinger, W. Winkler, and J. Osten, Proceedings of the 28th European Solid-State Device Research Conference. Editions Frontieres (ESSDERC98), 1998, p. 140 15. K. Schuegraf, M. Racanelli, A. Kalburge, B. Shen, C. Hu, D. Chapek, D. Howard, D. Quon, D. Feiler, D. Dornisch, G. U’Ren, H. Abdul-Ridha, J. Zheng, J. Zhang, K. Bell, K. Ring, K. Yin, P. Joshi, S. Akhtar, T. Lee, and P. Kempf, Proceedings of the 2001 BIPOLAR/BiCMOS Circuits and Technology Meeting (BCTM), 2001, p. 147 16. Y.-C Yeo, Q. Lu, T.-J. King, C. Hu, T. Kawashima, M. Oishi, S. Mashiro, and J. Sakai, Proc. of the International Electron Devices Meeting (IEDM) 2000, p. 753 17. J. Alieu, T. Skotnicke, J.-L. Regolini, and G. Bremond, Proceedings of the 29th European Solid-State Device Research Conference (ESSDERC‘99), 1999, p. 292 18. N. Collaert, P. Verheyen, K. De Meyer, R. Loo, and M. Caymax, accepted for the ULIS workshop 2002, Munchen, Germany, p. 77 19. N. Collaert, P. Verheyen, K. De Meyer, R. Loo and M. Caymax, submitted for publication in Solid State Electronics 20. N. Collaert, P. Verheyen, K. De Meyer, R. Loo and M. Caymax, in proceedings of the IEEE Nanoelectronics workshop, June 9-10, Honolulu, 2002, p. 15-16, IEEE Transactions on Nanotechnology Vol 1, 190 (2002) Summer 2004

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S

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B

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21. M.J. Palmer, G. Braithwaite, T.J. Grasby, P.J. Phillips, M.J. Prest, E.H.C. Parker, T.E. Whall, C.P. Parry, A.M. Waite, A.G.R. Evans, S. Roy, J.R. Watling, S. Kaya, and A. Asenov, Applied Physics Letters 78, 1424 (2001) 22. M.J. Palmer, G. Braithwaite, M.J. Prest, E.H.C. Parker, T.E. Whall, Y.P. Zhao, S. Kaya, J.R. Watling, A. Asenov, J.R. Barker, A.M. Waite, and A.G.R. Evans, Proceedings of the 31st European Solid-State Device Research Conference (ESSDERC‘01), 2001, p.199 23. R.J.P. Lander, Y.V. Ponomarev, J.G.M. van Berkum, W.B. De Boer, R. Loo, and M. Caymax, J. Appl. Phys.

88, 2016 (2000) 24. M. Shima, T. Ueno, T. Kujise, H. Shido, Y. Sakuma, and S. Nakamura, 2002 Symposium on VLSI Technology Digest of Technical Papers, p.94 (2002) 25. H. van Meer, S. Kubicek, J. Lyu, M. Caymax, R. Loo, and K. De Meyer, Proceedings of the 29th European Solid-State Device Research Conference (ESSDERC‘99), 1999, p. 388 26. H. van Meer, and Kristin De Meyer, 2002 Symposium on VLSI Technology, Digest of Technical Papers, p. 170 (2002) 27. Gannavaram-S; Pesovic-N; Ozturk-C, Proc. of the International Electron Devices Meeting 2000. Technical Digest. IEDM. IEEE, Piscataway, NJ, USA; 2000, p. 437 28. T. Uchino, T. Shiba, K. Ohnishi, A. Miyauchi, M. Nakata, Y. Inoue, T. Suzuki, International Electron Devices Meeting 1997, IEDM Technical Digest, IEEE, 1997, p. 479 29. I. J. Raaijmakers, H. Sprey, A. Storm, T. Bergman, J. Italiano, and D. Meyer, J. Vac. Sci. Technol. B 17, 2311 (1999) 30. W.B. De Boer and D. Terpstra, Electrochemical Society Proceedings Volume 99-10, 309 (1999) 31. T. I. Kamins, J. Appl. Phys. 74, 5799 (1993) 32. S. Ito, T. Nakamura, and S. Nishikawa, J. Appl. Phys.

78, 2716 (1995) 33. W. De Boer, D. Terpstra, and R. Dekker, Mat. Res. Soc. Symp. Proc. 533, 315 (1998) 34. W.B. De Boer, D. Terpstra, and J.G.M. Van Berkum, Materials Science and Engineering B 67, 46 (1999) 35. M. Meuris, S. Verhaverbeke, P. W. Mertens, H. F. Schmidt, A. L. P. Rotondaro, M. M. Heyns, Third Int. Symp. on Cleaning Technology in Semiconductor Device Manufacturing, 184th Electrochem. Soc. Meeting (1993)

80

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Yield Management Solutions

36. M. Meuris, S. Arnauts, I. Cornelissen, K. Kenis, M. Lux, S. Degendt, P. Mertens, I. Teerlinck, R. Vos, L. Loewenstein, M. M. Heyns, Proc. of the 1999 IEEE Int. Symp. on Semiconductor Manufacturing, 157 (1999) 37. R. Schild, K. Locke, M. Kozak, and M. M. Heyns, Marangoni drying: A new concept for drying silicon wafers, Proceedings of the Second Inter national Symposium on Ultra Clean Processing of Silicon Surfaces UCPSS 1994, 124 38. M. Caymax, S. Decoutere, E. Rohr, W. Vandervorst, M. Heyns, H. Sprey, A. Storm, J.W. Maes, Ultra Clean Processing of Silicon Surfaces. Scitec Publications, 1999. (Proceedings of the 4th International Symposium on Ultra Clean Processing of Silicon Surfaces (UCPSS‘98.), Solid State Phenomena; Vol. 65-66 pp.

237-240 (1999) 39. G. Badenes, R. Rooyackers, E. Augendre, E. Vandamme, C. Perello, N. Heylen, J. Grillaert, , and L. Deferm, J. Electrochem. Soc.. 147, 3287 (2000) 40. R. Loo, M. Caymax, M. Libezny, G. Blavier, B Brijs, L. Geenen, and W. Vandervorst, J. Electrochem. Soc. 147, 751 (2000) 41. R. Loo, M. Caymax, G. Blavier, and S. Kremer, Proc. Of the SPIE. Vol. 4406, p. 131 (2001) 42. D.W. Greve, Materials Science and Engineering B 18, 22 (1993) 43. M . C a y m a x , R . L o o , B . B r i j s , W. Va n d e r v o r s t , D. Howard, K. Kimura, K. Nakajima, Mat. Res. Soc. Symp. Proc. 533, 339 (1998) 44. H.P. Tang, L. Vescan, and H. Lüth, J. Cryst. Growth 116, 1 (1992) 45. T. Aoyama, T. Ikarashi, K. Miyanaga, and T. Tatsumi, J. Cryst. Growth 136, 349 (1994) 46. C.I. Drowley, G. A. Reid, and R. Hull, App. Phys. Lett.

52, 546 (1988) 47. A. Souifi, T. Benyattou, G. Guillot, G. Brémond, D. Dutartre, and P. Warren, J. Appl. Phys. 78, 4039 (1995) 48. R. Loo, M. Caymax, E. Simoen, D. Howard, M. Goryll, D. Klaes, L. Vescan, D. Gravesteijn, H. Pettersson, and X. Zhang, Thin Solid Films 336, 227 (1998)