Summer00

S U M M E R

2 0 0 0 Vfb:SPV=O

Dit:from slope

Tox:dQ/dVs

8

55

74

50 Matching Automated CD SEMS in Multiple Manufacturing Environments The ultimate technical performance of CD SEMs is dependent on consistent and tight operational controls, especially in multiple manufacturing environments where system matching is required. Matching and repeatability of CD SEMS can be evaluated using a standard daily monitor wafer.

78 iSupport Fast, Comprehensive, On-line Customer Support Program

55 Improving Process Control for 0.18 µm Technology and Beyond As the industry moves to 0.18 µm manufacturing and beyond, CD measurements alone are not providing enough information about the printed structures. An improved method uses information already collected by a CD SEM to automatically compare the stored image and linescan information of a correctly processed structure to that of the structure being measured.

79 8250 and 8450 Fully Automated CD SEM System

60 Optimizing Yield by Detecting Lithography and Etch CD Process Excursions There are many different yield-limiting excursion signatures in photo and etch, and a given excursion signature at photo may turn into a different excursion signature at etch with a different impact on yield and performance. Many current sampling plans and monitoring schemes miss these excursions. An improved procedure for effective detection of CD process excursions can have a significant impact on yield and revenue.

Product

News

AIT III High-Speed, High-Sensitivity Darkfield Patterned Wafer Inspection System

eS20XP High-Speed, In-Line E-beam Inspection System

65 Run-to-Run Control of Photolithography Processes Because the device fabrication process is extremely sensitive to key photolithography parameters, the benefits of superior process control are significant. Run-to-run (R2R) is rapidly becoming a key process control tool in the semiconductor industry.

Process Parametric Control 74 Analysis of Phosphorous Auto-doping in P-type Silicon Measured using Corona Oxide Silicon Techniques Cross contamination of P-type silicon to N-type carriers or vice versa in the near surface region of the silicon can be detrimental to device performance. In-line monitoring of these near-surface doping effects enhances the ability to diagnose auto-doping problems.

Sections

4

Editorial: The Shrinking Lithography Window

7

Business News Strategic Acquisitions Expand Litho PMC

Yield Management Solutions is published by KLA-Tencor Corporation. To receive Yield Management Solutions contact Corporate Communications at: KLA-Tencor Corporation 160 Rio Robles San Jose, CA 95134 Tel 408.875.4200 Fax 408.875.4144 www.kla-tencor.com For literature requests call: 800.450.5308

25 KLA-Tencor Trade Show Calendar 37 Q & A An interview with KLA-Tencor’s Senior Director of Marketing, Worldwide Support Operations on the iSupport Program.

©2000 KLA-Tencor Corporation.

All rights reserved. Material may not be reproduced without permission from KLA-Tencor Corporation.

Products in this document are identified by trademarks of their respective companies or organizations.

59 Yield Management Seminar Series Summer 2000

Yield Management Solutions

3

Editorial S

E

C

T

I

O

N

S

The Shrinking Lithography Process Window Photolithographers know more about the lithography collaborated on “Improving Process Control for 0.18 µm process than ever before. This knowledge is essenTechnology and Beyond,” which describes the use of tial because the process is more challenging than the 8100XP CD SEM’s capability to control the ever before. With device performance competition patterning process by measuring more than CD pushing designs smaller, all aspects of the process error with pQC (pattern quality confirmation). window are squeezed more tightly. The job of Metrology also the lithography engineer is to integrate each CD contributes to the total component of the system, minimizing its Defect CD budget; KLAcontribution to linewidth and overlay error Stepper Overlay Tencor worked with and defectivity, while simultaneously Motorola APRDL on controlling costs. This month’s issue of “Matching Automated Yield Management CD SEMs in Multiple Solutions examines Manufacturing methods for underResist Reticle Environments” to standing, optimizing, System Model identify and miniand controlling the and mize the measurement lithography system.

Control contribution within a company’s virtual factory.

The contribution of each component should not be considered Working with NEC Scotland, KLA-Tencor used the 2401 individually, but rather as a part macro defect inspection sysof the whole lithography system.

Inspection tem to control aspects of the The optimization and control and Track Metrology strategy encompasses design for stepper which also contribute to CD error in a manufacturing manufacturing, quantification of sources of variation from the environment. Each of these papers stepper, resist system, reticle, and track, and how describes methods which are valuable in designing they interact with each other. manufacturing processes for shrinking budgets.

KLA-Tencor has worked with several fabs to quantify the components of CD variance and helped to prioritize and improve the overall error; this is described in the paper “Optimizing Yield By Detecting Lithography and Etch CD Process Excursions” co-authored

by AMD and KLA-Tencor. The two companies also

4

Summer 2000

Yield Management Solutions

The NEC work also examined litho process defectivity. Current resist, application, and develop systems must work within tighter tolerances; in addition to linewidth errors, failures often result in defect mechanisms. The work done by NEC

Yield Management S O L U T I O N S

EDITOR-IN-CHIEF Kern Beare MANAGING EDITOR Judy Dale CONTRIBUTING EDITORS Carol Johnson Uma Subramaniam David Viera

illustrated the opportunity in better controlling litho defectivity. “Lithography Defects: Reducing and Managing Yield Killers through Photo Cell Monitoring” describes a strategy for quantifying litho defectivity and applying focused improvement through pareto analysis. It focuses on the defect generation process, and represents work which has been successfully implemented in manufacturing at numerous fabs worldwide.

As process tolerances shrink faster than individual variation sources can be improved, it becomes necessary to actively control the process. “Run-to-Run Control of Photolithography Processes” describes how fabs apply Advanced Process Control (APC). Using KLA-Tencor’s recently acquired Control Solutions Division’s Catalyst product, fabs apply APC to tighten CD and overlay performance.

Cost management is also a very important consideration of advanced lithography and control. APC can have significant cost benefit, as can careful application of management strategies. “Enhancing Overlay Metrology Productivity and Stability Using an Off-line Recipe Database Manager” describes how overlay productivity was improved at Texas Instruments’ DMOS 5 fab. At the same time, RDM also helped to improve consistency of performance across multiple measurement tools of multiple generations. This increased utilization, and reduced the variance contribution from multiple measurement systems.

Lithography process budgets require careful attention to CD and overlay control strategies, and to defect management and reduction. Escalating costs in the litho area also require similar attention. We hope that this issue of Yield Management Solutions can help in devising improved lithography strategies.

Be sure to get a copy of our reticle supplement scheduled for this fall, which will contain articles addressing issues in reticle and quality photomask control and optimization.

circle RS#046

ART DIRECTOR AND PRODUCTION MANAGER Carlos Hueso D E S I G N C O N S U LTA N T Harry Wichmann C I R C U L AT I O N A N D A S S O C I AT E E D I T O R Cathy Correia

KLA-Tencor Worldwide C O R P O R AT E H E A D Q U A R T E R S

KLA-Tencor Corporation 160 Rio Robles San Jose, California 95134 408.875.3000 I N T E R N AT I O N A L O F F I C E S

KLA-Tencor France SARL Evry Cedex, France 011 33 16 936 6969 KLA-Tencor GmbH Munich, Germany 011 49 89 8902 170 KLA-Tencor (Israel) Corporation Migdal Ha’Emek, Israel 011 972 6 6449449 KLA-Tencor Japan Ltd. Yokohama, Japan 011 81 45 335 8200 KLA-Tencor Korea Inc. Seoul, Korea 011 822 41 50552 KLA-Tencor (Malaysia) Sdn. Bhd. Johor Bahru, Malaysia 011 607 557 1946 KLA-Tencor (Singapore) Pte. Ltd. Singapore 011 65 782 6788 KLA-Tencor Taiwan Branch Hsinchu, Taiwan 011 886 35 335163

Scott Ashkenaz Vice President, Lithography Module Solutions Summer 2000

KLA-Tencor Limited Wokingham, United Kingdom 011 44 118 936 5700

Yield Management Solutions

5

IT WILL EITHER BE ROUGH WATERS OR SMOOTH SAILING. HOW WILL YOU NAVIGATE THE MOVE TO 0.13µ?

At 0.13µ, the old rules no longer apply. In their place, new complexities are emerging. Including high NA lithography.

Copper/low-k interconnect. And the 300mm wafer. That’s why we’re already charting a course for the 0.13µ transition continuously developing, testing and refining new tools and yield management methodologies that will help you get there. Our process module control solutions combine defect reduction, process parametric control and yield management software systems that are optimized for each process module films, litho, etch and CMP. And while the volume of process information continues to grow, our analysis software quickly reduces it to yield-relevant, actionable data. So you can make better decisions, quicker. Improve yield. And reduce time to market. To be sure, the transition to 0.13µ may not always be smooth sailing. But with our help you can be certain of reaching your destination. For more information, please call us at 1-800-450-5308, or visit us online at www.kla-tencor.com.

ALREADY THERE. ©2000 KLA-Tencor Corporation

S

E

C

T

I

O

N

S

Business News

STRATEGIC ACQUISITIONS EXPAND LITHO PMC Despite advances in lithography, chipmakers are stretching technology limits as they migrate to 0.13 µm and smaller geometries. Deep sub-wavelength lithography — a process that alters the pattern on the reticle to enable the printing of design rules at least 30 percent smaller than the wavelength of light used in the imaging process — is being considered as a necessary approach to successfully transition to the 0.13 µm node.

When utilizing deep sub-wavelength lithography at these geometries, the lithography process window becomes so narrow that chipmakers must have unprecedented lithography process control, in addition to the right tools, to maintain high yields. KLA-Tencor’s Lithography Process Module Control Solution (Litho PMC™) addresses the four critical components that drive the successful implementation of advanced lithography — critical dimension (CD) control, overlay accuracy, defect reduction and simulation/modeling.

KLA-Tencor made several strategic acquisitions that brought new analysis, modeling and advanced process control (APC) capabilities to Litho PMC, augmenting its performance. These capabilities, combined with the defect reduction and parametric process control components that comprise Litho PMC, provide chipmakers with the yield management strategies and lithography process control needed to navigate the transition to 0.13 µm.

Fab Solutions As a result of its acquisition of Fab Solutions in March 2000, KLA-Tencor gained new APC capabilities, including Catalyst APC software. Catalyst

provides a scalable open architecture that supports fab-wide, run-to-run process control and fault detection.

This capability allows engineers to efficiently deploy feed-forward and feedback process controls in all key process areas with a single integrated software solution.

When integrated into KLA-Tencor’s PMC-Net™ yield information network — a critical component of Litho PMC — Catalyst enables the correlation of real-time, in-situ data from a given process tool with in-line defect, metrology, work in progress (WIP) and endof-line wafer sort data already obtained by PMC-Net. The result is vastly improved identification of the key process parameters that adversely affect yield, or which can be tuned to increase device value.

FINLE Technologies KLA-Tencor’s acquisition of FINLE Technologies in February 2000 also added new capabilities to Litho PMC. FINLE’s PROLITH Toolkit of simulation software helps chipmakers reduce lithography development time and costs by reducing the number of experimental wafer runs required to validate a new process. When researching lithography process window issues, PROLITH can be used to narrow the scope of the search and determine the criticality of the process parameters to be investigated. PROLITH can also speed new process development by simulating the performance of new or unavailable materials or equipment.

Combining FINLE’s software with some of KLA-Tencor’s inspection and metrology tools has resulted in the development of KLARITY ProData, a Summer 2000

software tool that standardizes and automates experimental lithography data analysis. Using this technology, customers can speed the insertion of new lithography processes into their production line.

ACME KLA-Tencor further augmented the performance of Litho PMC through its acquisition of ACME Systems in November 1999. With the capabilities gained from ACME, a software developer specializing in yield engineering analysis software used to correlate parametric electrical test and wafer sort yield data with in-line data, KLA-Tencor developed the Klarity ACE software module. Klarity ACE provides low yielding lot, split lot and wafer yield spatial analysis when integrated into PMC-Net. This enables users to clearly identify relationships between in-line data, such as gate CDs, and test data, such as speed bin, to more rapidly identify and resolve process problems that impact device yield, performance and reliability.

Summary KLA-Tencor is continuing to strengthen its technology portfolio through a combination of new product introductions, in-house research and development, and strategic acquisitions. With the new capabilities acquired from Fab Solutions, FINLE Technologies and ACME Systems, combined with KLA-Tencor’s leading inspection and metrology tools, customers can now employ a complete lithography process control solution to optimize the critical areas of lithographic control, and help them successfully transition to the 0.13 µm node.

Yield Management Solutions

7

Defect Reduction F

E

A

T

U

R

E

S

The Advantages of In-line Electron-Beam Wafer Inspection

by Rob Cappel and Jay Rathert, KLA-Tencor Corporation

Electron-beam (e-beam) wafer inspection is emerging from its well-established place in the research and development laboratory and is moving onto the production floor. Changes in both semiconductor technology and economics are driving this expansion, taking advantage of the unique strength of e-beam inspection, and making its use more routine.

The pace of change within the semiconductor industry is unrivaled. The Semiconductor Industry Association road map, the forecast of technology trends for the industry, has been reviewed and updated annually for the last three years. Each revision has accelerated the design rule milestones that indicate the industry’s technological progress. Historically, the industry has paused at each of these milestones to reap the production benefits of its R&D work before leaping to the next node. This is no longer the case, as the economics of the “first mover� advantage create a continuing push to ever-smaller design rules. The period between nodes has been reduced to less than two years, and has brought the predicted arrival date for the 100 nm node, once forecast to appear in 2009, in by more than six years.

The difficulty for fab development and integration engineers tasked with keeping pace with shrinking design rules and the concomitant changes in acceptable process variations, has been compounded by the emergence of new processes and materials in the quest for faster, smaller, low power devices. These new materials, including low-k dielectrics and deep ultra-violet resists, add uncertainty to the process development phase, bringing new issues, interactions, and defect types. Furthermore, the rapidly emerging copper dual damascene 8

Summer 2000

Yield Management Solutions

process is replacing 30 years of aluminum-based experience, while simultaneously introducing new issues, such as high aspect ratio structures and copper interconnect fill. Despite these challenges, chip manufacturers are striving to complete development more quickly, and transfer to production ramp at increasingly higher yields. Once on the production floor, their goal is to drive out systematic failures, learn as quickly as possible, and rapidly attain high yields, while keeping tool utilization efficient and capital costs down.

Industry dynamics require new defect detection solutions

In the face of these economic and technology pressures, defectivity management is more critical today than ever before. To effectively accelerate the development and ramp phases, the engineering team must be able to detect and characterize all defect types, regardless of size, location, or material. The current difficulty in duplicating historically high aluminum yield levels in the new copper processes indicates that the scope of defects that should be considered critical is actually expanding. Dual damascene processing, critical for copper devices, changes the requirements for defect inspection.

While the detection of many surface defects remains important, the emphasis on yield-limiting defects changes from surface defects to defects at the interfaces, such as residues and particles within the trenches, and voids within the copper fill. Current automated optical imaging and light-scattering inspection technologies have limited success detecting physical defects within high aspect ratio structures and cannot detect electrical

F

E

A

T

U

R

E

S

Figure 2. This sub-100 nm defect is from a Metal 1 layer, yet no

Figure 4. The under-etched topography of the via creates localized

grain, color variation, or prior-level defects are discernible. The small

charging, causing the electron yield to increase, resulting in a clear

protrusion is a small micro bridge and almost certainly a killer defect.

voltage contrast signal. E-beam inspection provides the only practical method for detecting these defect types.

inspection system, and appears at first glance to be a “nuisance” defect. However, review on a a tilting review SEM revealed that this “nuisance” defect was actually a small micro bridge and almost certainly a killer defect.

Detection of defects in high aspect ratio structures As the number of device metal layers grows, quality control of interconnect layer issues will have an increasing effect on yield, and the bottom line. Moreover, the detection of partial defects within these high aspect ratio structures is critical since they can impact the reliability and performance of the device as well as lead to fatal defects during the plug fill process. Figure 3 shows a top view, high-resolution image of a small particle at the bottom of a via. The e-beam inspector’s large depth of focus enables the detection of particles, residues, coring, and scumming well beyond the limits of optical detection. It is important to note that this defect would not be detected using the voltage contrast capability of a typical e-beam inspection system, as the defect does not completely block the via.

changes the number of electrons collected from the isolated area relative to grounded area. This difference is detected by the image computer, and indicates a likely fault. In this example, the under-etched via isolates the structure from ground, and results in a localized charging that differs from the reference image. Typically, this difference is quite large, resulting in a clear signal of a problem. Because these defects are electrical in nature, they tend to have a very high correlation to yield. In the absence of e-beam inspection, there are few viable methods to detect defects of this nature.

Customers trying to detect these problems without e-beam inspection technology might wait until final probe six to eight weeks later, leaving many weeks of material at risk. Alternatively, material could be randomly cross-sectioned and defects counted manually.

This inevitably leads to delays and confidence issues when dealing with such a small ample. In this case, the e-beam inspector provides a real-time electrical test with the capability to scan an entire wafer for systematic signatures or random electrical failures.

Detection of voids and electrical defects The electron-beam inspector’s most unique feature, the voltage contrast effect, is illustrated in Figure 4.

Electrically isolated structures charge differently in the presence of an electron beam than the grounded reference structure to which they are compared. The charge

Figure 3. Top view of a small particle at the bottom of a via.

Detecting this kind of defect is made possible only by the e-beam inspection system’s high depth of focus.

10

Summer 2000

Yield Management Solutions

E-beam inspection challenges

Throughput The primary concern with e-beam inspection has been the tradeoff of throughput for sensitivity. Previous generation tools measured whole wafer inspections in terms of days. Advanced e-beam inspection systems are now able to complete a whole wafer in a little more than one hour, making it ready for the fab floor. To effectively maximize throughput, an e-beam inspector needs a high brightness gun and a low noise, high bandwidth collection system. Additionally, the system’s image computer must be fast enough to perform real-time image alignment to a 1/10th pixel level to ensure success in die-to-die comparisons. Thirdly, the system requires a scanning stage with interferometer control to provide both sufficient image acquisition speed, and real-time feed-forward and feedback to the beam scanning system and stage to keep

F

the beam constantly on its intended target. Finally, the system must have advanced image-processing algorithms that are able to keep pace with the hardware while resolving subtle defects and rejecting nuisance and false defects.

Charge control The second significant challenge for e-beam inspection systems is charge control, which is the ability of the system to compensate for material interactions with the electron beam. Without good charge control, the surface of the material being inspected could develop a positive or negative charge, resulting in image distortions, darkened images, or unwanted beam deflections. Random die-to-die inspection is particularly sensitive to this phenomenon, as the pair of die images under comparison must be relatively uniform, with evenly distributed gray levels and no charging artifacts to avoid false defects.

Figure 5 presents a charge-sensitive oxide layer without charge control to illustrate these effects. KLA-Tencor’s propietary charge-control techniques largely eliminate charge-related issues. Charging artifacts can be seen as darkening and “comet tails” on the image.

Yield correlation using e-beam inspection

Customer demonstrations of the eS20 on product wafer have clearly indicated a high correlation between the defects found and e-test results.

be uniform with no charging artifacts. Here the image does not have adequate charge control. Random mode inspection would be impossi-

T

U

R

E

S

In one evaluation of a 0.18 µm design rule aluminum process contact wafer, the system was set up for a whole wafer using a small area on the die, representing about 10 percent of the total die area. In this example, the inspection was focused on voltage contrast effects in an attempt to detect a known localized signature that was optically invisible. The inspection scan time for this whole-wafer test was only six minutes. The electrical signature was clearly found and perfectly matched the yield loss signature seen at final probe. In addition, the system also found many additional random defects that impacted yield. As a result, this customer was able to quickly isolate the cause of the yield loss, implement an immediate fix, and set-up an inspection recipe that could be used to monitor the production line to prevent further occurrences of this problem.

Isolation of in-line yield problems In another example of good yield correlation, the e-beam inspector was challenged with finding a group of yield signatures that had been previously defined at probe: primarily missing vias, blocked vias, or partially blocked vias. The inspector was run at a high sensitivity to accentuate both voltage contrast defect detection as well as small physical defects. All of the signatures were replicated by the e-beam inspector, including the subtle, partially blocked vias (Figure 6). Again, the inspection showed an extremely high correlation to

Dark images, uneven gray levels and charging artifacts

inspection. For die-to-die inspection to work properly the images must

A

Detection of yield signatures

Blocked vias

Figure 5. The importance of good charge control for random die-to-die

E

Partially blocked vias

Partially blocked vias Figure 6. Customer data from a KLA-Tencor eS20 demo at 0.1 µm pixel, demonstrating detection of yield signatures previously found only at probe.

ble; false defects due to variation would be detected.

Summer 2000

Yield Management Solutions

11

F

E

A

T

U

R

E

S

yield (less than 90 percent) and allowed the customer to isolate a yield problem within the line, instead of having to rely on end-of-the-line electrical testing followed by a lengthy and sometimes unproductive failure analysis process.

Tungsten plug fill issues in Cu dual damascene The e-beam inspector has also demonstrated repeatedly that the value in finding fill issues in tungsten plugs is replicated in copper dual damascene. The system has detected sub-surface killer voids as far as three metal layers back that presented no surface indication of failure when using optical inspection methods. Since the number of layers requiring high aspect ratio etch, copper fill and CMP polish is growing, e-beam inspection remains the only practical and reliable way of finding and eliminating these issues.

Optimizing e-beam and optical inspection strategies

The benefits of e-beam inspection are clear, but most fabs are accustomed to operating with an installed base of optical inspection systems. These optical inspectors currently have a better cost of ownership and usually see most defect types of interest. With the pressure to optimize capital expenditures, the optimum solution is to integrate e-beam inspection systems with optical inspection systems to gain the best data at the best cost. (Figure 7).

Throughput Emphasis

Yield

Data Emphasis

Ramp

As the product moves into ramp, understanding of many of the layers will begin to mature. The defectivity is better understood - the types are characterized and known to be systematic or random. In this phase, inspection of well-characterized layers with optically discernible defect types should move toward a lower cost of ownership (CoO) inspection system. The e-beam tool can be used synergistically with darkfield and brightfield optical inspection systems to optimize their recipes to ensure they capture the critical defect types.

Meanwhile, the e-beam inspector should continue to be used to get rapid DOE results for process changes, or to investigate any issues that arise from e-test, particularly on critical interconnect layers.

Finally, as the product moves into full production, and yields approach entitlement, the inspection strategy should emphasize optical inspection for the best-cost containment. The e-beam system should continue to be used in an audit mode to make sure that no new defect types are emerging. Any layers that are not indicating good yield correlation using the optical systems should be moved back to the e-beam systems until they are well understood.

Summary

Optimization Emphasis

R&D

During the development phase of the product, the focus should be on detecting all defect types, at the surface and below, visible, and sub-optical. While characterizing the defects, the quality of the data is paramount, and the e-beam inspection system should be prioritized.

Special emphasis should be given to the electrical layers that can take advantage of the voltage contrast effect.

Production

Next generation processes are creating many challenges. Electron beam inspection provides solutions to help engineering teams surmount these challenges by giving them the means to detect unique defect types impossible to find by any other practical method: defects in high aspect ratio structures, hidden electrical defects, and sub-optical physical defects. Historical challenges in throughput and charge control have been minimized by new developments that dramatically accentuate e-beam inspection’s value. Using the e-beam inspection system in conjunction with optical inspectors in a well-planned strategy can optimize both the CoO and the yield learning rate. circle RS#010

Time Figure 7. Balancing e-beam and optical inspection during the device life cycle.

12

Summer 2000

Yield Management Solutions

Defect Reduction F

E

A

T

U

R

E

S

Surfscan SP1TBI vs. Surfscan 6420: a Performance Comparison

by Dale Guidoux, KLA-Tencor

As the semiconductor industry continues to shrink critical design rule dimensions, the need for increased performance from laser-based surface defect inspection tools has intensified. Prior to 0.25 µm geometries, unpatterned wafer inspection uses focused primarily on Particle per Wafer Pass (PWP) measurements. KLA-Tencor’s Surfscan 6420 became an industry standard, based on its particle sensitivity performance on rough films, particularly metal layers. With the implementation of 0.18 µm and 0.13 µm process nodes, there is a need to detect and classify more defect types than just particles. The unique axi-symmetric collection optics and brightfield channels of the Surfscan SP1TBI, coupled with normal incident angle illumination and oblique angle illumination provide superior defect sensitivity and Real Time Defect Classification (RTDC). The tool can be used to differentiate crystal orginated particles or pits (COPs) from particles, classify EPI stacking faults, mounds and dimples, and detect CMP microscratches, chatter marks and slurry residue.

An additional benefit of the axi-symmetric collection optics on the Surfscan SP1TBI is uniform detection of scratches, regardless of orientation. Systems that use non-symmetric collectors can miss important defects such as slip lines and scratches in certain orientations.

An increasingly important issue in design rules less than 0.18 µm are the presence of COPs on silicon wafers. The Surfscan SP1TBI is able to detect and classify these COPs separately from surface particles by comparing the defect signal from the wide angle collector with the narrow angle collector signal. Previous generations of Surfscans were not able to differentiate COPs from particles. The ability to classify COPs has two advantages. First, certain device performance can be affected by the presence of COPs. IC manufacturers must add epitaxial layers to overcome this problem. Secondly, when performing tool contamination monitoring with test wafers, it is important to measure just the particles added during a process step, and the presence of COP defects in the total count can give false indications of the actual particle trend.

Surface Nanotopography (SNT) is the newest product feature on the Surfscan SP1TBI. It provides the ability to measure surface features with nanometer height variations across a lateral surface dimension in the 0.5 mm to 20 mm range. A primary application for this feature

Nitride

CVD Oxide

Nitride N-Well

Boron

P-Well

Nitride

Influences leakage or breakdown voltage

Si

Nitride

CVD Oxide

Nitride N-Well

P-Well

Figure 1. A small deviation in the underlying silicon topography can lead to leakage or breakthrough, and ultimately device failure. Surface height variations can also lead to depth of focus lithography problems in advanced <0.18 µm processes.

Summer 2000

Yield Management Solutions

13

F

E

A

T

U

R

E

S

6420

400 300 200 100 0

40nmTan 150nm Cu/40nm Tan 100nm ECD Cu ECD Cu CMP Cu W 400nm Wsi 55nm AI 200nm BPSG 300nm Nit 150nm 150nm Nit/35nm Ox 100nm Ox (B) Ox 100nm 100nm Ox (A) 100nm Poly/550nm Ox 200nm Poly/100nm Ox 240nm Poly/300nm Ox Resist C Polished Si 1300nm TEOS 1000nm TEOS 720nm TEOS Tin 70nm Tin/Ti 500/200A

PSL diameter (nm)

500

Figure 2. SP1 sensitivity compared to 6420 on various films.

is to control non-uniform film thickness variation in shallow trench isolation (STI) CMP. Even with all of the new defect classification capabilities on the SP1, sensitivity to particles on rough films still remains a primary requirement of unpatterned wafer inspection tools, and the performance of the Surfscan SP1 is commensurate with the requirements of 0.13 µm processes. The graph in Figure 2 shows that the SP1

A case study comparing defect capture on the Surfscan SP1TBI versus the Surfscan 6420 on electro-chemical deposition (ECD) copper was performed at a customer site. At equivalent thresholds of 0.25 µm, the SP1 captured more than twice as many defects (Figure 3). The defects that were missed by the Surfscan 6420 were reviewed on a CRS laser confocal review station. The size of the additional defects captured by the Surfscan SP1TBI were not all close to the detection threshold, but rather distributed across a wide size spectrum as exhibited in Figure 4.

Surfscan SP1TBI

Surfscan 6420

0.25 µm threshold (1938 defects)

0.25 µm threshold (754 defects)

TBI

Figure 3. The Surfscan SP1

14

has superior sensitivity compared to the Surfscan 6420 for all examples tested. (Note: The sensitivities shown in Figure 2 are obtained from random customer samples.

The performance can be better, depending on the surface quality of the film.)

The oblique angle incident illumination, coupled with S, P or Circular polarization and the high efficiency ellipsoid collector are key to optimizing sensitivity on rough films. This same collector is also effective at capturing surface haze data over a wide spatial frequency range. Haze measurements have proven useful in monitoring film uniformity and surface roughness.

captured more than twice as many defects as the Surfscan 6420.

Summer 2000

Yield Management Solutions

F

0.51 µm spike, 0302 µm LSE on SP1

E

A

T

U

R

E

S

1.10 µm particle

Figure 4. Two types of defects that the Surfscan 6420 missed but the Surfscan SP1 TBI captured easily: a 0.51 µm high spike and a 1.10 µm particle.

This means the SP1 captures more defects (and defect types) than the Surfscan 6420 at equivalent sensitivities.

Another defect type captured by the Surfscan SP1 using the brightfield channel are the “copper swirl” marks shown in Figure 5. As can be seen in the microview close-up, these swirl marks have significant topography contours.

When adopting new tool sets, it is always advantageous to be able to correlate existing baseline data sets with the new tool data. Correlation studies performed between the SP1 and the 6420 show good correlation with the existing 6420 installed base. For example, a recipe was created on the SP1TBI that exhibited a count A

correlation R2 value of 0.979 on a typical oxide layer compared to the Surfscan 6420 count. No changes were made to the existing Surfscan 6420 recipe.

In summary, the Surfscan SP1TBI has better sensitivity and higher throughput (up to 125 wafers per hour), is able to capture a wider variety of defect types and perform real time defect classification on many defect types.

It has proven matching between tools and demonstrated correlation to the previous generation Surfscan 6420 series. It has already achieved a large acceptance at all the top IC, equipment and wafer manufacturers worldwide and has become identified as the tool of choice for both 200 mm and 300 mm installations.

B

Figure 5. Copper swirl marks are another defect type detected using the brighfield channel of the Surfscan SP1 TBI .

5A: Brightfield map of ECD Cu wafer with swirl marks. 5B: Swirl marks captured by SP1 TBI .

Summer 2000

circle RS#013 Yield Management Solutions

15

Cover

Story

Lithography Defects: Reducing and Managing Yield Killers through Photo Cell Monitoring

by Ingrid Peterson, Gay Thompson, Tony DiBiase and Scott Ashkenaz, KLA-Tencor Corporation Rebecca Howland Pinto, Ph.D., Consultant

Defectivity challenges in the lithography module

Recent results have shown that lithography defects previously thought to be cosmetic can affect yield by as much as 15 percent.1 Stains and minor color variations can be translated into blocked contacts, bridging, missing or extra pattern defects, and CD variations during subsequent steps in the process. As a result, managing defectivity during photolithography is as crucial to the contribution of the photo cell to yield as are proper design, control of critical dimension (CD) and overlay, film parameters and electrical parameters.

Many leading semiconductor manufacturers have found that the most effective methodology for controlling defectivity in the lithography module is to supplement after-develop inspection (ADI) with macro and micro photo cell monitoring (PCM) using test wafers. The traditional approach has been to inspect product wafers in-line after the resist has been developed, using a high numerical-aperture, brightfield micro inspection system together with a brightfield/darkfield macro inspection system. While this approach is highly effective for capturing micro defects (such as developer spots, resist lifting and collapse, uncleared patterns, developer nozzle impact patterns, resist-developer residue and amine contamination) and macro defects (such as missing photoresist, focus spots, gross overlay errors and scratches) some compelling studies have shown that several of these defect types have a low capture rate on product wafers. The low capture rate is primarily due to interference from defects from previous layers, or underlying grain or color variation that makes detection of a defect, that is itself represented as a minor color change, challenging. The resulting delay in detecting a tool or process problem can have serious financial consequences, especially for back-end-of-the-line (BEOL) layers, where priorlevel â&#x20AC;&#x153;noiseâ&#x20AC;? is highest. Consequently, lithography process excursions may not be evident until electrical testing several weeks later.2 A photo cell monitor, sometimes called an excursion monitor,2 is a resist-onsilicon or resist-on-oxide-on-silicon patterned test wafer fully processed through the lithography cluster. It may use the same reticles as the product wafer, or use a reticle specifically designed for photo cell monitoring. Macro and micro defectivity are measured on the PCM wafer, the defects are classified using automatic defect classification (ADC) and the critical dimensions (CDs) Spring 2000

Yield Management Solutions

17

C

O

V

PCM Defect

E

R

S

T

Defect After Etch

Figure 1. PCM defects can accurately represent defects on product wafers, and find them earlier in the process. On the left are three examples of defects found on PCM wafers that may cause defects of the types shown on the right, detected on product wafers after etch.

of the resist are measured using scanning electron microscopy (SEM).3 Statistical process control (SPC) charts use the categorized defectivity and metrology data to monitor the performance of the lithography cluster and identify excursions and trends.

The advantage to using a PCM methodology is that the wafer has

21XX micro wafer inspection system

O

R

Y

only one resist film, which dramatically reduces the noise introduced into the inspection by underlying layers, which inevitably have defects, grain, and film-thickness variations — especially in the backend layers. The topography of a PCM wafer is also much simpler than that of a product wafer. As a result the PCM wafer can provide a very sensitive monitor for yield-limiting excursions caused by either equipment- or process-induced defects. Furthermore, the experience of KLA-Tencor’s Yield Management Consulting (YMC) group has shown that roughly 90 percent of defect types seen on product wafers at ADI can be detected by PCM (Figure 1).

Using KLA-Tencor’s 21XX micro and 2401 macro inspection systems, the PCM methodology provides the most efficient and effective inspection strategy for detecting process excursions in the lithography module (Figure 2). The complete equipment set would include reticle requalification using STARlight SL3UV, unpatterned wafer inspection to qualify and monitor the health of the tools using SP1TBI, automatic defect classification using IMPACT ADC on off-

2401 macro wafer inspection system

Figure 2. Poor spin quality can be obser ved visually and captured using automated micro inspection and/or automated macro inspection. In most instances the lowest cost of ownership system that can detect the defect will provide the most benefit. In this case an intelligent sampling strategy would allow the high-speed macro inspection system to capture this defect first – making the micro inspection unnecessar y.

18

Summer 2000

Yield Management Solutions

line optical and SEM review stations, and PMC-Net analysis for aid in tracing the source of the defects and managing the data flow. Finally, the Sample Planner™ program can help develop a custom sampling plan for the fab’s specific needs.

The equipment set and methodology described in this paper have arisen from collective expertise and case studies from many fabs, with the aim of minimizing the contribution of the lithography module to yield loss.

This is accomplished through efficient capture and classification of critical defect types which in turn enable quick response to defect excursions, and best return on investment of the defectivity equipment set, while improving the overall equipment effectiveness of the lithography clusters.

Financial impact of a PCM program

Motorola estimated recently that replacing manual macro inspection with automated macro inspection would prevent more than $4M scrap per year, with a differential average net yearly equipment cost of ownership of $0.4M.4 This estimate was based on assuming a scrap rate from the lithography module of 0.01 percent and 5000 wafer starts/week. In a pilot study they found that the greatest benefit was obtained from 100 percent inspection of output from a new photo cell, which produced sporadic failures due to multiple coat and develop stations, and new software issues. The magnitude and quality of this financial benefit can be applied to macro PCM as well as to macro ADI. The use of PCM has been shown to be effective in managing lithography defectivity. It provides a high signalto-noise ratio and early detection of problems which might not otherwise be recognized, or might be recognized only at test, once yield has been impacted, and after many lots of wafers may have been affected.

Yield impacts of 15 percent have been seen where defects were not otherwise under effective control.

C

• • • • • •

Comets Striations Spins Microbubbles Lifting No resist

Surface Prep

O

V

E

R

S

T

O

R

Y

• Missing • Wrong width • Miscentering

Resist Spin

Edge Bead Removal

Hard Bake

Develop

• • • • • • •

Soft Bake

Align and Expose

Post Exposure Bake • • • • • •

Scumming Developer spots Residue Resist collapse Satellite spots No develop Deformed contacts

Missing Focus error Gross misalign Aperture blade error No exposure Hot spots

Figure 3: A wide variety of defect types can arise in the lithography cell.

The yield impact has significant cost, both through lost material, and through lost fab manufacturing capacity. In the case of multi-product ASIC and foundry fabs, the rise in defectivity may have significant impact on the fab’s ability to satisfy a customer with a small number of wafers of a particular product.

PCM methodology for defect reduction

Defectivity control in the lithography module relies on three steps: 1) optimization for detection of photo problems; 2) establishment of the process performance baseline; and 3) improvement of the baseline.

Introducing the PCM approach to complement ADI information addresses each step.

Photo defects are difficult to detect on product wafers because the noise from the topography, grain and color of the underlying layers confounds the detection of current-layer defects, as mentioned previously. In particular, many lithography defects have low

topography, subtle color variation, and/or small physical extent. All of these characteristics mean that the signal for optical detection is small.

Thus, reducing the denominator in the signal-to-noise ratio by removing the additional challenge of detection on a product wafer raises the capture probability of defects having these characteristics.

Micro PCM Defect Types

Developer spots (Figures 3 and 4) are observed on developer equipment from every vendor, and are one category of lithography-related defects whose capture rate benefits from using a photo-cell monitor wafer. Often classified as missing pattern or extra pattern during in-line monitoring after-etch, and commonly detected on the perimeter of the wafer, these defects can be caused by splash-back after the develop cycle. Possible causes include poor exhaust in the developer cup, developer cup design, or the type of developer nozzle. This defect type is not seen by traditional develop Spring 2000

track particle monitors using bare silicon wafers since its mechanism is dependent upon the surface tension between resist and developer. The surface properties of the resist-coated PCM wafer, however, are favorable for detecting this defect type.5 Developer residue ( Figures 3 and 4) is a defect type found on PCM wafers that monitor via and contact pattern.

Because the defects are very low contrast and have color variation similar to that of developer spots, they are hard to find on production wafers during ADI due to noise from underlying layers. Their spatial distribution is distinctive. Very dense, radial, and typically following the pattern on the wafer, the spatial distribution of developer residue provides an important clue to the source of this type of defect. Developer residues can cause blocked contacts or blocked via openings on the product wafer, which can lead to significant yield loss (Figures 6 and 7). Probable causes include developer CO2 or resist-

Yield Management Solutions

19

C

O

V

E

S

R

T

O

R

Y

Defect

Typical Cause

Comet

• Dried resist on dispense nozzle

Missing and extra pattern, CD error

• Contamination or perturbation on wafer surface

Example

Recommended Inspection System

2401

• Contamination in resist • Changes in surface tension conditions

Lifting Missing and extra pattern

• Inadequate soft bake

2401

• Missed PEB • Over/under priming • Resist dispense rate

Microbubble Broken leads for smaller design rules

• ARC/resist interfacial interaction between substrate, primer and coating

21XX

• Air leak in the resist pump • Mis-adjusted suck back Developer Spot Missing or extra pattern after etch

Developer Residue Blocked contacts after etch

• Splash-back after the develop cycle • Poor exhaust in the developer cup, developer cup design, or developer nozzle type

21XX

• Developer-CO2 or resist-developer interaction • Ph shock

21XX

• Non-optimized develop/rinse conditions Closed or Deformed Contact

• Residue on the contact hole, unoptimized develop program

Satellite Spot

• Resist-developer interaction

Blocked contact or extra pattern after etch Developer Nozzle Residue Bridge between lines

21XX

21XX

• By-product of develop and resist chemistries • Contamination of developer nozzle

21XX

Figure 4. Detecting these common defect types before the wafers leave the lithography cell allows simpler and faster identification of the source of the defects, and results in fewer wafers scrapped or dispositioned for re-work.

20

Summer 2000

Yield Management Solutions

C

O

V

E

R

S

T

O

R

Y

are typically near the center of the wafer or out near the edge, and are due to exhaust imbalance, EBR pressure control problems, or spurts.

EBR width errors come from improper setup of the EBR nozzle or optical EBR exposure. These can result in a reduction of usable wafer area (if too large) or contamination from flaked resist (if too small).

Excursions resolved using Klarity Defect IMPACT classified defects Klarity observed signatures Figure 5. In production, IMPACT ADC classified the Satellite and E 2 Nozzle defects with better than 95 percent accuracy and purity, while Klarity Defect observed their spatial signatures. The trend chart shows that both problems were fixed, and excursions in both defect types were monitored. 9

Microbubbles (Figures 3 and 4) are examples of defects whose size (<< 0.5 µm) makes them difficult to detect at ADI. This defect, which can cause broken leads for devices having critical dimensions less than 0.35 µm, is readily detectable using PCM wafers with high sensitivity inspection. Probable causes include resist dispense rate, ARC/resist interfacial interaction, and interaction between substrate, primer and coating.

While the resist process is typically very clean, an example of a resistrelated defect that can be found through PCM is amine contamination of the deep ultra-violet (DUV) resist.

The contamination can degrade the profile of the resist.

Macro PCM Defect Types

While many lithography process defects are readily detected using micro inspection, some may also be detectable using macro inspection, at substantially higher throughput.

Many errors in resist coating, exposure, develop, and rinse result in defects which cover a relatively large area.

Resist coating errors can come from a number of causes, from poor surface

prep to problems with the resist dispense. These defects can cover large portions of a wafer, but may also be as small as 50 µm. Because they are relatively large, and tend to occur in clusters, they can have significant yield impact.

Resist film defects such as comets may come from contamination in the resist.

A well-defined head points toward the center of the wafer, and a wake of resist thickness variation flares out toward the wafer edge. The head will cause a hard defect, while the tail may result in significant CD variations.

Edge Bead Removal (EBR) splashback comes from solvent which is aspirated and deposits back on the wafer surface during spin, resulting in spots of cleared resist. These spots Cup 3-2 Defect Density (Defects/cm2)

developer interaction; developer precipitates, rinse deficiencies, or resist and developer surfactant bonding.

Hot spots or focus spots are regions where the stepper does not focus properly. These may be due to backside particles which remain on the wafer or are transferred to the stepper chuck. With today’s high numerical-aperture lenses, the susceptibility to hot spots is increasing.

Several of the developer errors listed as micro PCM defects may also manifest themselves at a size detectable by macro inspection.

Inspection equipment set

Apart from the PCM wafers themselves, the inspection equipment set for defect reduction in the lithography module using a PCM approach is identical to that used for ADI. A brightfield inspection system having a high numerical aperture, such as KLA-Tencor’s 21XX, is optimized for capturing low-contrast micro defects like developer spots, residues and microbubbles. Defects having characteristic spatial distributions, such as comets, striations, spin defects, scratches, etc. require a macro inspection system like KLA-Tencor’s 2401.

Contact PCM

Cup 3-3

Poly PCM

Develop Process Related Defects

Develop Process Related Defects

Time Figure 6. Using a PCM wafer based on the actual contact reticle instead of a lines-and-spaces PCM wafer provided much improved correlation to the observed defect density on the product.

Spring 2000

Yield Management Solutions

21

C

O

V

E

S

R

T

O

R

Y

Defect Type: Isolated Closed Contacts

SEM Image of Closed Contact

Optical Image of Closed Contact Defect Description:

Low-Magnification SEM Image

High-Magnification SEM Image

• •

Killer Defect

•

Can be eliminated by optimizing develop program, and/or eliminating bubbles in the developer puddle

Posible cause: micro-bubbles in the developer

Defect Type: Resist residue EDX Analysis Results

Optical Images

Defect Description:

SEM Images

•

Defect can be caused by nozzle residue

•

Can be a killer defect if it lands on top of contact

•

Can be reduced by optimizing develop program (dispense speed and time, DI water rinse speed)

Defect Type: Area of Missing Pattern 0.00-0.20 0.20-0.50

Defect Description:

7

0.50-1.00

9

1.00-1.50

6

1.50-2.00 2.00-3.00

The way these two systems are used together is primarily based on defect type, but also on minimizing cost of ownership. The 2401 is more sensitive to low-level hot spots, and its higher throughput and lower price make it more cost-effective than the 21XX for detecting large-area errors such as bad spin, comets, striations, edge-bead removal errors, etc.

(Figure 2.) The 21XX is essential for detecting small, localized defects.

While the best strategy for implementing the tools depends upon individual circumstances including the complexity of the lithography process and operation of the fab, typically the 21XX and 2401 would be used to scan each PCM wafer every shift during development, and daily during production. The 2401 would typically be used first to filter macro issues.

The wafers would then be inspected for micro defects by the 21XX. Both micro and macro PCM inspection are used for each path through the track and resist combination, since each may fail independently.

After the defects are detected, automatic defect classification is used to separate the defects into types. Once defects are classified, SPC can be applied to track by defect type or by grouping killer versus non-killer defects. The kill ratio of individual defect types would be determined from short loop PCM experiments since the capture rate for many of the lithography-related yield-limiting defects is low for after-develop inspection on product wafers.

3.00-5.00 5.00-8.00 8.00-10.00 10.00-9999.00 0

Optical Review

5

SEM Images of Area of Missing Pattern

Figure 7. Defect types in the lithography cell associated with missing contacts after etch were uncovered using the contact PCM technique. These defect types included: (a) isolated closed contacts; (b) resist residue; and (c) areas of missing pattern.

22

Summer 2000

Yield Management Solutions

Optical ADC should be performed in conjunction with SEM review since some defect types cannot be distinguished optically, but only through SEM review.

After-develop inspection complements the lithography defect reduction program by capturing topographyrelated process-integration defects.

Micro ADI might be employed for 2 or 3 wafers per lot, while macro ADI would be used on 50 percent to 100 percent of the wafers in each lot.

C

Case study 1: AMD SDC

AMD SDC discovered the value of using a photo cell monitor for a critical lithography process having six levels of metal. They found by failure analysis that they had a problem with missing contacts and vias, but neither their in-line inspection results after etch or after develop detected an excursion.6 When they first implemented a PCM methodology they used a lines-and-spaces reticle that mimicked the poly step.

They still found poor correlation between the contact failures and their inspection results.7 The breakthrough came when they created a new PCM using the contact reticle itself. This contact PCM increased their sensitivity to subtle, low-topography defects by reducing the noise contributed to the measurement by the underlying layers of the product wafers. Furthermore, some defect types depend upon the amount of unexposed photoresist on the wafer and its interaction with the developer.

These defect types are usually not detected reliably using a lines and spaces reticle (Figure 6). Using the PMC based on the actual contact reticle enabled the mystery to be solved.

Three defect types in the photo cell were found to be associated with the missing contacts after etch: isolated closed contacts, resist residue and areas of missing pattern (Figure 7).

The low noise of the contact PCM also allowed AMD to detect a repeater on the contact reticle, which they were unable to detect with any inspections using product wafers.7 The missing contact and via problems were found to have four different sources: 1) randomly isolated missing contacts and vias due to a developer program optimization issue; 2) randomly isolated missing contacts caused by a residue falling on the open contact and via after develop, which blocked the etch;

O

V

3) large areas of missing contacts and vias caused by large residues and bubbles in the develop process; 4) the repeater mentioned above.

Although 1) and 2) were indistinguishable under optical review, subsequent SEM review clarified that the sources of these defect types were very different.

Case Study 2: IBM

IBM began to experiment with PCM methodologies when they were dissatisfied with the correlation between product inspections and yield in the photolithography module. After six months of PCM operation, they found that all process excursions were detected, and response time to the excursions had improved significantly.2 The defect types that were identified successfully using PCM included starburst defects, hexamethyl-disilazane (HMDS) flaking, focus spots, printed defects, and dose and resist-thickness variations. These defect types are described and illustrated in Reference 2. Each of them causes yield-limiting defects down the line. Furthermore, the PCM approach allowed the engineers to identify equipment problems quickly, reducing the rework and scrap costs. In some cases, the source of the defects was found months before it may have been found using traditional methods.

Case Study 3: NEC UK

NEC were interested in using automated macro inspection and a PCM wafer to monitor their stepper.8 They created a diffraction-grating reticle with 0.3 µm lines and spaces, and performed a focus-exposure matrix with focus offsets and leveling offsets.

They inspected the wafers on the 2401 and used the results to estimate the process windows. The 2401 detected a slight defocus process excursion, and a slight field tilt process excursion.

(See article on page 35.)

Summary

Photo cell monitoring using a test wafer with a single layer of patterned Summer 2000

E

R

S

T

O

R

Y

photoresist can be cost-effective and can provide defect capture in many cases superior to that of after-develop inspection.

The superior defect capture using a PCM wafer instead of product arises from its single-layer design, which removes the noise contributed by the topography, grain and color variation of underlying layers. This is a particularly important strategy when the defects are low-contrast, which is typical for many of the lithography-related defect types.

The complementary strategy of line monitoring using micro and macro ADI on production wafers makes it possible to (1) catch excursions of critical defects including topography related process integration defects not seen on the PCM wafer; (2) make quick go/no-go determinations of the health of the production lot and process tool module; and (3) disposition product wafers more effectively.

As part of a complete defect reduction program in the lithography module, the use of a photo cell monitor for micro and macro process tool monitoring can provide significant improvement in defect detection, better process tool health plans and faster response time to process excursions. These benefits translate directly into significant savings in rework and scrap costs, and raise the contribution of the lithography module to device yield. Numerous fabs have demonstrated significant improvements in lithography defectivity by establishing defect management through PCM. References 1. Ingrid Peterson, “Defect Reduction Methodology in the Lithography Module,” Proceedings from the XIII Annual Meeting of the SPIE Microlithography Conference, March, 1999, pp 520-528.

2. Eric H. Bokelberg and Michael E. Pariseau, “Tracking the performance of photolithographic processes with excursion monitoring,” MICRO, January 1998.

Yield Management Solutions

23

C

O

V

E

R

S

T

O

R

Y

Focus Offset Results Wafer No. +ve Offset Detected -ve Offset Detected 1 0.05 N -0.05 N 0.1 N -0.1 N 2 0.15 N -0.15 N 0.2 N -0.2 N 3 0.25 N -0.25 N 0.3 N -0.3 Y 4 0.35 N -0.35 Y 0.4 Y -0.4 Y 5 0.45 Y -0.45 Y 0.5 Y -0.5 Y 6 0.55 Y -0.55 Y 0.6 Y -0.6 Y 7 0.65 Y -0.65 Y 0.7 Y -0.7 Y Figure 8. Defocus process excursions were identified by the 2401 by performing a focus-exposure matrix using a PCM wafer, after a problem with the stepper was suspected.

3. John Allgair, Gong Chen, Steve Marples, David Goodstein, John Miller and Frank Santos, “Feature Integrity Monitoring for Process Control Using a CD SEM,” presented at SPIE’s 25th Annual International Symposium on Microlithography, February, 2000.

4. Arnold Yanof, Vincent Plachecki, Frank Fischer, Marcelo Cusacovich, Chris Nelson and Mark Merrill, “Implementation of Automated Macro After Develop Inspection in a Production Lithography Process,” p r e sented at SPIE’s 25th Annual International Symposium on Microlithography, February, 2000.

5. Ingrid. B. Peterson, “Importance of Defect Reduction in the Lithography Module,” Yield Management Solutions, Autumn 1998.

6. Christina Cheung, Robert Chiu, Khoi Phan, Ingrid Peterson, Andy Phillips, Kevin Kan, “Contact Photo Cell Monitor (PCM) for an Advanced BEOL Lithography Process,” in Proceedings of the SEMICON/West Yield Management Solutions Seminar, July, 1999.

7. Private communication.

8. Iain Rutherford, Brian Haile, and Tony DiBiase, “Production QC and Tool Monitoring Using and Automated Post Develop Macro Inspection System,” to be published in Proceedings of the SEMICON/Europa Yield Management Solutions Seminar, April, 2000.

9. Frank Poag, Douglas Paradis, Mahesh Reddy and Jon Button, “Defect Yield Management using the KLATencor Intelligent Line Monitor,” in Proceedings of the SEMICON/ Southwest Yield Management Solutions Seminar, October, 1999.

24

Summer 2000

About the Authors Dr. Ingrid B. Peterson is currently Solutions Development Manager for Lithography and Parametric Module Solutions at KLA-Tencor. She joined KLA-Tencor in 1995 and has held positions as Applications Development Manager for Reticle Inspection Analysis products and as a consultant for KLA-Tencor’s Yield Management Consulting Group. Prior to joining KLA-Tencor, Ingrid worked as a staff process engineer in photolithography, was a staff research scientist at the Max Planck Institute for Solid State Physics in Stuttgart, Germany and was an adjunct assistant professor in the Physics Department at the University of California Los Angeles. Ingrid earned a Ph. D. in Physics from the University of California at Santa Barbara.

Gay Thompson is currently Field Marketing Manager for Defect Module Solutions at KLA-Tencor. She joined KLA-Tencor in 1996 and has held positions in New Production Introduction and Product Marketing for KLA-Tencor’s wafer inspection products. Prior to joining KLA-Tencor, Gay worked as a program manger in the U.S. Air Force, managing the development, production and launch of satellite systems. Gay earned a B.S.E.E. from MIT and a M.S.E. from the University of Texas at Austin.

Tony DiBiase is a director in the Yield Management Consulting division of

Yield Management Solutions

KLA-Tencor. Since 1980, Tony has held various positions in maskmaking, process integration, metrology, lithography development, and maskmaking at National Semiconductor, Synertek, and Synergy Semiconductor. He has a B.S. in Chemistry from the University of Cincinnati.

Scott Ashkenaz is KLA-Tencor's Vice President of Strategic Marketing for Patterning and Parametric Process Module Control Solutions (PMCS), which provides lithographic and parametric alignment among KLATencor's products to improve wafer fab productivity and capability. Prior to joining KLA in 1985, Scott was the Mask Lithography Manager for Austrian Microsystems, and responsible for AMI's advanced mask development program. He attended the Bachelor's and Master's programs in Photographic Science and Engineering at Rochester Institute of Technology.

A former director of marketing with KLA-Tencor, Rebecca Howland Pinto is an independent consultant in technical marketing. A frequent contributor to Yield Management Solutions, Ms. Pinto has published numerous articles and lectured worldwide during her 10 years in the industry. She has a Ph.D. in applied physics from Stanford University, and an A.B. in physics from Dartmouth College. circle RS#046

New look . . . new perspective.

Visit www.kla-tencor.com

Coming soon to a monitor near you.

KLA-Tencor Trade Show Calendar July 10-14

SEMICON/West, San Jose and San Francisco, California

August 2-4

CleanRooms/DataStor Asia, Singapore

September 13-14

BACUS, Monterey, California

September 13-15

SEMICON/Taiwan, Taipei, Taiwan

September 18-20

UCPSS, Ostend, Belgium

September 19-21

Diskcon, San Jose, California

October 3-5

ITC, Atlantic City, New Jersey

December 6-8

SEMICON/Japan, Makuhari, Japan Summer 2000

Yield Management Solutions

1

Yield Management Seminar A valuable venue for innovative ideas KLA-Tencor’s Yield Management Seminars (YMS) focus on value-added, integrated process module control solutions for defect reduction, process parametric control and yield management. Key topics include navigating the transition to the 0.13 µm technology node, with special emphasis on copper/low κ interconnect, sub-wavelength lithography, and the 300 mm wafer.

To reserve your space at the upcoming YMS, contact Tavis Szeto by email at tavis.szeto@kla-tencor.com.

Date: Time: Location:

Tuesday, July 11, 2000 9:00 am – 6:30 pm The Argent Hotel, San Francisco

For information on future YMS, please complete and return the enclosed business reply card.

Call for future papers Papers should focus on using KLA-Tencor tools and solutions to enhance yield through increased productivity and performance. If you are interested in presenting a paper at one of our upcoming yield management seminars, please submit a one page abstract to: Tavis Szeto by fax at (408) 875-4144 or email at tavis.szeto@kla-tencor.com.

YMS at a Glance DATE July 11 August 3 August 9 October 18

24

Spring 2000 Yield Management Solutions

LOCATION San Francisco, California Singapore Hsinchu, Taiwan Austin, Texas

Lithography S

P

E

C

I

A

L

F

O

C

U

S

Application of Automatic Defect Classification in Photolithography

by Gary Stinson, Microchip Technology Inc. and Bo Magluyan, KLA-Tencor Corporation

This paper presents two applications of Automatic Defect Classification (ADC) to monitor and control defect density in photolithography processing. These techniques can also apply to any process module. Many defect types are only generated when wafer pattern is present, while other yield impacting defects are detected only on monitor wafers due to a low signal-to-noise ratio on product wafers. The use of ADC in both cases to find root cause solutions is a powerful tool enabling quick time to results and reduced yield risk in the manufacture of integrated circuits.

ADC is a powerful technique that has truly come into its own in recent years.

Envisioned as a logical progression of defect inspection and review, the ADC concept has been faced with serious technical challenges that have taken time to overcome. Its primary focus is to replace the manual review of defects detected by the inspection systems. Classification accuracy, speed, and cost are all significant factors relating to the justification of ADC, especially for fabs that already have manual classification systems in place. In this paper another perspective concerning the justification of ADC over manual review is presented.

Identifying a defect and finding the piece of equipment or process module that is generating the defect is only the first part of improving yields. Eliminating the root cause is always a difficult task that often requires designed experiments to identify the defect mechanism. When designed experiments are used to solve a defect issue, the output response is the number of the defect type of interest. Depending on the complexity of the process, many wafers may need to be inspected and reviewed to determine the statistical validity of the changes made. Additionally, the confidence level of

results generated from such a study is directly dependent on the accuracy and purity of the classification of the defect.

Microchipâ&#x20AC;&#x2122;s ADC program, consisting of KLA-Tencorâ&#x20AC;&#x2122;s IMPACT ADC, 2135 inspection system, and Klarity Data Analysis is used extensively in this engineering role.

Case 1: Problem description

Yield trends for a new device were trending below expectations. One of the primary failure modes for the device was high standby current. Failure analysis revealed a trench from metal to substrate causing the high standby current failure (Figure 1).

Figure 1. SEM image of device failure.

Summer 2000 Yield Management Solutions

27

S

P

E

C

I

A

L

F

O

C

U

S

The spatial signature of the defect showed a higher density in the center of the wafer. Analysis of multiple die failing for the same bin found that there was a tendency for the defect to occur around specific types of structures. The source of the defect appeared to be between the second poly silicon level and first metal deposition. The crack would travel along the edge of the poly2 until it found relief.

To investigate further, a newly installed KLA-Tencor 2135 with IMPACT ADC was brought on-line. Initial inspections prior to Metal1 deposition detected the defect, which appeared to be a stress-relieving crack in the dielectric. This was allowing the remaining etch processes to trench into the silicon substrate causing the current leakage. Since the dielectric was identical to previous technologies, which were not experiencing the problem, it was suspected that the defect had to be patterned on the wafer in the contact photo step and subsequently etched through to the substrate.

Inspection of wafers after the contact photo step detected the stress crack in the resist as suspected. SEM images showed that the contacts were not distorted, but lifted from the wafer intact (Figure 2).

ADC on product wafers

After the defect was found patterned in the photoresist, the process module was shut down until a solution could be found. Photo engineering evaluated all lithocells qualified for the process to ensure that specifications were being adhered to. All systems were functioning normally and in control. After the setup parameters were verified, monitor wafers were processed with individual photo process steps and film stress measurements were made. Although the stress measurements were tensile, consistent with the formation of these types of cracks, the data failed to indicate a part of the process causing the defects (Figure 3).

Process

Stress (mPa Tensile) Bare Si

BPSG

Prime/Coat

16.4

12.9

Prime/Coat/Soft Bake

15.1

4.6

Prime/Coat/SB/PE Bake

13.5

10.2

Prime/Coat/SB/PEB/Develop

18.4

18

Prime/Coat/SB/PEB/Dev/Expose

14.3

12.3

Figure 3. Film stress data.

While these experiments were being conducted, an ADC classifier based on the initial wafer inspection data was being developed. This rudimentary classifier was constructed from only two wafers from one lot, but since the defect features were unique, the accuracy and purity were high.

ADC was used to generate results for the next designed experiment, which focused on various modifications of the process. Data from the ADC bin for resist cracks was able to show that the number of cracks were reduced on each of the non-standard splits, but were not eliminated entirely (Figure 4).

If manual review utilizing defect sampling were used, it is possible that split #5 could have given a false good result. Not only did ADC return information more quickly, but the data was also more accurate.

Figure 2. SEM image of resist crack.

The sequence of events in the investigative process, from the failure analysis results to locating the defect in the resist took a relatively short period of time.

Solving the problem without significantly changing a critical photo process appeared to be a much more difficult task.

28

Spring 2000

Yield Management Solutions

Since the first tests reduced the number of cracks but did not eliminate them entirely, the root cause was still to be determined. Several process splits were generated, varying the resist thickness and coat procedures. Again, ADC was used to review all the defects detected. This time the data showed the stress cracks to be eliminated on all splits except the standard process. The standard

S

P

E

C

I

A

L

Split

Description

Wafer #

Cracks Found

Split

Description

1

Standard Process

1

33

1

2

12

3 4

2

3

4

5

6

F

O

C

U

Wafer #

Cracks Found

Standard Resist Thickness

7

0

with Split Cast/Dry Steps

12

0

20

14

0

46

21

0

5

21

25

0

Standard Process with

18

7

Modified Prime

20

7

21 Standard Process without ARC

ARC after Soft Bake

ARC after SB,

Thicker Resist with

1

0

Extended Dry Step

8

0

11

15

11

22

9

10

0

23

7

22

0

24

18

25

7

14

Thicker Resist with

2

0

Split Cast/Dry/Step

9

0

5

17

0

17

3

18

0

10

2

rinsed before PEB

13

3

Standard Process with

6

8

extended Prime

2

3

4

23

0

Thicker Resist with

3

0

Modified Prime Step

4

0 0

8

10

5

9

2

10

0

24

0

11

6

13

3

20

3

Figure 4. ADC results of first experiment.

The quickest and best solution was to leave the resist thickness unchanged and implement the changes to the dry step. Within hours, production was resumed with an ADC wafer inspection implemented. After the process change, the ADC classifier detected no additional cracks.

Inspections continued until yield data could be gathered using the new process. A dramatic yield improvement in the form of reduced variation confirmed the data already available from the ADC classifier (Figure 6).

Case 2: Problem description

The second case applies to an incident of contaminated photoresist. A simple EPROM device has historically been used as a defect monitor since it has relatively high circuit density and significantly larger die than the majority of other microcontroller products. Yield

6

Standard Process

Standard Process

6

3

without PEB

19

3

Figure 5. ADC results of second experiment.

trends on this device had not been meeting expected goals. Several failure analysis attempts to identify the cause pointed to 0.5 Âľm to 1.0 Âľm Poly2 bridging between adjacent memory cells, but visual and laser scattering inspections were not able to find the defect Resist Crack Eliminated

Number of Parts Passed

process used a high spin speed for an extended period of time to accomplish both the cast (step used to get the proper thickness) and dry (step used to allow solvents to evaporate). The ADC data showed conclusively that by slowing down the dry step or by increasing the resist thickness, the defect was eliminated entirely (Figure 5).

5

S

Lot Number Figure 6. Parts Passed trend chart shows case 1 yield improvement.

Summer 2000

Yield Management Solutions

29

S

P

E

C

I

A

L

F

O

C

U

S

in-line. A sharp downturn in yield for this device and others relating to the same defect mechanism raised the priority for eliminating the defect.

A KLA-Tencor 2135 inspection system was brought on-line and quickly detected the defect. Resist precipitates that were not being developed away were protruding from the resist lines causing the blocked poly etch (Figure 7).

The defect density was very high indicating that something had gone wrong with the resist quality. All product lines using this resist were shut down until the problem could be solved.

promising. The first experiment was to put the old filter type back on line to see if it would get the problem under control so that production could continue.

Product wafers were processed and inspected using the ADC classifier to measure effectiveness. Although there was a decrease in defect density, it was not significant enough to resume production. More tests were attempted with a new bottle of resist, hand dispensed resist, new resist lines, new resist pump, etc. The defect density and defect size were reduced with each test as the resist delivery system was purged of the contamination.

Production was resumed and the inspection with ADC was used to monitor the defectivity level.

As the precipitates became smaller, it became obvious that background nuisance defects in the underlying poly silicon were causing confusion. A better solution had to be found to monitor for additional excursions.

The product inspection was replaced with a daily patterned resist monitor. The use of monitor wafers brought about new types of defects not seen on product, but since the poly silicon was not present, the accuracy and purity of the classifier were much improved. Monitoring the defect level of the resist ADC bin was successful in measuring additional improvements and monitoring for excursions.

Figure 7. Resist precipitate.

The Photo Groupâ&#x20AC;&#x2122;s efforts to find the source of the defect focused on several possible causes. Photoresist handling and storage techniques were verified to be in spec. Particle tests for contaminated batch also proved to be within the manufacturing tolerances. Yield data vs process dates were analyzed showing the downturn to loosely correlate with a change in resist filter type.

Since the precipitates were larger than the filter rating, and the particle counts of the resist were in spec, there had to be more to the problem than the filter issue.

ADC on monitor wafers

While photo engineering was investigating the resist, an ADC classifier was developed using the initial data that detected the defects in the resist. Overall setup of the classifier took only a few hours and appeared very

30

Summer 2000

Yield Management Solutions

Additional tests indicated that an interaction was occurring between the resist and the pumping system, causing the precipitates to form downstream of the filter. Since no other resist in use was showing the problem, the root cause solution was determined to be a resist change. Qualification of a new resist can take a considerable amount of time especially for a critical layer like Poly2. Using the ADC classifier, a maintenance procedure was identified to control the defectivity until a new resist could be qualified. This procedure was incorporated in the scheduled quarterly PM and involved changing the pump, filter, and chemically cleaning the delivery lines. By having a cleaned pump ready at all times, the time required to perform the procedure did not significantly increase downtime.

As the monitor wafer procedure was fine-tuned, it became possible to control the defectivity by using the raw counts from the inspection. The defect mechanism proved to follow a predictable failure cycle that was controllable through a scheduled maintenance procedure. Defect images captured using the ADC system were still useful to verify the defect type, but the control charts were changed to total counts for simplicity.

Device yield for all products using the resist increased by a step function in response to the actions taken. The resist monitors were changed from daily to weekly as confidence in the maintenance procedures increased (Figure 8).

Summary

In this paper two examples of the use of ADC to find root-cause solutions for yield limiting defect excursions have been presented . The first utilized ADC on product wafer splits since the defect was generated only on wafers with topography. The second example showed that ADC’s capability can be extended beyond the inspection noise level inherent in product inspections by using monitor wafers. By using ADC, useful information from the wafer inspection data was generated faster and with improved signal to noise than if manual review were used. This technique demonstrates the natural extension of ADC from the production-monitoring arena into complex engineering studies to eliminate defects and improve yields.

P

E

C

I

A

L

F

O

C

U

Resist Defect Eliminated

Lot Number Figure 8. Parts Passed trend chart shows case 2 yield improvement.

Presented at 10th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (ASMC), September 8-10, 1999, Boston, MA.

circle RS#015

Are you gambling with your device performance and reliability?

Achieve superior in-line process control of CMP and Etch.

S

Number of Parts Passed

S

In today’s world of complex integrated circuits, smaller device geometries, and higher levels of metallization the chips are stacked high. Really high. The critical production challenges of Etch and CMP process monitoring could zap your yield.

And send your wafers to the scrap heap. Why take chances with your customer satisfaction and profitability?

Rely on our award-winning, production-proven surface metrology solution. The HRP™ Series. An industryleading high-resolution profiler that offers you exceptional throughput, sensitivity, reliability, and repeatability.

And helps you meet the metrology challenges of modern wafer production.

To receive your FREE guide, Process Control Solutions for CMP and Etch, e-mail us at info@kla-tencor.com.

Visit us at www.kla-tencor.com and find out why more than 100 customers around the world rely on the HRP.

Lithography S

P

E

C

I

A

L

F

O

C

U

S

Production QC and Tool Monitoring Using an Automated Macro ADI Defect Inspection System

by Iain Rutherford, Brian Haile and Tony DiBiase, KLA-Tencor Corporation This paper was presented at KLA-Tencor’s Yield Management Solutions Seminar during SEMICON/Europa in April 2000.

The major weakness of traditional, manual after-develop inspection (ADI) lies in the variability of the results. Defect capture rates are variable due to differences in the ability and experience of the inspection operators. Subsequent analysis of defects can also be inconsistent as some operators might flag a defect while others might pass it thinking it unimportant.

Manual inspection is also one of the most tedious and unpopular jobs in the fab among the operators.

The ability to drive yield improvement from manual inspection results can be very poor. Data from manual inspections can be vague and subjective, making it difficult to archive or correlate with yield and parametric results. The bottom line is that manual ADI misses macro defects and costs money.

Manual vs. automated ADI

A solution to these issues is an automated, optical macro defect inspection system such as KLA-Tencor’s 2401. This system was installed for evaluation at NEC in Livingston, Scotland, and this paper reports the results from the evaluation at that site.

The study was conducted in two parts: First, a comparison of manual versus automated inspection using the 2401 for ADI, and second, an investigation of the potential of the 2401 for evaluating and monitoring certain aspects of stepper performance.

Eight layers from one particular product were chosen.

Lots were then randomly sampled from these layers.

The layers represented a typical mix of front-end and back-end layers, both critical and non-critical.

The 2401 works by simultaneously scanning and capturing darkfield and brightfield images of a wafer. The inspected field is compared with two fields adjacent to it and any discrepancies between the two fields are flagged as a potential defect. The system has an 80 wafer-per-hour throughput and can capture defects greater than 50 µm. If needed, wafers can be reviewed using a variety of software tools on the machine.

32

Summer 2000

Yield Management Solutions

Over 5500 wafers were involved in the first part of the evaluation, and most of these (5019) were randomly selected for after-develop inspection. Some wafers with known problems were chosen (225), and some originated from engineering (322). The wafers were inspected manually, then taken to the 2401 for automated inspection.

Figure 1 demonstrates the overall sensitivity of the 2401 compared with manual inspection. While manual inspection found that 3 percent of lots had issues worth Visual Inspection Results

2401 Inspection Results

3%: Failed

97%: Passed

46%: Failed

54%: Passed

Figure 1. With 213 lots inspected at random, 6 lots failed visual inspection while 97 lots failed the 2401 inspection, demonstrating a 10X difference in capture rate when replacing manual with automated macro inspection.

S

p 25

VI Fails

20

2401 Fails

15 10

WW Focus

Lifting Resist

Comets

Poor Coat

Contamination

ILD Issue

Metal Dep Issue

Scratch

Accel

Hot Spot

5

Leveling

C

I

A

F

L

O

C

U

S

p

30

Number Lots

E

p

35

0

P

Figure 2. A breakdown of the detected defect types shows that stepper problems such as leveling, hot spots and acceleration errors dominated. This chart also emphasizes the difference in capture rate between the 2401 and manual inspection.

investigating further, the 2401 found that nearly 50 percent of lots had defect issues of interest to the NEC engineers. These results correspond to a 10-fold difference in capture rate between the automated inspector and the manual inspection procedure at NEC. Examining these results as a function of defect type, Figure 2 illuminates the important fact that the top three defect types — leveling, hot spots, and acceleration errors — are related to the stepper (acceleration errors are caused by movement or vibration of the stepper stage during exposure). Figure 2 also reinforces the difference in capture rate between the 2401 and manual inspection.

Of the 13 ADI defect types that were part of this evaluation, the 2401 was able to capture 10 of them with a “good” rating, and two of the remaining three with a “fair” rating. These qualitative results are tallied in Figure 3. The 2401 failed to capture whole-wafer focus defects, but the next version of software is expected to remedy this omission. The two defect types receiving “fair” ratings are also whole-wafer defect types: no coat and no exposure/develop. The ability of the 2401 to capture these defect types is also expected to improve with the version 2.2 software release.

Defect Type Hot Spot Leveling Acceleration Scratch Contamination Comet Particle Lifting Resist Poor Coat No Coat* No Exposure/Develop* Film Thickness Variation Whole Wafer Focus*

VI Capability Fair Poor Fair Fair Good Fair Poor Fair Good Unknown Unknown Good Good

*WWD software version 2.2 will implement capture Figure 3. Qualitative ratings of defect capture by type for the 2401 and manual inspection further demonstrates the benefits of automated macro inspection.

the lots were only flagged by the 2401 and fell into the “rework/save” category as yield loss would have resulted and the 2401 enabled them to be reworked and rescued.

The most common defect type seen during the evaluation was leveling problems. In particular, nearly 60 percent of metal 2 lots were found with leveling issues. Any problems with the stepper focus or leveling at metal layers can cause catastrophic electromigration failures out in the field. In the case of metal 2, these defects were not caught by manual inspection but the 2401 was able to capture them reliably. Further investigation suggested a solution to NEC for the problem.

7%: Rework/Save 5%:

Rework/ No Save

In contrast, only 4 of the 13 defect types received a “good” capture rating using manual inspection. Five received a “fair” rating, two received a “poor,” and two received an “unknown.”

The heart of the yield benefits for the 2401 over manual inspection is given in Figure 4. Of the lots that were chosen at random for inspection, 12 percent were sent for rework. Five percent of the lots were flagged by both manual inspection and the 2401. These lots fell into the “rework/no save” category. However, another 7 percent of

2401 Capability Good Good Good Good Good Good Good Good Good Fair Fair Good n/a

88%: No Rework Figure 4. While 12 percent of randomly inspected wafers were reworked, only 5 percent were detected by visual inspection. The 2401 detected these wafers but also detected a further 7 percent that could be reworked successfully.

Summer 2000

Yield Management Solutions

33

S

P

E

C

I

A

L

F

O

C

U

S

Figure 5. Four focus-offset fields were created per wafer, and demonstrated that the 2401 could detect a process window of 0.7 µm, making it suitable for monitoring the stepper for focus-offset excursions.

Of second highest importance — on 21 percent of the lots — were hot spots. A particularly challenging layer for manual inspection was a high-aspect ratio contact layer called “hole.” NEC found it impossible to see any hot spots or other focus-related defects at this layer using manual inspection. It was proven that the 2401 was able to capture these defect types at “hole”.

The third most important defect type was acceleration errors. For one of the poly layers, ten lots were reported to have acceleration errors. Four of them were found by manual inspection, while nine out of the ten were found by the 2401.

Two other defect types of note included no coat/exposure/develop defects and CVD stripe defects. The no coat/exposure/develop defects were created intentionally to test the 2401, because NEC did not see any natural examples during the evaluation though this defect type was known to occur occasionally. The CVD stripe defect was found on several lots that had been put on hold by the operators and had been categorized as lifting resist. NEC found that adjusting the recipe on the 2401 enabled them to either flag the defect or screen it out while still capturing photo related defects.

Stepper monitoring

The second part of the 2401 evaluation investigated applying the automated system for stepper monitoring.

34

Summer 2000

Yield Management Solutions

The goal was to set up a quick, sensitive process for looking at focus-exposure matrices, focus problems and leveling problems. A diffraction grating reticle was created with 0.3 µm lines and gaps, and then printed on unpatterned, resist-coated wafers using a KrF, deep UV stepper. This diffraction grating was used to reduce the process window of the photo process and bring it close to the process window of the stepper itself.

A focus-exposure matrix wafer was created (Exposure: centre 31mJ/cm2, step 2mJ/cm2 Focus: centre 0.0 µm, step 0.1 µm). The focus-exposure matrix produces a histogram that indicates the optimum focus and optimum exposure for the process. Changes in the focus or exposure conditions would produce a change in this histogram. Refinement of the field size used and focus and exposure steps should produce an effective and sensitive check for the stepper.

For the focus offset check, wafers were created with four offset fields, and each field had increasing positive and negative focus offsets (Figure 5). The wafers were then inspected and the focus process window estimated. The 2401 was able to detect a 0.4 µm positive offset and a 0.3 µm negative offset. This equates to a detectable process window of 0.7 µm. KrF steppers typically have inherent process windows of 0.6 to 1.0 µm. This would indicate that the 2401 can be used to detect any focusoffset excursions outside the stepper’s optimum process window.

S

P

E

C

I

A

L

F

O

C

U

S

Figure 6. Four tilt-offset fields were created per wafer, and demonstrated that the 2401 could detect a process window of 20 - 35 µrads, depending on the direction of the grating. This sensitivity suggests that the 2401 would be suitable for monitoring the stepper for tilt excursions.

The investigation of leveling offsets was similar. Wafers were created with four offset fields, this time with increasing tilts on both the “X” and “Y” axes (Figure 6). Again the offsets showed up clearly using the 2401.

In the “X” axis, the 2401 detected tilt offsets of 20 µrad and greater, while in the “Y” the 2401 detected offsets of 35 µrad and greater. By calculating the effective focus offset at the edge of the titled fields the detectable process window is in the order of ±0.35 µm offset at the edge of a 22 mm field. This is comparable to the focus offset detectable process window and again suggests that the 2401 can be used to detect tilt excursions outside of the stepper’s own process window.

Return on investment

At the conclusion of the evaluation, the return on investment was calculated by comparing manual versus automated after-develop macro inspection. The calculations were based on data from the eight layers evaluated, which were designed to represent the whole process. It should be noted that the product studied was a stable main runner. The yield kill rate of each defect type was considered using historical rework data and compared with the rework rate that resulted from using the 2401. The model did not include any of the savings that would be gained through using fewer operators or by taking into account the shorter time to detection of defect incidents. Furthermore, the opportunities for

savings are expected to be greater on shrinking technologies having higher wafer and die costs. Even using these conservative assumptions and a low average selling price product, potential savings of over $66,000 per month were calculated from using the 2401.

Summary

The KLA-Tencor 2401 was installed in less than 10 days. Twelve operators and three engineers were trained on the system and provided positive feedback about its ease of use and production integration. The 2401 proved to be 10 times more sensitive than manual inspection, with 12 out of 13 critical defect types captured reliably.

The thirteenth type is expected to be captured as soon as the next software version is installed. This system demonstrated potential for a very simple focus-exposure matrix utility and promising capability for monitoring steppers for focus and tilt excursions. The return on investment is quite aggressive even for a low average selling price product. Finally, NEC was able to reduce scrap and reduce excursion detection time, which translates to better yield and profitability. circle RS#034

Summer 2000

Yield Management Solutions

35

A WHOLE NEW WORLD

i Support

W O R L D W I D E S U P P O R T O P E R AT I O N S w w w. k l a - t e n c o r. c o m

IN CUSTOMER SUPPORT

circle RS#033

S

E

C

T

I

O

N

S

Q&A iSupport™ — the Most Advanced, On-line Customer Support Program An Interview with Beth McAllister, Senior Director of Marketing, Worldwide Support Operations.

What is iSupport and why is it important to our semiconductor industry customers?

Q

start-up issues, reducing steep learning curves and providing hands-on assistance for new users.

A iSupport is a first-of-its-kind support

Q How does iSupport Work?

A The most recent KLA-Tencor tools

offering providing a comprehensive, fast, secure and cost effective on-line support solution for KLA-Tencor tools.

With iSupport, most assistance that doesn’t require parts replacement can be quickly and completely resolved online. This is accomplished by installing a diagnostic server (iDM) to monitor our tools in the customer’s fab. The diagnostic server is connected to KLATencor’s secure On-line Support Center where authorized support personnel provide immediate help at the first sign of an equipment problem. The iSupport Program extends the availability of KLATencor’s current on-site support team with secure on-line support.

The ability to provide rapid on-line assistance to our customers, to correct equipment problems faster and more efficiently, and to provide real-time equipment performance and process data results in higher tool productivity, improving Cost of Ownership and asset utilization. In addition, iSupport accelerates the ramp for new tools and new fabs by expediting resolution of

are specifically designed for iSupport.

The KLA-Tencor diagnostic server is installed in the customer’s fab and connected to KLA-Tencor tools through the fab network. The iDM provides continuous monitoring of connected tools for automated fault detection and alert, data storage and analysis for reporting and trending, and secure and safe access to our On-Line Support Center (OSC). The security features built into iSupport ensure every possible safeguard has been taken; and the customer is in complete control of the secure information at all times. At the first notification of an equipment problem or at the customer’s request for assistance directly from the tool, the OSC’s technical and applications engineers log onto their central server and the iDM to access the KLA-Tencor tool on the customer’s fab network. The OSC desktop mimics the tool keyboard and display monitors on the tool, enabling the OSC engineers to access log files, error messages, recipe paraSummer 2000

meters and sensor data, just as if they were actually in the fab. From there, the engineers can assess system performance, execute diagnostics and assist with recipe setups.

Q Why iSupport?

A The need for e-diagnostics capabil-

ity has recently become a focus of semiconductor manufacturers. KLATencor, however, realized almost two years ago that with technology becoming increasingly complex and more capital intensive, customers would need cost-effective, around-the-clock, expert support at every location to maximize the return on their investment.

After benchmarking several industries for best-in-class support, KLA-Tencor initiated iSupport and is now the first company to bring a fast, comprehensive, secure, on-line solution to the semiconductor industry. iSupport is much broader than e-diagnostics, providing continuous tool monitoring and reporting, as well as automated early detection of system problems at the customer site.

For more information, please visit our Internet site: www.kla-tencor.com

Yield Management Solutions

37

THE GOOD NEWS IS, 300 MM IS GOING TO CHANGE OUR WORLD. THAT’S ALSO THE BAD NEWS. You already know that 300 mm wafer technology is on the way. But you might not be ready for how big it’s really going to be. Or how many new challenges it’ll bring. Like uniformity control in deposition, CMP, litho and etch processes, for instance. And an increase in process-induced, center-to-edge defectivity ratios. So along with a knowledgeable and experienced partner, tomorrow’s fabs need tools and control systems that are integrated, automated and optimized for 300 mm.

Which is where we come in. With the only complete 300 mm process module control solution available, combining defect reduction, process parametric control and yield management software. As well as applications and consulting expertise. It’s how we’re making sure your fab stays well ahead of the technology. And the competition. For more information on all of our 300 mm offerings, please visit www.kla-tencor.com/300mm, or call us at (800) 450-5308.

We’ll help put your future in a much better perspective.

ALREADY THERE. ©2000 KLA-Tencor Corporation

Lithography S

P

E

C

I

A

L

F

O

C

U

S

Collapse of the Deep-UV and 193 nm Lithographic Focus Window Yield Impact of Cross-Field and Cross-Wafer CD Spatial Uniformity Kevin Monahan, Pat Lord, Waiman Ng, Hubert Altendorfer, George Kren, and Scott Ashkenaz KLA-Tencor Corporation

© 1999 IEEE. Reprinted, with permission, from the Proceedings of the 1999 IEEE Symposium on Semiconductor Manufacturing; 1999; pgs 115-118.

The 0.13 µm semiconductor manufacturing generation, shipping as early as 2001, will have transistor gate structures as small as 100 nm, creating a demand for sub-10 nm gate linewidth control. Linewidth variation consists of cross-chip, cross-wafer, cross-lot, and run-to-run components. In this work, we explore spatial dependencies across the lithographic field due to reticle error and across the wafer due to wafer and chuck nanotopography. Both sources of spatial variation can cause collapse of the lithographic focus window near the limits of resolution, resulting in CD excursions for gate structures in high-performance microprocessors. Our work supports the contention that photolithography-induced defects may become the primary source of yield loss for the 0.13 µm generation and beyond.

As an extension of previous work on temporal variation1, we are currently exploring spatial dependencies across the lithographic field due to reticle and lens error and across the wafer due to wafer nanotopography and chuck flatness. The new study uses data from a comprehensive set of measurement technologies, including reticle and wafer CD SEM metrology, phase-shift focus metrology, cross-wafer interferometry, differential interference contrast metrology, and macro defect inspection. We have found that, as in the case of temporal variation, spatial variation can cause collapse of the common CD-defocus window near the limits of lithographic resolution, particularly for the gate and contact structures in high-performance devices.

There are many sources of spatial variation that contribute to process window collapse.

These include overlay error, reticle error, lens error, and focus errors. To predict yield, we treat each of them as defects with a specific “kill potential”. One example is the recent use of logistic regression to correlate overlay error with the probability of device failure2. In such a unified defect scenario, yield may be expressed as a product of survival probabilities given by N

Y=

∏(1 – λ )n

i

i

i=1

where lambda is the defect kill potential for defects of type i, n is the number of defects per die of type i, and N is the total number of defect types. In the case of parametric defects, the kill potentials may be functions of measured parameters such as overlay and critical dimension (CD) or unknown parameters, such as exposure variation and local defocus, which are observed indirectly in the form of CD excursions. Generally, we Summer 2000

Yield Management Solutions

39

S

P

E

C

I

A

L

F

O

C

U

S

200

350

180

300

% Dose

250

60 70 80 90 100 110 120 130 140 150

140 Gate CD (nm)

Raleigh Dof (nm)

160

200 150 100

120 100 80 60

50 40

0

248

193 157 Exposure Wavelength (nm)

EUV

20 0 -3

2

Figure 1. Collapse of the 0.5λ/(NA) Raleigh focus window as litho-

-2

-1

0 Defocus Units

1

2

3

graphic exposure wavelength is decreased. Values for the numerical apertures are assumed to be 0.7, 0.7, 0.7, and 0.25, respectively.

Figure 2. CD-defocus response surface (equation below) for isolated lines in negative resist (raw data not shown). Underexposure was used

The EUV wavelength is 13 nm.

to get 130 nm gate structures (90 percent exposure dose, E) at the expense of low focus latitude and high sensitivity to exposure variation

improve the accuracy of the lithographic yield model by identifying those defects with the highest kill potential, or even those that pose a quantifiable economic risk by affecting bin yield3.

Lithographic defocus is likely to be an indirect source of CD defects with high kill potential, particularly as exposure wavelengths decrease from 248 nm to 193 nm, 157 nm, and even 13 nm. This is primarily due to the reduction of the Raleigh focus window with shorter wavelength. CD and defocus are highly interactive, as shown in the example of Figure 2. Reticle CD errors or overlay errors that force reduction of the overall CD error budget will have a negative effect on the allowable range of defocus.

Results and discussion

A comprehensive “systems approach” was used to analyze complex spatial uniformity data from reticles and wafers. At least five state-of-the-art methodologies were applied to the problem:

collapse of the focus window as the CD tolerance is tightened by 50 percent.

1 2 y(E,D) = (b0 = b1D + b2D 2) + — (b3 + b4D + b5D ) E

•

Wafer surface nanotopography using differential interference contrast metrology

•

Cost-effective screening using darkfield and brightfield macro inspection technology

Our results show that the sources of CD error due to lithographic defocus can be de-confounded using this comprehensive approach. Reticle CD error, for example, can be stripped out using CD SEM measurements.

Confounded lens, wafer, and chuck components can be separated using a phase-shift focus monitor, combined with double-sided, wafer-scale interferometry and singlesided, differential interference contrast metrology.

Reticle and Wafer CD SEM Metrology

•

Lithographic reticle and optical characterization using reticle and wafer CD SEM metrology

•

Phase-shift focus measurement using optical overlay metrology and model-based analysis

•

Wafer thickness metrology using wafer-scale transmission interferometry

40

under conditions of defocus (D). The outer and inner boxes show the

Summer 2000

Yield Management Solutions

Focus errors create spatial CD non-uniformity. These can be due to the reticle, the projection optics, and the wafer/chuck surface upon which the pattern is printed.

CD SEMs can be used to map cross-field and cross-wafer errors, creating model-based CD uniformity maps and generating feedback to the stepper/track systems for correction of systematic spatial variation. Examples of cross-field CD error, measured using a specially adapted

S

P

E

C

I

A

L

F

O

C

U

S

Figure 3. Cross-field CD SEM data on a reticle, showing radial

Figure 4. Cross-field CD SEM data on a wafer showing apparent

dependence of the CD values in nanometers.

“tilt” in the DUV optics. Reticle CD error has been removed. Scale is in nanometers.

CD SEM, are shown in Figure 3 (reticle) and Figure 4 (wafer). In this case, the total CD variation on the wafer is due to reticle error, lens error, and nanotopography of the chucked wafer. Since the reticle and wafer CDs are measured in the same SEM, the reticle error is removed from the wafer data without heterogeneous tool matching.

Data from a phase-shift focus monitor characterizes focal plane deviations within the field and from field to field across the wafer. A monitor reticle with asymmetrically phase-shifted overlay targets is used in conjunc-

tion with a high-speed overlay tool to generate artificial registration errors that are a linear function of lithographic defocus. Fitting the data to a model enables the quantitative assessment of lens tilt, field curvature, astigmatism, scan errors, wafer/chuck flatness, lens heating, barometric effects, and other lithographic focus anomalies. The cross-field mapping capability of the phase-shift focus monitor is shown in Figure 5.

Figure 6 shows the same capability across a wafer. The total range is ±200 nm, including top surface nanotopography, wafer thickness variation, and chuck nonuniformity.

Figure 5. Cross-field response surface generated with data from a

Figure 6. Cross-wafer phase-shift focus data includes top surface

phase-shift focus monitor. The root-cause of CD error is often traced to

nanotopography, wafer thickness variation, and chuck non-uniformity.

cross-field defocus effects arising from wafer/chuck nanotopography.

Range is ±200 nm.

Registration-Based Phase-Shift Focus Metrology

Summer 2000

Yield Management Solutions

41

S

P

E

C

I

A

L

F

O

C

U

S

Figure 7. Cross-wafer interferometry isolates top surface nanotopography and thickness variation from chuck non-uniformity. Range is ±200 nm on 300 mm wafer.

Cross-Wafer Transmission Interferometry Cross-wafer interferometry can be used to separate thickness variation and surface nanotopography from chuck-induced deformation. In this case, monochromatic light is projected through the wafer and interference from the top and bottom surfaces of the wafer is used to determine thickness. Data for a 300 mm wafer polished on both sides is shown in Figure 7. The total range is ±200 nm. Measured in this way, the thickness data is confounded with top surface nanotopography.

In general, nanotopography with spatial periods below 5 mm (the slit-width of a scanner) and amplitudes in the hundred-nanometer range can create significant focusing errors in scanning lithography. A 193 nm scanner with 0.7-N.A. optics will have a theoretical depth-of-focus of about ±200 nm for dense lines, and less for isolated features.

Nanotopography at high spatial frequencies can exceed the dynamic range of a scanner’s in-situ focusing subsystems. If the focus errors are large, the resulting CD variations can create severe device yield and speed binning excursions, particularly in high-performance microprocessors.

Differential Interference-Contrast (DIC)Metrology Differential interference-contrast metrology uses the phase response of light reflected from the top surface of the wafer. Along with micro-tilt sensing, it can be used to separate top surface nanotopography from wafer thickness variation. In our case, the DIC metrology is 42

Spring 2000

Yield Management Solutions

Figure 8. Differential interference metrology isolates top surface nanotopography. Range is ±30 nm.

implemented on a high-speed, unpatterned-film inspection tool. A high-resolution profilometer is used for height calibration. As shown in Figure 8, DIC metrology responds to the higher spatial frequencies that could be missed by cross-wafer transmission interferometry. The total range of the top surface nanotopography is ±30 nm, much of which is due to “polishing chatter” arising from a process excursion that could have gone unnoticed without the DIC monitor. In some cases, we have observed top surface nanotopography with ranges below ±3 nm. This level of wafer surface quality is costly, but it may become critical for chemical-mechanical planarization (CMP) used in advanced shallow-trench isolation (STI) technologies.

Whole-Wafer Macro-Defect Inspection Gross defocus on patterned wafers is generally visible as a “hot spot” during macro-defect inspection. Hot spots can sometimes be seen in brightfield illumination, but they are much more visible in darkfield illumination due to scattering from pattern defects. Hot spots often result from extreme nanotopography caused by particles on the backside of a wafer, a problem that could become worse as the industry makes the transition to double-sided polishing on 300 mm wafers.

These gross focus excursions can be detected using high-speed, macro-defect inspection tools as monitors.

S

P

E

C

I

A

L

F

O

C

U

S

The wavelength reduction strategy for extending optical lithography will have the following consequences:

•

Reticle error will become a larger part of the CD error budget, forcing narrower lithographic process windows for focus and exposure.

•

Focus windows will dwindle as the CD error budgets shrink and theoretical depth-of-focus drops in proportion to exposure wavelength.

•

The need for monitors may increase as spatial CD variation and nanotopography effects detract from the focus window and impact yield.

•

The kill potential of both direct (CD) and indirect (defocus) parametric defects will need to be quantified more accurately using robust statistical methods4.

Figure 9. Whole-wafer, darkfield macro inspection data showing

Acknowledgements

focus “hot spot” in the upper left quadrant.

We are in debt to Ken Schroeder, Robert Lee, Jan Waluk, and many others at KLA-Tencor for their encouragement and contributions to this work.

Since backside particles produce pattern defects over relatively large areas, the 50-micrometer sensitivity of a macro inspector is more than sufficient to detect this form of wafer contamination. A typical darkfield image of a hot spot is shown in Figure 9.

Summary

Wavelength reductions and increases in numerical aperture have extended the life of optical lithography, but the improvements in resolution come at the cost of reduced depth-of-focus, as shown by the Raleigh equation below:

λ NA2 where λ is the exposure wavelength and NA is the numerical aperture of the optics.

DOF = 0.5

References 1. K. M. Monahan and P. Lord, “Lithographic focus stabilization for model-based gate CD control systems”, Proc.

ISSM, Tokyo, October 7-9, 1998, pp. 347-350.

2. M. E. Preil, J. McCormak, “A new approach to correlating overlay and yield”, Proc. SPIE, Vol. 3677, 1999.

3. K. M. Monahan, P. Lord, C. Hayzelden, and W. Ng, “An application of model-based, lithographic process control for cost-effective IC manufacturing at 0.13 micron and beyond”, Proc. SPIE, Vol. 3677, p. 435 (1999).

4. R. Martin, X. Chen, and I. Goldberger, “Measuring fab overlay programs”, Proc. SPIE, Vol. 3677, p. 64 (1999).

Summer 2000

Yield Management Solutions

43

Lithography S

P

E

C

I

A

L

F

O

C

U

S

Enhancing Overlay Metrology Productivity and Stability Using an Off-line Recipe Database Manager

by Stephen J. DeMoora, Stephanie Hilbun, George P. Beck III, Kristi L. Bushmana, Russell D. Fields, Texas Instruments Incorporated Robert M. Peters, Todd E. Calvert, KLA-Tencor Corporation

Tool cost of ownership and manufacturing productivity continue to be key factors in equipment selection discussions. Products that differentiate themselves by maximizing tool utilization and minimizing engineering resources make the best economic impact in a time of increasing fab capital costs. This paper will demonstrate the use of a single off-line recipe database manager (RDM) in conjunction with multiple optical misregistration measurement tools for the purpose of misregistration recipe creation and management in a high volume ASIC manufacturing line.

The manufacturing environment that exists in todayâ&#x20AC;&#x2122;s high volume ASIC production fabs presents multiple logistic challenges to the photolithography sector. In such fabs, it is common to have hundreds of independent devices running concurrently. This, in turn, corresponds to having thousands or even tens of thousands of reticles active at any one time. Typically, each individual reticle will require independent recipes for stepper exposure, and the subsequent misregistration and critical dimension metrology steps. In such an environment, recipe creation and management become very large and critical tasks.

In order to maximize tool utilization and minimize cycle time impact, recipe setup time must be minimal. Furthermore, in order to ensure the robustness and stability of a large number of recipes, the number of personnel involved in recipe creation and maintenance should be minimized. To meet these requirements, the recipe management system must be fast, simple to use, and capable of easy replica44

Summer 2000

Yield Management Solutions

tion and/or distribution of recipes to multiple process tools within the fab. In an ideal case, the system should be capable of creating recipes off-line from the production tool without requiring a wafer, and be able to distribute recipes to process tools via network connections.

Historically, metrology tools have not been capable of meeting this ideal case, mainly due to restrictions placed on metrology equipment vendors by their customers. With limited real estate available in scribe lines, chip manufacturers have pushed metrology vendors to design flexible pattern recognition systems that do not require a specific alignment target to be placed in the scribe. As a result, most metrology systems on the market today require that recipe setup be performed on the tool using a production wafer in order to acquire the necessary pattern recognition and measurement site templates with the proper illumination and other setup conditions.

The limitations described above can be overcome to a large degree by using a system that allows for storage of â&#x20AC;&#x153;masterâ&#x20AC;? templates for pattern recognition and measurement site setup. Furthermore, by using some forethought, a standard pattern recognition structure can be designed for use by multiple types of metrology

S

systems (overlay, CD SEM, film thickness, etc.), while minimizing the scribe line space used. By using standard structures, and taking advantage of process similarities across multiple devices, a system can be developed that allows for nearly 100 percent off-line, waferless recipe creation. The strategy for using such a system to handle recipe creation and management for overlay metrology systems, along with the associated productivity and recipe stability improvements will be discussed for the remainder of this paper.

P

E

C

I

A

L

F

O

C

U

S

Parameters

Wafer Map

Run time options Wafer selection Data output options

Wafer orientation Grid layout and offset Step pitch

Alignment

Tests

Pattern recognition image Pattern recognition location*

Misregistration target image Measurement options Measurement locations*

*Denotes a parameter that is associated with the element, but is physically linked to the recipe, not the element.

Recipe and element management strategy

For the work presented in this paper, a KLA-Tencor Recipe Database Manager (RDM) was used in conjunction with multiple KLA-Tencor overlay metrology systems installed in Texas Instruments’ DMOS 5 production facility. The RDM consists of a server with a database for storing recipes and recipe elements with clients which allow for the creation, editing, and distribution of recipes. The server is linked to each of the overlay systems via network connection to allow for easy recipe distribution. The RDM database employs a library structure that allows for recipe elements to be easily manipulated and also allows multiple recipes to share the same element. Inside the RDM database, the standard recipes are broken down into a series of four separate recipe elements. (Table 1.)

The first goal is to develop a strategy that minimizes the total number of elements required to support all recipe creation for the fab. Figure 1a describes an ASIC fab scenario with two distinct product families. The product families are differentiated by unique manufacturing process flows. Within a single product family, there are several different devices that run on the same

Process Flow X Device X1

Device X2

Process Flow Y

Device X3

Device Y1

Device Y2

Level 1x Level 1x

Level 1x

Level 1y

Level 1y

Level 1y

Level 2x Level 2x

Level 2x

Level 2y

Level 2y

Level 2y

Level 3x Level 3x

Level 3x

Level 3y

Level 3y

Level 3y

• • •

• • •

• • •

• • •

•••

• • •

Level Nx Level Nx ••• Level Nx

• • •

Level Ny

•••

Device Y3

Level Ny ••• Level Ny

Table 1: RDM recipe element structure and content.

process flow. Outside of using a different reticle set and the associated wafermap layout, each device will see the exact same process steps, and thus should appear optically identical.

By standardizing pattern recognition and miss-registration targets, one can take advantage of the similarities within the process flow. As Figure 1b illustrates, at a specific process level, the same single alignment and single test element can be used in the recipe for every device under the same process flow. All that needs to be changed is the vector location of the pattern recognition target and each misregistration target with respect to the center of the field.

Figure 1b also illustrates that for a single device, the same wafermap element can be used at each process level within that device. RDM parameters generally contain information that is global to the manufacturing facility, such as wafer size, notch orientation, etc. Thus only a handful of specific parameter elements (typically less than 5, possibly as few as 1) are necessary to cover all recipes running within the fab.

The test case outlined in Figure 2 demonstrates the effectiveness of the above strategy. For the test case specified (three process flows, each with 20 layers, and each having 100 devices running under the flow), 6000 recipes are necessary. However, these 6000 recipes can all be created using as few as 421 distinct elements.

Productivity improvement

Minimizing the number of recipe elements using the strategy defined in the previous section results in significant productivity improvements for the fab. When

Figure 1a. ASIC fab example of multiple product families.

Summer 2000

Yield Management Solutions

45

S

P

E

C

I

A

F

L

O

C

U

S

Process Flow X Device X1

Device X2

•••

Process Flow Y

Device X3

Device Y1

Device Y2

•••

Device Y3

Align_FlwX_Lev_1 Test_FlwX_Lev_1

Level 1x Level 1x

Level 1x

Level 1y

Level 1y

Level 1y

Align_FlwY_Lev_1 Test_FlwY_Lev_1

Align_FlwX_Lev_2 Test_FlwX_Lev_2

Level 2x Level 2x

Level 2x

Level 2y

Level 2y

Level 2y

Align_FlwY_Lev_2 Test_FlwY_Lev_2

Align_FlwX_Lev_3 Test_FlwX_Lev_3

Level 3x Level 3x

Level 3x

Level 3y

Level 3y

Level 3y

Align_FlwY_Lev_3 Test_FlwY_Lev_3

• • •

• • •

• • •

• • •

• • •

Align_FlwX_Lev_N Test_FlwX_Lev_N

• • •

• • •

• • •

Level Nx Level Nx • • • Level Nx

Level Ny Level Ny • • • Level Ny

Map_Dev _X1 Map_Dev _X2

Map_Dev _Y1 Map_Dev _Y2

Map_Dev _X1

Align_FlwY_Lev_N Test_FlwY_Lev_N

Map_Dev _Y1

Figure 1b. Strategy for selecting common recipe elements for different process flows and devices.

Process Flow X

Process Flow Y

Process Flow Z

Tab Total

# Device # Layers

100 20

100 20

100 20

300 60

# Recipes

(100)(20)=2000

(100)(20)=2000

(100)(20)=2000

6000

1* 100 20 20

1* 100 20 20

1* 100 20 20

1 300 60 60

141*

141*

141*

421

# Parameter Elements # Wafermap Elements # Alignment Elements # Test Elements Total # Elements

Second, since waferless recipe creation is now possible, a significant amount of tool time previously used for setup is now made available for production use. Figure 3 shows

Figure 2. Element selection strategy vs. number of recipes.

46

Summer 2000

Yield Management Solutions

RDM Phase-In Avg. Eng. Hours per System Avg. Eng. Utilization (4 Systems) Eng. Util. due to non-recipe setup items

60.00 50.00

9.00% 8.00% 7.00% 6.00%

40.00

5.00% 30.00

4.00%

20.00

3.00% 2.00%

10.00 0.00

*The same parameter element may be used for the entire fab

10.00%

70.00

1.00% 0.00% Apr99

May99

Jun99

Jul99

Aug99

Figure 3. Average engineering utilization.

Sep99

Oct99

% Eng. Utilization

The productivity benefits from this process are realized on three separate fronts. First, using the database library of elements, recipe creation time is significantly reduced. Waferless recipes in RDM can be created in

approximately five minutes as opposed to approximately 30 minutes when written on the tool. This time savings, along with the relatively small number of elements that need to be maintained, allows for reduction in the number of personnel required to handle recipe creation and maintenance. For example, implementing RDM has allowed DMOS 5 to reduce the number of people responsible for new recipe creation and maintenance from less than 10 down to 1.

Hours

a new process flow is introduced into the fab, the recipes for the initial device will need to be written on the tool itself with a wafer present, as alignment and test elements will not yet exist in the database.

However, as these initial recipes are created, they are imported into the database. Once in the database, the alignment and test elements can then be used as the “master” elements to create recipes for each successive device running under the same process flow. All successive recipes in the process flow can thus be written off-line and waferless.

S

The third productivity benefit is tied to manufacturing cycle time. If waferless setup is used for a new device, recipes can be created and distributed to the tools in the fab in advance of lots being released into the line.

As a result, lots sitting in queue waiting for overlay recipes to be written do not add cycle time. While no hard data has been obtained to quantify the exact effect of using RDM on cycle time, the following estimates can be made. To write a recipe on the tool takes approximately 30 minutes. Furthermore, most often the tool is not available, nor is there a person readily available to write the recipe at the exact time when the lot arrives at the overlay process step. A conservative estimate would add another 30 minutes of queue time per level. If a typical high-end device requires overlay measurement at approximately 20 layers, this adds at least 20 hours to the cycle time for that lot. In the case of the prototype lot for a new device, cycle time is critical for verifying design functionality. Therefore, a oneday cycle time improvement provides significant return on investment to the fab.

E

C

I

A

L

F

O

C

U

S

Theoretically, if a single test element is used at the same process level for multiple devices under the same process flow, then on a specific overlay tool, the TIS values for that process level should be the same for each device using that element. Some preliminary data has been taken to verify this hypothesis. Recipes for two devices running on the same process flow were set-up via RDM using the same “master” test element. These recipes were also set up to measure and record the TIS value on every production lot run with that recipe. The recipes were released to standard production on all KLA-Tencor overlay tools in DMOS 5 and allowed to run and collect TIS data for one month. Figures 4a, 4b and 5a, 5b summarize some of the results from this experiment.

Figures 4a and 4b show the TIS values for X and Y measurement orientations for a contact process level for both devices across four overlay systems at DMOS 5.

The values represent the mean of the TIS values from all production lots run through each tool during the 10 9

Absolute Value Mean TIS (nm)

the engineering utilization as tracked by on-board automation log files for four KLA-Tencor overlay systems used in Texas Instrument’s DMOS 5 wafer fab.

Prior to April 1999, DMOS 5 was performing all recipe setup directly on the overlay systems. Over MayJune 1999, RDM was implemented, employing the element strategy as defined in Section 2. By October 1999, the average engineering utilization on the 4 tools dropped to 2.35 percent from the initial April value of 8.86 percent. Based on a 720-hour month, these percentages correspond to picking up almost 47 hours of production availability per overlay machine per month as a result of implementing RDM.

P

Device A

8

Device B

7 6 5 4 3 2 1 0 Tool 1

Tool 2

Tool 3

Tool 4

Figure 4a. X-TIS values for contact level across four overlay.

Tool induced shift (TIS) stability 10 9

Absolute Value Mean TIS (nm)

Along with the productivity improvements seen with RDM, recipe stability improvements should be seen as well. By using a “master” element strategy, person-person and tool-tool variation in the alignment and misregistration test setups can be minimized, if not completely eliminated. One of the areas in which stability and consistency can be improved is tool induced shift, or TIS1. TIS tends to be sensitive to the illumination and focus conditions present on the tool during misregistration measurement setup2. Therefore, if multiple tools and/or people are involved in recipe setup, it is extremely difficult to maintain consistent TIS results for the same process level across multiple devices.

Device A

8

Device B

7 6 5 4 3 2 1 0 Tool 1

Tool 2

Tool 3

Tool 4

Figure 4b. Y-TIS values for contact level across four overlay tools.

Summer 2000

Yield Management Solutions

47

S

P

E

C

I

A

F

L

O

C

U

S

10

Summary

Absolute Value Mean TIS (nm)

9 Device A

8

Device B

7 6 5 4 3 2 1 0 Contact

Metal A

Metal B

Implant A

Implant B

Implant C

Process Level Figure 5a. X-TIS value for six different process levels on one tool.

10

Absolute Value Mean TIS (nm)

9 Device A

8

Device B

7 6 5

To summarize, a KLA-Tencor Recipe Database Manager (RDM) system was used in conjunction with multiple KLA-Tencor overlay metrology systems to significantly improve manufacturing productivity and recipe stability in Texas Instruments’ DMOS 5 wafer fab facility. The strategy employed to minimize the number of recipe elements required to create and maintain all recipes in the fab was discussed. Through the implementation of this strategy, a 6.5 percent improvement in tool availability, corresponding to almost 47 hours per tool per month was realized in DMOS 5 over a time frame of six months. Associated improvements in material cycle time were also discussed. Data was also presented to verify that using the RDM system produced recipes with highly consistent tool induced shift (TIS) results, typically within 1 nm between recipes using the same overlay test element. Future work will include a more in depth analysis of TIS stability, as well as investigating further productivity improvements that may be attained by fully automating the recipe creation process by utilizing CAD output data and factory automation.

4 3

Acknowledgements

2 1 0 Contact

Metal A

Metal B

Implant A

Implant B

Implant C

Process Level Figure 5b. Y-TIS value for six different process levels on one tool.

one-month test period. On all four tools, the TIS values for Device A and Device B match within 2.5 nm, and in all but one case, match to less than 1 nm.

Figures 5a and 5b summarize the TIS values for X and Y measurement orientations for a combination of six process levels for both devices on a single overlay system in DMOS 5. Again, the values represent the mean of the TIS values from all production lots run through each tool during the one-month test period.

For this case, at all process levels, the TIS values for Device A and Device B match within 3 nm, and in all but one case, match to less than 1 nm.

The authors would like to acknowledge Mark Smith and Tim Zommermaand of KLA-Tencor, and Russ Funk of RFSolutions for their assistance in collecting and analyzing the automation logs from the overlay metrology systems.

The authors would like to acknowledge the management at Texas Instruments’ DMOS 4 and DMOS 5 production facilities and at KLA-Tencor for their support of the work presented in this paper.

References 1. Daniel J. Coleman, Patricia J. Larson, Alexander D. Lopata, William A. Muth, and Alexander Starikov, “On the Accuracy of Overlay Measurements: Tool and Mark Asymmetry Effects,” SPIE Vol. 1261, pp. 139-161, 1990 2. Moshe E. Preil, Bert Plambeck, Yoram Uziel, Hao Zhao, and Matthew W. Melvin, “Improving The Accuracy of Overlay Measurements through Reduction in Tool and Wafer Induced Shifts,” SPIE Vol. 3050, pp. 123-134, 1998 Reprinted with permission from SPIE. Presented at SPIE ‘00 Microlithography.

Vol. 3998-115.

circle RS#021

48

Summer 2000

Yield Management Solutions

WE’RE READY FOR THE FUTURE OF COPPER/LOW-κ INTERCONNECT. WHATEVER IT MAY HOLD. Nobody’s certain what the right low-κ dielectric for copper interconnect at .13µm and beyond is going to be. But one thing’s for sure: the integration challenges will be formidable.

And they’ll range from optimizing barrier and etch stop layers to having the mechanical strength to withstand CMP. That’s why we’re developing the new applications you’ll need to control low-κ technologies, and integrating them into our advanced defect, parametric and analysis systems. All so that you’ll be able to evaluate yield at virtually every step. It isn’t easy. But it’s proof once again that we’re the right choice to help speed your fab’s transition to the new world. For more information, call 1-800-450-5308, or visit www.kla-tencor.com/lowk. You’ll see that we’re ready for the future. No matter what it holds.

ALREADY THERE. ©2000 KLA-Tencor Corporation

Lithography S

P

E

C

I

A

L

F

O

C

U

S

Matching Automated CD SEMs in Multiple Manufacturing Environments

by John Allgair and Dustin Ruehle, Motorola, John Miller and Richard Elliott, KLA-Tencor Corporation

As critical dimension (CD) design rules for semiconductor manufacturing become increasingly stringent, manufacturers of automated CD SEMs are developing systems with improved linewidth measurement repeatability and reproducibility 1. The ultimate technical performance of CD SEMs, however, is very much dependent on consistent and tight operational controls.

This is especially true in multiple tool manufacturing environments where system matching is required to preserve proper operation.

The matching and repeatability of CD SEMs can be evaluated using a standard daily monitor wafer that tracks the major system components that impact performance.

By using a method of statistical analysis on the data, matching can be verified immediately. This control procedure tracks tool stability, provides a common CD SEM length reference, and enables the seamless use of multiple CD SEMs within a single manufacturing environment or between separate manufacturing environments, without significantly increasing tool qualification time.

Shrinking linewidths and manufacturing challenges

The latest production devices have critical dimensions well below 0.25 Âľm, and future generations are targeted to have transistor gate structures at or below 100 nm. The value of tight dimensional control at the gate level is well understood, with the dollar value estimated to be as much as $7.50 in average selling price (ASP) per nanometer of difference in gate CD2.

An automated CD SEM can demonstrate sufficient repeatability for effective process control of these leading edge technologies3.

50

Spring 2000 Yield Management Solutions

Equally important to process control is tracking basic tool performance once it is integrated into a production line, which ensures that the expected precision is in fact realized from the metrology tool on a daily basis4.

Even when the performance of an individual tool is verified, it is also necessary to ensure that multiple metrology tools in the production line will deliver the same results.

Matching multiple CD SEMs in one or more manufacturing locations becomes even more important in large manufacturing facilities. Many fabs have numerous CD SEMs that are operated by separate groups within the facility, and production lots can be directed to various areas with available SEM capacity. Additionally, process development facilities must transfer new devices and processes to production environments, which requires the measurement of established devices on different CD SEMs. In both cases, there is a strong requirement for all CD SEMs to consistently match to within a predetermined specification.

Method: Setting up the match study

Once basic tool performance has been established in the manufacturing facility, effective matching programs must be relatively simple and not require specific personnel. Realistic verification techniques require minimizing time and effort, whether on start up, integrating new production layers, technology families or new CD

S

SEMs; or when re-qualifying systems after significant maintenance activity. Fortunately, a short daily qualification procedure that monitors CD stability on a single wafer is sufficient to ensure matching across all tools.

First, it is necessary to verify that each individual system is operating to specification, and that the resolution of each SEM is within specification and the imaging of each system is comparable. Next, a common set of wafers to which all of the SEMs can be calibrated is needed.

In the following study, the standards were based on the pitch of a nested line structure on a series of etched poly wafers. Using the average pitch of a series of sites from these wafers is a practical, easy-to-implement calibration option in the absence of a traceable length standard for SEMs. Wafer-to-wafer variation in the pitch structure used for calibration was measured to be less than 1 nm. Comparison of these standard wafers to an early version of a proposed NIST CD SEM pitch standard showed the absolute calibration to be off by less than 1 percent.

Using an etched wafer for calibration also has the advantage that closely matched wafer standards can be kept in close proximity to each SEM to simplify daily tool qualification and stability monitoring. The wafers can be easily transferred between fabs, serving as a portable length standard to further check CD matching between facilities. The wafers used in this study should have a useful lifetime of 40 months if care is taken to rotate measurement sites to avoid CD growth due to repeated measurements5. The six CD SEMs in this study were located in four physically distinct bays in two different manufacturing facilities. As a result, four separate calibration/tool qualification wafers were used for the calibration of the tools.

Measurements were taken on two KLA-Tencor 8100XP CD SEMs and four KLA-Tencor 8100 CD SEMs. To ensure operational consistency, all layers used in this study were measured with a single beam setting of 600eV landing energy, with a consistent beam current setting for each of the six tools.

P

E

C

I

A

F

L

O

C

U

S

The eight layers used in this study are specified in the following table: Type

CD(nm)

Feature Type

Etched Oxide

335

Dense Line

Resist on Nitride

325

Dense Line

Etched Nitride

380

Dense Line

Resist on Poly

<250

Dense Line

Etched Poly

<250

Dense Line

Resist on Metal

475

Dense Line

Etched Metal

475

Dense Line

Etched Oxide

280

Contact

All wafers were measured once on each tool, with the mean value calculated from nine sites measured on each wafer. In addition to these eight layers, a resist contact layer with nominal features of 330 nm in diameter was analyzed to evaluate contact hole imaging capabilities.

Performing the matching test

Previous matching analysis methods have compared measurements collected over an extended period of time. Typically one or two wafers are used. The wafers are measured on each system every day for a period of days, and the differences between wafer means for each day are compared to estimate system matching.6,7 The time and effort required to gather several days worth of measurements from each SEM using an extensive sampling plan is often prohibitive in a manufacturing environment. In addition, when evaluating matching between facilities, the technique becomes completely impractical.

A more practical strategy for estimating system matching is to apply past knowledge of within-system performance to the matching analysis. This can alleviate the need to run tests on multiple tools over multiple days.

The wafers used in the study were taken from a production device and represent a variety of layers, including resist and etched features. Matching performance was evaluated on eight layers including one of the calibration wafers.

Summer 2000

Yield Management Solutions

51

S

P

E

C

I

A

F

L

O

C

U

S

In order to test for a statistically significant difference between two populations of data at the level of the matching specification, we need estimates of the major sources of CD variation in the tools. The total measurement variation can be written as: σT2 = σM2 + σL2 + σD2

measuring the mean of the measurements on a particular wafer, the dynamic component of the variance of a wafer mean is reduced by a factor of 1/√N when N points are averaged to obtain a wafer mean. The subsequent estimate for the variance in the estimate of the wafer mean, µ, measured on a single system is: σµ2 = σD2/√N + σL2.

where, σM2 = the variation due to matching between systems σL2 = the variation within a single system over time (long-term component) σD2 = the variation within a single system between multiple measurements and wafer loading (dynamic precision) The combination of terms σM2 and σL2 correspond to “reproducibility” while dynamic precision (σD2) corresponds to “repeatability”8.

Within a single system, only the long-term and dynamic components are relevant. For this study, a standard tool acceptance test was used to quantify the dynamic precision of a single measurement on the system for each particular layer. To measure σD , a single job was run several times in succession with the wafer fully unloaded from the system between each run. When 1.96σ L

1.96σ L

SEM A

SEM B

α/2 = 0.025

95% confidence interval for ∆

With sufficient sampling per wafer (30 points per wafer for example), the contribution of the dynamic precision term becomes negligible and we can focus on the long-term variation as the major source of uncertainty in the wafer mean (Figure 1).

The uncertainty due to long term variation cannot, however, be reduced by increased sampling on a single run or by multiple runs in a short period of time.

Multiple measurements are required over an extended period of time. These measurements can be performed on the wafers to be matched or, alternatively, on a separate wafer used to track the CD stability of the tool.

The second approach has the advantage that the long term variation for each system can be monitored as part of the daily tool qualification. This is the approach adopted in this study.

Because many points are sampled on a wafer, the variation in the estimation of a particular wafer mean should be roughly equal to the long-term precision specification of a single system. For example, for the 8100XP system, the long term specification is 5 nm 3σ, or about 1.7 nm 1σ. Analysis of data obtained from the daily qualification of the SEMs verifies that the systems do, indeed, operate within this long term specification.

With this understanding of the variance in the mean for a single system, the most common test used for the comparison of two populations were examined, the student’s t-test9. For two systems, we wish to test the hypothesis that the measurements do not differ by more than the matching specification. (The null hypothesis is that the means do not differ by the predetermined amount.) For this example, we will use the matching specification for the 8100XP of 5 nm, mean to mean (∆M).

The test statistic for significant differences between wafer means measured on two different systems, ∆µ is thus: ∆µ > σL*t + ∆M

Figure 1. Typical distribution of CD measurements due to long-term system variation of two SEMs. The means of these two distributions can be considered significantly different when the overlap between the distributions is smaller than a predetermined value. The width of each distribution is determined by σL.

52

Summer 2000

Yield Management Solutions

or ∆µ > 1.7 * 1.96 + 5.0

S

P

E

C

I

A

F

L

O

C

U

S

370 365 360

30 20

355 350 345

10 340

0

1

2

3

4

5

6

7nm

335

Figure 2. Histogram of tool-to-tool wafer mean differences, all layers, all possible pairs. Differences are in nm. Total number of pairs for all 8 layers = 120. The number of differences for each layer is given by

nm 1

2

3

4

5

6

SEM #

N(N-1)/2 where N is the number of tools.

Figure 3. Average diameter by SEM for resist contact layer. Middle of

using the t-value appropriate for a 95 percent confidence interval10. Therefore differences in wafers means ∆µ that satisfy

diamond indicates wafer mean, points indicate individual measurements. A clear difference is evident between SEMs #4 and #5 (8100XP), and SEMs #1, 2, 3 and 6 (8100).

∆µ > 8.3 nm can be considered significantly different at the level of the 5 nm matching specification.

It is important to consider the application of this test value for the wafer means. Each individual pair of systems is evaluated at each layer to this maximum measured matching value. This ensures that no two systems differ with statistical significance by more than 5 nm.

Understanding the results

Figure 2 depicts the distribution of the pair-wise differences between the wafer means measured on six SEMs for all eight layers. The graph shows that all layers measured pass the specification of 5 nm with a significance limit of 8.3 nm. The largest difference between SEM#

3

6

2

5

4

1

3

0

1.5

1.9

2.8

3.7

3.9

0

0.4

1.3

2.2

2.4

0

0.9

1.8

2.0

0

0.9

1.1

0

0.2

6 2 5 4 1

0

Table 1. Pair wise SEM differences (nm) for resist on poly layer.

any pair of SEMs on any layer was less than 7 nm. The average difference was ( 3 nm for all layers individually (Table 1).

Figure 3 shows the results of measurements on a resist contact layer with nominal features of 330 nm in diameter. With this layer, a distinct difference between the two populations of SEM was identified. Within the subgroup of the four KLA-Tencor 8100 systems, the maximum delta between any two systems was 3.5 nm.

Between the two 8100XP systems, the delta was 1.1 nm. The difference between the two subgroups was 8 nm. This difference is attributable to the improved contact hole imaging of the 8100XP. To determine if the use of an etched wafer to establish CD SEM matching has an impact on the matching of resist features, we looked at the correlation between the average pitch value for the dense line structures measured on the two critical layers in this study and the average feature size for these wafers by tool. This was compared to the correlation between the average pitch value on a calibration wafer measured on the tools. In both cases, for the etched polysilicon wafer and the resist on polysilicon layer, excellent correlation (>90 percent) was found between the pitch value of the product wafer and the pitch value measured on the calibration wafer. This is a clear indication that differences in the wafer means for the two critical layers are not dominated by the choice of the calibration standard.

Summer 2000

Yield Management Solutions

53

S

P

E

C

I

A

L

F

O

C

U

S

Summary

References

It is possible to match multiple SEMs in more than one manufacturing environment using a straightforward, simple daily qualification procedure and a calibration standard based on the pitch of a nested line structure. Using a simple statistical method to test the matching between all pairs of tools allows matching compliance to be established with a minimum amount of time and effort. In addition, a wide variety of production layers can be measured on CD SEMs without the need to distinguish between the tools on which the measurements were made.

1. J. Allgair, et. al. “Towards a Unified Advanced CD SEM Specification for Sub-0.18 um Technology,” in Proceedings SPIE 3332, 1998, pp.138-149.

2. J. Sturtevant, et. al. “Implementation of a closed loop automatic CD and overlay controller for sub 0.25 micron patterning,” in Proceedings SPIE 3332, 1998.

3. K. Monahan, et. al. “Subnanometer-precision metrology for 100-nm gate linewidth control,” in Proceedings SPIE 3332, 1998, pp.110-123.

4. J. Allgair, et. al. “SPC Tracking and Run Monitoring of a CD SEM,” in Proceedings SPIE 3332, 1998, pp.243-251.

5. Ibid.

6. R.R. Bowley, et. al. “Matching analysis on seven manufacturing CD SEMs,” in Proceedings SPIE 3331, 1998, pp.94-99.

7. D. Erickson, et. al. “Statistical verification of multiple CD SEM matching,” in Proc. SPIE 3050, 1998, pp.93-100.

8. J. Allgair, et. al. “Towards a Unified Advanced CD SEM Specification for Sub-0.18 um Technology,” in Proceedings SPIE 3332, 1998, pp.138-149.

9. Box, Hunter & Hunter, “Statistics for Experimenters”, Wiley, 1978, p111.

10. Ibid., p630.

All of these results demonstrate that it is possible to ensure CD SEM system matching within a fab and between fabs by employing a simple daily method. The process control gained offers clear benefits to ensure the reliable, repeatable performance of automated CD SEMs in a production environment.

circle RS#009

Mark Your Calendar for. . .

KLA-Tencor’s 7th Annual Data Storage Technical Information Session and Reception Wednesday, September 20th, 2000 6:30 p.m. — 10:00 p.m.

San Jose Hilton and Towers

Limited seating available.

To reserve your space today, please contact Tavis Szeto at tavis.szeto@kla-tencor.com

Lithography S

P

E

C

I

A

L

F

O

C

U

S

Improving Process Control for 0.18 µm Technology and Beyond

by Bryan Choo, Trina Riley, Bernd Schulz, Bhanwar Singh, Advanced Micro Devices

Production fabs typically use critical dimension (CD) measurements as their primary means for process control in printing lines, spaces, and contacts in lithography and etch processes. However, as the industry moves to 0.18 µm manufacturing and beyond, CD measurements alone are not providing enough information about the printed structures. As the geometry shrinks, slight changes in the shape and profile1,2 can significantly affect the electrical characteristics of the circuit even while maintaining the same CD value. An improved method uses information already collected by a CD SEM to automatically compare the stored image and linescan information of a correctly processed structure to that of the structure being measured.

Lithography and etch depend on CD measurements to provide feedback on whether circuit structures have been printed correctly. Data collected from critical dimension scanning electron microscopes (CD SEMs) provide information about the width of lines and spaces and the diameter of contact holes. Besides the sizing of the structures, factors such as the slope of the line and the existence of notching or footing can significantly alter the performance of the chip, while remaining relatively undetected in the simple linewidth measurement.

CD SEM scans contain far more information than just the CD value3, and this information can be used to better characterize the circuit. A relatively straightforward scheme to utilize all of the data would be to compare the entire scan to previously captured data. This would provide a correlation score that shows how the measured structure compares to one measured previously. This correlation score can be used to better define process windows and catch process problems.

For instance, by using this data it is possible to distinguish between different profiles and determine if a process shift has occurred, even when the measured CD remains within specification. Without this information, the

process used may not be truly optimized, or a shift may occur that is not detected in a timely manner, resulting in the loss of yield and revenue.

In the following application, data was collected and implemented in production on an interconnect lithography process. Before the correlation information was available, it was very difficult to detect scumming within the LI trench, so it was a time consuming and labor intensive procedure to identify problem lots. The correlation scores, collected automatically and concurrently with the CD measurement, allowed tracking through the SPC chart and automatic flagging of problems while the lot was still in the photolithography module. The result was faster feedback control and thus less scrap material.

Setting up the automated method

The correlation score technique was implemented in the pattern quality confirmation (pQC) software of the KLA-Tencor 8100XP CD SEM. This software allows the automated CD metrology program to collect CD measurements and correlation values simultaneously.

The program uses the pattern recognition template to generate an image correlation score and the microalignment template to generate a linescan correlation score. An algorithm compares the stored image and linescan (considered to be the ‘golden’ structure or standard process) to the site being measured. The results are reported on screen and within the standard output file.

Summer 2000

Yield Management Solutions

55

S

P

E

C

I

A

L

F

O

C

U

S

130

130

120

120

110

110

100

100

90

90

80

80

70

70

60

60

50

50 0

512

1024

reference

1536

2048

score = 0.86

Figure 1a: Example of linescan correlation for a properly processed

0

512 reference

1024

1536

2048

score = 0.35

Figure 1b: Example of a linescan correlation for a poorly printed circuit.

circuit.

The scores show how closely the given site matches the reference. Figure 1 shows linescan comparisons taken for a set of dense lines and spaces. In Figure 1a, the circuit was printed correctly, resulting in a high correlation value of 0.86. The circuit in Figure 1b was misprocessed, leading to deviations from the reference linescan and a low score of 0.35.

The software allows the user to decouple the reference image and linescan from the automation software, thus enabling each to be optimized separately. The pQC software also allows focusing the linescan comparison on a particular area of interest, such as between dense lines for the detection of scumming.

can correlation contours are of particular interest. In the areas where the CD is obviously out of specification (less than 0.325 µm or larger than 0.425 µm), the linescan correlation drops precipitously to about 0.4 (Figure 4). In the area of the wafer where the CDs are within the specified window, the linescans are obviously higher (roughly 0.6-0.8), but also show additional detail on which process conditions provide the best ‘match’ to the ideal. The linescan contours, therefore, provide a wealth of useful information: they not only correlate well with the CD contours, but also exhibit increased sensitivity where the CD contours show little resolution.

The sample process

In this sample application, a focus-exposure matrix (FEM) was used to characterize a lithography process for a damascene Metal 1 layer. The stepper focus and exposure were centered to target a CD of 0.375 µm for dense spaces, and for the desired process to hit this target within a range of ±0.025 µm. An automated CD program was set up to measure the wafer, providing critical dimension, linescan correlation, and image correlation data.

The CD measurements indicated that only the extreme process parameters at the edges of the wafer were outside the desired 0.350-0.400 µm window. In contrast, both the linescan (Figure 2) and image correlation scores detect significant changes in the dense trench structure being measured, even within the area of the wafer where the CDs are relatively constant. The lines56

Spring 2000

Yield Management Solutions

Figure 2: Plot of linescan correlation contours.

S

80

80

70

70

60

60

50

50

40

40

30

30

20

20

0

E

C

I

A

L

F

O

C

U

S

for each box. Figure 3 shows an example of the aligned pQC and reference scans. This clarifies the information on the size and shape of the circuit structure. The CD measurement still provides the linewidth or contact hole diameter, while the correlation score is now focused only on the shape of the edges.

0 LCorr

P

RCorr

Figure 3: Scan segments covered by the left and right correlation boxes.

It must be noted that although a linescan score of 0.7 was set as the cutoff value for this process, each process layer should be characterized separately. Once this minimum correlation is determined, collecting these linescan values, in conjunction with the CD measurements, results in a better characterization of the process.

Advanced analysis

The new linescan correlation algorithm in the pQC software allows the placement of two independent boxes (which are also independent in size, similar to the measurement boxes for a CD site) in the region where the most changes in the signal can be expected.

This allows the comparison to focus on a particular area of interest. Whereas the algorithm in the older software versions would be affected by any change in the CD (even if the signals from the line edges were very similar), the new software searches for an edge inside the box and aligns the pQC scan to the same edge in the stored reference scan before it calculates the correlation score

Finally, for both the image and linescan algorithms, three different types of score parameters can now be calculated. In each particular application of the correlation scores, the most sensitive parameter should be determined in preliminary tests.

In our sample application, this advanced capability successfully detected scumming during the CD measurement step, without the need for any additional measurements on other tools or operator assistance. To conduct the study, the photolithography cells were monitored with photo track monitor wafers (PTM).

Since part of the PTM process flow is a CD measurement step, a pQC site was inserted into the CD measurement program to collect correlation scores. A FEM wafer was analyzed for best image quality and used to save the reference scan of the â&#x20AC;&#x2DC;goldenâ&#x20AC;&#x2122; structure.

Knowing that scumming normally starts in dense structures, the left correlation box was placed so that it captured only the left edge of a dense trench and the right box was stretched over the trench to include the right edge. When the program was run, the scores for both boxes (LCorr and RCorr respectively) were calculated without the need for an additional scan.

Figures 4 and 5 show the lot average charts of the correlation scores for the left and the right boxes. Both indicate numerous wafers with scumming problems,

110

110

95

95

90

90

85

85

80

80

75

75

70

70 1

4

7

10 13 16 19 22 25 28 31 34 37 40 Wafer

Figure 4. Lot average chart for left box corrlation.

1

4

7

10 13 16 19 22 25 28 31 34 37 40 Wafer

Figure 5. Lot chart for right box correction.

Summer 2000

Yield Management Solutions

57

S

P

E

C

I

A

L

F

O

C

U

S

correlation values were able to differentiate between structures with similar CDs and detect resist scumming. In fact, the additional information gained from the correlation data provided a better characterization of a photolithography process than the CD measurements alone, resulting in significant savings in time, cost, and materials.

Acknowledgements Figure 6. Good sample.

which were verified on images automatically captured during the measurement (Figures 6 and 7). The charts also show the final stabilization of the process after the problem was fixed.

By using the new pQC feature, it was possible to get a signal for scumming when the problem had just begun.

Interestingly, the defect count from the defect inspection did not raise a flag for scumming. So, without using this technique, the scumming might only have been found accidentally during a manual defect review. Thus, the correlation scores enabled the immediate detection of the scumming problem in the PTM, which might have otherwise gone unnoticed until production lots were affected. In the sample application, the cause of the problem was an erroneous PEB plate temperature setting.

The resolution of the problem was then confirmed in the correlation score data (Figures 4 and 5).

Broader applications

This technique can be applied to any linear measurement feature. For nonlinear features, such as contacts, the image based algorithm can be used. With the new software, the reference image is independent from the pattern recognition template, so optimal magnification of the region of interest can be obtained without any impact on automation robustness.

Correlation scores, which indicate the degree of matching between the measured circuit structure and a ‘golden’ or reference structure, provide valuable information about a process. They can, therefore, be utilized as an effective process control monitor, without the need for additional tools or process steps. Even in this sample application, a basic and preliminary embodiment, the 58

Spring 2000

The authors would like to express their appreciation for helpful discussions and support from Luis Ortiz and Joerg Thuemmel of KLA-Tencor. The authors would also like to thank Stu Brown, Chris Fischer and Renee Walker for their aid in running wafers and analyzing data in Fab 25.

Figure 7. Sample with severe scumming.

Yield Management Solutions

References 1. J. M. McIntosh, B. C. Kane, J. B. Bindell, C. B. Vartuli, “Approach to CD SEM metrology utilizing the full waveform signal,” Metrology, Inspection, and Process Control for Microlithography XII, Bhanwar Singh, Editor, Proceedings of SPIE Vol. 3332, pg. 51-60, SPIE, Bellingham, WA, 1998.

2. B. Banke, C. Archie, “Characteristics of accuracy for CD metrology,” Metrology, Inspection, and Process Control for Microlithography XIII, Bhanwar Singh, Editor, Proceedings of SPIE Vol. 3677, pg. 291-308, SPIE, Bellingham, WA, 1999.

3. D. C. Joy, “Ultra-low Energy Imaging for Metrology,” Metrology, Inspection, and Process Control for Microlithography XII, Bhanwar Singh, Editor, Proceedings of SPIE Vol. 3332, pg. 42-50, SPIE, Bellingham, WA, 1998.

4. D. G. J. Sutherland, A. Veldman, Z. A. Osborne, “Contract hole characterization by SEM waveform analysis,” Metrology, Inspection, and Process Control for Microlithography XIII, Bhanwar Singh, Editor, Proceedings of SPIE Vol. 3677, pg. 309-314, SPIE, Bellingham, WA, 1999.

5. E. Solecky, R. Cornell, “CD SEM Edge Width Applications and Analysis,” Metrology, Inspection, and Process Control for Microlithography XIII, Bhanwar Singh, Editor, Proceedings of SPIE Vol. 3677, pg. 315-323, SPIE, Bellingham, WA, 1999.

6. D. M. Goodstein, B. Choo, B. Singh, “Correlation Flagging of i-Line Lithographic Process Drift,” KLA-Tencor CD SEM Users Group Meeting, Santa Clara, CA, 1999. circle RS#009

Lithography S

P

E

C

I

A

L

F

O

C

U

S

Optimizing Yield By Detecting Lithography and Etch CD Process Excursions

by Richard C. Elliott, Raman K. Nurani, Sung Jin Lee, Luis Ortiz, Moshe Preil, KLA-Tencor Corporation, J. George Shanthikumar, University of California at Berkeley, Trina Riley, Greg Goodwin, Advanced Micro Devices

Effectively detecting lithography and etch critical dimension (CD) process excursions while minimizing added cost can have a significant impact on semiconductor production yield. Finding this balance requires effective application-specific planning in order to identify excursions and find the optimal measurement scheme. There are many different yield-limiting excursion signatures in photo and etch, and a given excursion signature at photo may turn into a different excursion signature at etch with a different impact on yield and performance. Many current sampling plans and monitoring schemes miss these excursions.

An improved procedure for effective detection of CD process excursions can have a significant impact on yield and revenue.

Feature dimension is a critical parameter for lithography and etch processes in semiconductor manufacturing. CD measurements are made for pass/fail purposes to ensure that the data for a particular lot are within the process tolerances. These tolerances are usually specified in terms of basic statistics such as the lot mean and range.

The data is also used to identify systematic trends in the process over time. If necessary, the lot CD measurements can be fed back manually or automatically to adjust the process. The measurement sampling required to precisely estimate the mean CD of the lot is a function of the baseline process variations. For example, in a process that has minimal wafer-to-wafer variation, the measurement of multiple wafers per production lot does not greatly improve the estimate of the lot mean CD. Determining baseline variations requires accurate estimation of different variance components such as lot-to-lot variation, wafer-to-wafer variation within a lot, fieldto-field variation within a wafer, and siteto-site variation within a field7. It is common practice to use a nested ANOVA model to compute these variations3,6.

60

Spring 2000

Yield Management Solutions

However, current ANOVA models do not provide accurate estimates of these variations when systematic variations are present in the data. A new Generalized ANOVA model is more effective than the conventional ANOVA model for characterizing the baseline process variations.

The full distribution of CD measurements can also be used to identify isolated process failures or â&#x20AC;&#x153;excursions.â&#x20AC;?

While process excursions that are isolated to within field or within wafer may not greatly affect the mean CD of an entire production lot, they can have a catastrophic impact on the performance or yield of the semiconductor devices. Identifying these excursions is critical to ensure timely correction of yield limiting lithography and etch process issues. This requires a precise estimation of the systematic and random components of the total variation (otherwise some of the random excursions can be masked under the total variation).

The guiding principle to the approach outlined in this article is to determine a sampling plan that effectively detects process excursions, while minimizing the metrology resources required to support the collection of this data. These resources include not only the capital cost of the CD measurement equipment, but also the engineering resources required to analyze and interpret the data, and the lost production time which occurs when metrology data erroneously indicates the occurrence

S

of a CD excursion. The optimal sampling plan provides not only the quantity of data needed to detect excursions, but also the quality of data needed to detect real excursions with a minimum of false alarms. The best sampling plans will also enable the user to effectively diagnose the types of excursions when they do occur, and to facilitate the best corrective action so that production can be maintained with a minimum of interruptions.

Analyzing the sources of variation and determining the primary excursion types and frequencies in the process are thus key building blocks of an effective sample planning methodology. While statistical analysis and cost modeling are an important part of sample planning, understanding the basic lithographic variations in the process is equally important in determining the optimal sampling plan.

There are three basic steps to determining an optimal process sampling plan: determining the baseline statistics of the CD process; identifying the different excursion types, as well as their magnitudes and frequencies; and the evaluation of alternate sampling strategies for detecting process excursions.

P

E

C

I

A

F

L

O

C

U

S

ponent being larger than the sum of the lower plus the higher order components. When this happens, fabs typically set the â&#x20AC;&#x153;negativeâ&#x20AC;? variance component equal to zero and make decisions accordingly. In this case, for example, this could lead to sampling fewer fields on the wafer and eventually missing the field-to-field baseline variation problems and excursions. In fact, true field-tofield variance obtained from the Generalized ANOVA model is indeed the most significant component of the total variation. Precise estimation of variation leads to better understanding of the process variations, and allows us more reliable capture of random excursions.

The conventional model is at risk to underestimate the total variance components (Table 1).

Generalized ANOVA Systemic Random Total Site-to-Site

6.25

2.25

Conventional ANOVA

8.50

8.50

Field-to-Field

1.21

5.29

6.50

Neg.Var.

Wafer-to-Wafer

0.08

0.49

0.57

0.42

Lot-to-Lot

1.44

2.25

3.69

3.69

Table 1: Baseline variance components (nm 2 ).

Baseline statistics

To evaluate the sampling plan, we collected production CD data for over 600 lots (X wafers per lot, Y fields from a wafer and 2Z sites from each field) from poly gate photolithography and etch steps of a 0.18 Âľm logic product. The CD data were collected using the KLA-Tencor 8100 CD SEM measurement tools at the end of poly after-develop and after-etch steps. We analyzed this data to characterize the baseline process and identify excursions. We also collected wafer level yield data in order to study if the identified wafer level excursions resulted in any yield impact.

Using the data, we computed the baseline distributions and excursion statistics, separating the systematic and random baseline components of variation. Table 1 depicts the results of our generalized ANOVA approach and those of the conventional nested ANOVA approach.

The nested ANOVA does not separate the systematic and random components of variation, which can cloud results.

For instance, some of the variance components from the conventional model will be reported as negative numbers.

This happens whenever there are systematic variations, which results in the lowest order nested variance com-

The sampling plan for excursion monitoring is primarily dependent on the random variance component. Without separation of the systematic and random components, sampling decisions will be made using the total variation, which can be much higher than the random component. In the example in Table 1, the total variance for the site-to-site component has the largest value, which might cause the user to allocate more metrology resources to measuring multiple sites. In fact, the random variance components show that field-to-field variation is larger, and thus between field measurements are more important for excursion monitoring. In this case, failure to separate the random and systematic components leads to a sampling plan that is not optimal.

CD excursion types

A lot is considered to have an excursion if its statistics are significantly different from the baseline with 95 percent confidence level. The Generalized ANOVA model identifies mean excursions as well as several types of variance excursions, such as site-to-site within field variance excursions, field-to-field within wafer variance excursions, and wafer-to-wafer within lot variance excursions.

Summer 2000

Yield Management Solutions

61

P

E

C

I

A

L

F

O

C

U

S

Most of the lot level mean excursions can be detected by monitoring the lot mean of photo and etch CD processes in an SPC chart. Detection of variance excursions requires separation as well as precise estimation of systematic and random variance components. Using our baseline analysis and excursion detection algorithms, we identified several types of excursions in the photo and etch CD data. Each excursion signature demonstrated how much the CD deviated from the baseline at some of the representative fields and sites on a wafer.

After identifying the excursion types, it is necessary to determine their frequency during photo and etch. The difference between photo and etch CD distributions is a function of the different etch biases for different types of features, as well as the different patterns of spatial variations in the etcher as opposed to the stepper and track processes.

In general, a photo CD variance excursion resulted in an etch CD variance excursion, even if the signature of the excursion changed from photo to etch. In fact, about 55 percent of the photo field-to-field variance excursions in our study became field-to-field variance excursions after etch. This usually occurs when there is no feed forward control from photo to etch. Moreover, after applying regular etch bias to a given excursion wafer, the photo CD excursion signature turns into a different CD excursion signature after etch. These observations indicate that it is very important to understand different types of excursions at photo as well as at etch in order to design an optimal feed forward/feedback model for CD control. It is also important to sample enough fields and sites within a field to detect these excursion signatures and to comprehend the correlation between photo and etch excursion signatures.

The true purpose of measurement is to identify problems and facilitate their rapid correction. Classifying excursions into types can dramatically reduce the engineering time and resources required to isolate the root cause of a problem and initiate appropriate corrective action. Understanding the patterns of excursions can also help drive process improvements and enable setting tighter tolerances to improve the performance and value of the finished parts.

After correlating the wafer level excursion to yield, we observed that the field-to-field (or across wafer) variance excursions had significant impact on yield. In fact, 70 percent of the time, these excursions resulted in low 62

Spring 2000

Yield Management Solutions

Above Average Yield

Yield Factor

S

Low Yield

1

2

3

4

5

6

7

8

9

10

11

12

13

Wafers with field-to-field variance excursion Figure 1. Examples of yield impact of field-to-field variance excursions on wafer yield. The yield factor illustrates whether the yield for the wafer was above or below average (horizontal black line). There is no significance to the sequence of the wafers; they were arranged from lowest to highest yield simply for visualization purposes.

yield. Figure 1 shows the normalized wafer level yield of thirteen wafers that were subjected to field-to-field variance excursion at photo and etch. (The correlation of within field excursions to yield requires analysis of more detailed die level yield and performance data, and this study is currently ongoing.)

Sampling plans

Various sampling strategies are available to detect process excursions. Finding the optimal plan requires finding the best balance between missing excursions and triggering false alarms; in other words maximizing yield while minimizing cost.

The key question is what is the optimal sampling plan for detecting excursions. This is evaluated based on the trade-off between “lots exposed to these excursions” (which is proportional to β-risk) and “number of false alarms” (which is proportional to α-risk).

If the sampling frequency increases, the number of lots exposed to these excursions is reduced due to early detection. The trade-off is that there could be more false alarms when there are no excursions. Tighter process specs can also minimize β-risk, but again, this improvement is obtained at the cost of more false alarms. The goal is to find a sampling plan with the lowest possible β-risk for a given level of α-risk. We attempt to find the most effective sampling answer by looking at what appropriate control charts to use and

S

P

E

C

I

A

F

L

O

C

U

S

0.06

0.1

Lot Average and Lot Range

0.08

Fraction of Material-at-Risk

Fraction of Material-at-Risk

0.09

Lot Average and Variance Control Charts

0.07 0.06 0.05 0.04 0.03 0.02

0.05

X Wafers, 2Y Fields, 2Z Sites X Wafers, Y Fields, 2Z Sites

0.04

0.03

0.02

0.01

0.01 0

0 0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0

0.1

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

Fraction of False Alarms

Fraction of False Alarms

Figure 2. Fraction of material at risk (proportional to β-risk) vs. fraction

Figure 4: Fraction of material at risk vs. fraction of false alarms for

of false alarms (proportional to Îą-risk) for the same sampling plan but

two sample plans with a different total number of measurements.

with different SPC control charting strategies.

Doubling the number of fields per wafer reduces the amount of material at risk for any given fraction of false alarms.

then obtaining the sampling plan. Figure 2 shows that using the lot average and lot range control charts is not adequate for quick detection of the CD excursions at photo and etch. The addition of variance control charts using the exact same sampling plan greatly reduces the material at risk for a given fraction of false alarms.

Simply using a better set of control charts provides a far more favorable control strategy.

Increasing the number of fields from Y to 2Y results in significant reduction in material at risk (Figure 4). In fact, at a 3 percent false alarm rate, which is the normal operating region, the material-at-risk can be cut almost in half. In this case, the number of measurements required increases by a factor of two.

Assuming that we use lot average and variance control charts, we examine if sampling Y fields per wafer and 2Z sites per field is better than sampling 2Y fields per wafer and Z sites per field. The curves in Figure 3 demonstrate that sampling the same number of fields per wafer and twice as many sites per fields produces better results.

In this example, it is also more beneficial to allocate a fixed number of measurements to more fields on fewer wafers than to measure more wafers with a smaller number of fields. Figure 5 shows that sampling X wafers per lot, 2Y fields per wafer, and 2Z sites per field is better than sampling 2X wafers per lot, Y fields per wafer, and 2Z sites per field. These results were not

0.1

0.06

X Wafers, 2Y Fields, Z Sites

0.08

Fraction of Material-at-Risk

Fraction of Material-at-Risk

0.09

X Wafers, Y Fields, 2Z Sites

0.07 0.06 0.05 0.04 0.03 0.02

0.05

2X Wafers, Y Fields, 2Z Sites X Wafers, 2Y Fields, 2Z Sites

0.04

0.03

0.02

0.01

0.01 0

0 0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

Fraction of False Alarms

Fraction of False Alarms Figure 3. Fraction of material at risk vs. fraction of false alarms for

Figure 5. Fraction of material at risk vs. fraction of false alarms for two

two different sampling plans with the same total number of measure-

different sampling plans with the same total number of measurements

ments but a different allocation of measurements between fields per

but a different allocation of measurements between wafers per lot and

wafer and sites per field.

fields per wafer.

Summer 2000

Yield Management Solutions

63

S

P

E

C

I

A

L

F

O

C

U

S

surprising given that Table 1 showed the field-to-field variance, when properly computed, is larger than the wafer-to-wafer variance. (This improvement would not be obvious using a conventional nested ANOVA model.)

After applying the learnings from these sampling strategies to the 0.18 µm logic fab, the material at risk was reduced by roughly 28 percent at a constant 3 percent false alarm rate.

A mere 1 percent saving in material at risk can result in significant financial returns. For example, if a fab has 5000 wafer starts per week, 200 die per wafer, and a $100 selling price per die, then 1 percent material at risk has a revenue potential of $1 million a week, which translates into $52 million a year. With a very conservative yield benefit estimate of 10 percent, which is the difference between the baseline and excursion yield, and a baseline yield of 50 percent, the net benefit from saving 1 percent material-at-risk could be $2.6 million a year. In each case, the additional cost savings need to be weighed against the cost of any increase in measurements. In this case, the additional measurements required did not significantly increase the cost of metrology for the fab, so the change in sampling plans was clearly beneficial.

Summary

Properly characterizing baseline excursions and applying optimal sampling techniques allowed a notable increase in yield without a significant increase in cost. For this particular fab, the best answer was to double the number of fields per wafer sampled, thereby realizing a significant reduction in material-at-risk.

In order to maximize yield and minimize false alarms, each fab needs to precisely estimate the baseline statistics, understand the different types of excursions, their frequency, their yield impact, and how they carry over from photo to etch. Moreover, a stochastic model that captures all these dynamics and evaluates the risks/costs of different sampling strategies is needed to determine the best-customized CD sampling plan-and realize significant financial gains.

64

Spring 2000

Yield Management Solutions

Acknowledgements

The authors would like to thank Steve Reeves, Paul Ackmann, Renee Walker of AMD, Gus Pinto, Gil Griffin, Umar Whitney, Pat Lord, Harikrishnan Rajagopal, Dadi Gudmundsson, Richard Quattrini of KLA-Tencor Corporation, and Chayakrit Charoensiriwath of UC Berkeley for their support and assistance in executing this joint project.

References 1. R. Carnes and M. Su, “Long term cost of ownership: Beyond purchase price,” in the proceedings of IEEE/SEMI International Semiconductor Manufacturing Science Symposium, pp. 39-43, 1991.

2. C. Derman and S. M. Ross, “Statistical Aspects of Quality Control,” Academic Press, 1997.

3. S. A. Eastman, “Evaluating Automated Wafer Measurement Instruments,” SEMATECH Technology Transfer report 94112638A-XFR, 1995.

4. R. Elliott, R. K. Nurani, D. Gudmundsson, M. Preil, R. Nasongkhla, and J. G. Shanthikumar, “Critical dimension sample planning for sub-0.25 micron processes,” in the proceedings of Advanced Semiconductor Manufacturing Conference and Workshop, pp. 139-142, September 1999.

5. S. Kudva, and R. Potter, “Cost analysis and risk assessment for metrology application,” in the proceedings of SPIE, vol.

1673, pp. 2-13, 1992.

6. K. Monahan, R. Forcier, W. Ng, S. Kudallur, H. Sewell, H. Marchman and J. Schlesinger, “Application of statistical metrology to reduce total uncertainty in the CD-measurement of across-chip linewidth variation,” in the proceedings of SPIE, vol. 3050, pp. 1-14, 1997.

7. B. E. Stine, D. S. Boning and J. Chung, “Analysis and decomposition of spatial variation in integrated circuit processes and devices,” IEEE Transactions on Semiconductor Manufacturing, vol. 10, no. 1, February 1997.

Reprinted with permission from SPIE. Presented at SPIE ‘00 Microlithography.

Vol. 3998-120.

circle RS#009

Lithography S

P

E

C

I

A

L

F

O

C

U

S

Run-to-Run Control of Photolithography Processes

by W. Jarrett Campbell, Ph.D., KLA-Tencor Corporation

Run-to-run (R2R) control is rapidly becoming a key process control tool in the semiconductor industry. Due to the complexity and importance of the photolithography process, overlay and critical dimension are two common process parameters that are controlled via advanced process control. As the device fabrication process is extremely sensitive to key photolithography parameters, the benefits resulting from superior process control are significant.

Traditionally there have been two distinct approaches to process control. Statistical process control (SPC) is a technique in which the process output is monitored, usually ex situ, in order to detect an out of control process. SPC attempts to assign a causality relationship to an external disturbance. A process is considered out of control if output variance can be attributed to an assignable cause1. However, many times the machine has not reached an inoperable state. The operator simply compensates for the error by manipulation of a process input variable.

SPC does not define the control action necessary to return a process to an in control state. This decision is left to the operator or control engineer. SPC has seen widespread acceptance in discrete parts manufacturing where processes generally have high repeatability and natural variability.

The other approach to process control is APC. Sometimes referred to as engineering process control (EPC), APC uses measurements of important process variables to incorporate a feedback loop into the control strategy. The feedback loop uses a mathematical relationship to adjust process inputs based on the measure-ments in order to keep the product on target. APC accomplishes this by transferring variability in the output variable to an input control variable2.

Recently, a combination of SPC and APC has emerged to address processing issues in the semiconductor manufacturing industry. Known as run-to-run (R2R) control, this approach combines techniques from both SPC and APC in an attempt to reduce output variability.

From an SPC standpoint, R2R control extends traditional process monitoring by monitoring control actions for abnormality. APC practitioners can view R2R control as a supervisory controller that manipulates the setpoints of underlying tool controllers. The ultimate goal of R2R control is that of batch control for a lot of wafers. By analyzing the results of previous batches, the R2R controller should be able manipulate the batch recipe in order to reduce output variability.

The motivation for R2R control is a lack of in situ measurements of the product quality. Typically, in semiconductor manufacturing, the goal is to control qualities such as film thickness or electrical properties that are difficult, if not impossible to measure in realtime in the process environment. Most semiconductor products must be moved from the processing chamber to a metrology tool before an accurate measurement of the control variable value can be taken. Semiconductor processing tools generally have real-time controllers, typically PID loops, for controlled variables that can be measured in real-time. The variables are typically process inputs, such as chemical flow rates, or reactor states like temperature or pressure. The manufacturing engineer must specify a recipe that contains the setpoints of these inputs and states that will produce the proper output product. The job of the supervisory, Summer 2000

Yield Management Solutions

65

S

P

E

C

I

A

L

F

O

C

U

S

R2R controller is to adjust these recipes to reduce variability in the output product.

R2R control is further necessitated by the non-stationary nature of most semiconductor processes. While SPC is designed for stationary processes where output variations are independent, R2R control is able to compensate for drifting processes where output variations are correlated. The variation correlation is typically caused by changes in the processing environment. For example, in a deposition process, the reactor walls may become fouled by deposition as many products are processed.

This slow drift in the reactor chamber state requires small changes to the batch recipe in order to ensure that the product outputs remain on target. Eventually, the reactor chamber will be cleaned to remove the wall deposition, causing a step disturbance in the process.

Just as the R2R controller compensates for the drifting process, it will also compensate for the step disturbance to return the process to target after an environment change.

Many manufacturers have concentrated their efforts in R2R control on the photolithography process. Because lithographic processes are perhaps the most critical device fabrication steps, R2R control has the potential to significantly impact the quality and maufacturability of semiconductor devices. Using advanced APC software such as KLA-Tencorâ&#x20AC;&#x2122;s Catalyst, several large semiconductor manufacturers have applied R2R control to their manufacturing processes in order to minimize variations in both critical dimension (CD) and overlay registration.

Overlay control

One type of R2R control often employed in device fabrication is overlay control. The purpose of overlay R2R control is to minimize the errors in registration between subsequent masking layers. There are many types of overlay errors that may occur during manufacturing. Some of these errors include translation, rotation, magnification, and shear. Examples of these overlay errors on a wafer-scale are shown in Figure 1.

A typical means of controlling overlay errors is to setup a feedback loop between the overlay metrology tool and the masking tool via an APC software system. The APC system continually monitors overlay errors at each masking operation to detect slow drifts or sudden shifts. When a disturbance in overlay is detected by the APC system, the software automatically updates the stage and reticle offset parameters on the masking tool 66

Spring 2000

Yield Management Solutions

Grid Translation

Grid Magnification

Grid Rotation

Grid Shear/Orthogonally

Figure 1. Examples of overlay errors.

in order to eliminate the overlay errors. Figure 2 illustrates a typical feedback system for overlay control.

When overlay R2R control is implemented, many manufacturing benefits result. Semiconductor manuacturers have reported increased Cpk, reduced rework, reduced send-ahead wafers, and decreased engineering time devoted to stepper matching. Advanced Micro Devicesâ&#x20AC;&#x2122; Fab 25 has reported that their implementation of overlay R2R control has decreased overlay-specific photolithography rework by over 50 percent and three sigma translation errors were reduced by greater than 20 percent. In addition, AMD has been able to eliminate test-wafer and send-ahead qual procedures for overlay calibration because these procedures are now handled exclusively by the APC software.3

Figure 2. Overlay feedback system.

S

CD control

Another key process parameter in photolithography is CD. Just as overlay can be controlled using a feedback system, CD variations can be minimized using R2R control. However, CD control is not as easy as using a feedback system between the stepper and the CD metrology tool. This is because there is an etch bias, shown in Figure 3, that results during the post-photolithography etching process.

Etch Bias FI CD DI CD

Previous Layers Figure 3. CD bias induced by etch process.

Instead, a combined feedforward-feedback control system must be built around the etch process to ensure that the final inspection (FI) CD is at the appropriate process target.

First, the CD is measured after the development inspection (DI). This value is used in a feedforward manner to allow customization of the etch process recipe on a lot-by-lot basis. In other words if variability in the DICD value for a lot is measured, it can be directly compensated for by manipulation of that lotâ&#x20AC;&#x2122;s etch recipe.

In addition to feedforward control, feedback control is performed by monitoring the FICD resulting from the etch process. The APC system can detect drifts or shifts in etch bias caused by disturbances to the etch chamber.

The feedback system can then change the etch recipe appropriately to eliminate any systematic disturbances in the etch bias. Typically, the feedforward and feedback information is combined using a mathematical model of the etch process to determine an appropriate etch time for each lot.

P

E

C

I

A

L

F

O

C

U

S

One difficulty of this CD control approach is that drifts in the upstream photolithography process can be compensated for after the fact, but cannot be corrected directly at their source. Imagine a scenario where stepper drift has caused the DICD values after photolithography to drift so far that even the feedforward control system cannot properly compensate for incoming DICD variation. An example would be a case where the etch time required is outside the allowed process window. In order to prevent such difficulties, a second feedback loop, often called a cascade loop, can be implemented between the etcher and photolithography tools.

The purpose of the cascade loop is to ensure that etch times remain centered in the allowable process window.

This is done by manipulating the DICD target of the photolithography process. For example, if the etch tools have drifted such that long etch times are required to achieve the desired FICD target, the photolithography recipe can be adjusted in order to target a new DICD value that will not require as much etch to achieve the same DICD target. This feedback system is unique from those previously discussed because the monitored output of the control loop is actually the recipe settings used in the etch process. The manipulated variable in this control loop is the process target in the photolithography process.

Once a cascade loop is in place to set the DICD targets, it may also be desirable to add a third feedback control loop around the photolithography process to ensure variations in DICD are minimized. This third control loop is a simple feedback loop between the CD metrology tool and the stepper. Although the feedforward controller at the etch process can compensate for variations in DICD, the etch controller will perform better if the variations in incoming DICD are localized to a small operating region. This allows more precise modeling of the etch process and results in better control of FICD. Although it has been shown that several recipe settings including post-exposure bake time and develop time can affect changes in CD4, the most popular recipe setting used to control DICD is the exposure dose. Dose is often chosen because the photolithography process tends to have a strong, linear relationship between changes in exposure dose and changes in DICD. Once these three control loops are put into place, a comprehensive control system is now available to minimize variations in CD across the patterning process.

Figure 4 represents a schematic of such a control system.

Summer 2000

Yield Management Solutions

67

S

P

E

C

I

A

F

L

O

C

U

S

Summary

Figure 4: Comprehensive CD Control Strategy

Because CDs are very closely tied to semiconductor device performance, it is easy to imagine that the superior process control achieved through implementation of R2R control can have significant impact on the manufacturing process. IC manufacturers have validated that implementation of R2R control of CD can result in tremendous financial and manufacturing benefits. In particular, Advanced Micro Devices has reported that R2R control of CD has lead to a greater than 8 percent increase in overall device speed. This boost in performance allowed AMD to realize approximately $40 million in increased revenue per year. On the manufacturing side, AMD also reported that photolithography rework for CD variation was reduced by over 90 percent and that one sigma variation in FICD was reduced by 45 percent5.

Once the R2R control systems are developed, they must be implemented in software and integrated into the manufacturing facilities. This integration effort is the single largest roadblock preventing rapid deployment of R2R control solutions throughout the semiconductor industry. Advanced APC software, like KLA-Tencor’s Catalyst*, eases the integration effort by providing a software framework in which APC applications can be developed and implemented into semiconductor manufacturing systems.

The benefits of applying R2R control are significant.

One semiconductor manufacturer’s experience with R2R control is summarized in Table 1.

68

CD

Overlay

Rework reduced 90%

Rework reduced 50%

Std. dev. reduced 45%

Std. dev. reduced 20%

Speed increased 8%

Eliminated test quals

Revenue increased $40 million per year

Eliminated need for manual tool matching

Summer 2000

* Note:

Catalyst is the result of a three year, ten million dollar NIST-sponsored joint research project between KLA-Tencor’s Control Solutions division, Advanced Micro Devices, and Honeywell. The research project established SEMATECH and SEMI standards for APC software. Catalyst is the first commercial APC software to be based on these standards and it is SEMATECH CIM Framework compliant.

References

Integrating APC into the fab

Table 1: Results from R2R Control Production Implementations

R2R control is rapidly becoming a key process control tool in the semiconductor industry. Because of the complexity and importance of the photolithography process, overlay and CD are two common process parameters that are controlled via R2R control. Advanced Process Control (APC) software, such as KLA-Tencor’s Catalyst, provides a means of integrating R2R control solutions into today’s device fabrication facilities. By using such software, many of the top semiconductor manufacturers have been able to reduce the effort, cost, and time required in deploying APC in their production environments.

6

.

Yield Management Solutions

1. Douglas C. Montgomery. Introduction to Statistical Quality Control. John Wiley & Sons, 2nd edition, 1991.

2. Douglas C. Montgomery, J. Bert Keats, George C. Runger, and William S. Messina. Integrating Statistical Pprocess Control and Engineering Process Control. Journal of Quality Technology, 26(2), April 1994.

3. Christopher A. Bode. Run-to-Run Control of Photolithography Overlay. Proceedings of SEMATECH AEC/APC Symposium XI. October 1999.

4. Thomas F. Edgar, Stephanie W. Butler, W. Jarrett Campbell, Carlos Pfeiffer, Chris Bode, Sung Bo Hwang, and K.S. Balakrishnan. Automatic Control in Microelectronics Manufacturing: Practices, Challenges, and Possibilities.

Automatica. Accepted for Publication.

5. Anthony J. Toprac and W. Jarrett Campbell. Run-to-Run Control Using the APC Framework. Proceedings of SEMATECH AEC/APC Symposium X, October 1998.

6. Terry Caudell. APC: An Enabling Technology in the Subquarter Micron Era. Proceedings of AEC/APC Workshop Europe. March 2000.

Defect Reduction F

E

A

T

U

R

E

S

Enhancing Sensitivity and Throughput in Brightfield Inspection

by P.H. Wu, J.P. Wu,TSMC Fab 3; J. Liao, C. Chuang, K. Nafisi, M. Dishner, KLA-Tencor Corporation

This paper was presented at KLA-Tencor’s Yield Management Solutions Seminar during SEMICON/Europa in April 2000.

It was edited for this publication by Mark Keefer, KLA-Tencor Corporation.

As integrated circuit feature sizes continue to shrink, and device cycle times are reduced, defect inspection technology must continue to improve for device manufacturers to manage their yield. The introduction of the KLA-Tencor 2139 increased sensitivity, defect capture and throughput on its 2100-series brightfield optical imaging inspector product line. Primary sensitivity improvements are achieved by decreasing the pixel size and by automating the recipe development of segmented thresholding routines (AutoSAT). Productivity is enhanced by job queuing and faster edge die inspection (double detection of edge die defects without re-swathing).

From December 1999 to March 2000, TSMC’s Fab 3 facility evaluated a 2139 beta system versus the baseline 2138 system for throughput and sensitivity. All layers were 0.18 µm to 0.22 µm design rule logic devices. A 2138 system already installed in the fab was upgraded to a 2139 system.

Negligible baseline shift between the tools using the same inspection recipe and wafer was observed. Data were collected to show the robustness of job queuing, the sensitivity of the 0.16 µm pixel, the throughput using the new version 5.2 software, and the robustness of SAT recipes for production.

Additionally, the sensitivity improvement obtained by optimized SAT recipes (using AutoSAT software) relative to the baseline mean-range image processing method was evaluated.

Throughput results

After verifying that there was no baseline shift on Metal 4, Spacer, and Polysilicon 1 etch levels, inspection equipment throughput and productivity was tested. Inspection

equipment productivity was increased in two ways.

First, the multi-tasking feature of Windows NT software (KLA-Tencor 213x version 5.2) allows job queuing. While an inspection is in progress, the next inspection lot and recipe can be prepared, reducing idle time on the inspector. The time savings can be quite significant, especially in a SMIF fab with pod load and unload times. Figure 1 shows the time savings achieved using the job queuing feature for inspection of two lots (in the left and right cassettes), two wafers per lot.

Another throughput improvement in the 2139 is fast edge die inspection, referred to as the Mass Memory Edge Die (MMED) feature. Prior to MMED, double detection of edge die defects required that the edge die be re-swathed, which adds considerable time to the inspection (referred to as the TEO method, meaning “triple edge only”. First the wafer center is scanned, then the left side, then the right side). The MMED upgrade allows sufficient inspection data to be stored in the memory buffers so that the edge die do not require reswathing. Figure 2 compares inspection time on 0.22 µm Metal 3 etch wafers from five different lots (using 0.39 µm pixel). The average inspection time using TEO is 14 minutes 47 seconds; the average time using MMED is 12 minutes 18 seconds, a 17 percent improvement.

Summer 2000

Yield Management Solutions

69

F

E

A

T

U

R

E

S

60 Time (minutes)

50 40 30 20 10 0

2138 5.1 DOS

2139 5.2 NT

2138 DOS = 50 m 6 s 60s

13s

90s

21m7s

5s

60s

60s

13s

90s

21m28s

5s

60s

Load L. SMIF

Load L. Cassette

Load Recipe

Run Inspection

Unload L. Cassette

Unload L. SMIF

Load R. SMIF

Load R. Cassette

Load Recipe

Run Inspection

Unload R. Cassette

Unload R. SMIF

0

0

0

19m17s

0

0

0

0

0

19m43s

0

0

2139 NT = 39 m 5.2 NT time saving: 10 m 54 s (>20%) Figure 1. Breakdown of time savings achieved using the job queuing feature.

Sensitivity results

Smaller pixel sizes can increase defect detection sensitivity for process levels that are limited by inspection resolution. The 2139 0.16 µm pixel was compared to the 2138 0.25 µm pixel. The increased capture of the 0.16 µm pixel on a 0.18 µm Polysilicon 1 etch level is shown in Figure 3. The defect counts are cumulative totals of five wafers from five different lots.

Figure 4 shows SEM images of some of the defect types detected using the 0.16 µm pixel in die-to-die (random) mode on the 0.18 µm design rule Polysilicon 1 etch level. These defects were not caught using the 0.25 µm pixel. In conjunction with the smaller pixel, a higherresolution camera provides sharper images for defect

review, making verification of real and false or nuisance defects during inspection recipe development easier.

Inspection sensitivity is determined by resolution (small pixel size) as well as suppression of pattern and process variation noise. Segmented Auto Thresholding (SAT) is an image processing technology used to suppress pattern and process noise. SAT segments the wafer image based on the gray level signature of the pattern and dynamically sets separate thresholds for each segment, resulting in higher sensitivity than the mean-range image processing method. An AutoSAT routine has been developed to simplify SAT recipe 1000 0.25µm pixel (2138)

443 265

0.16µm pixel (2139)

TEO MMED

Inspection Time (minutes)

16

12

8

122

100

120

70 44 29 19 17

10

2

2

4 1 0

Test 1

Test 2

Test 3

Test 4

Test 5

Figure 2. Comparison of inspection times for Metal 3 etch level.

70

Defect Count (log scale)

201

20

Summer 2000

Yield Management Solutions

Particle (open)

Particle (dense)

Scratch

Pattern

Poly Residue

False

Figure 3. Poly etch defect capture comparison (0.16 µm and 0.25 µm pixels).

F

E

A

T

U

Oxide Hole

Particle

Pattern

W-Puddle

R

E

S

Figure 6. SEM images of 0.22 µm design rule Metal 3 etch defect Figure 4. SEM images of 0.18 µm design rule Polysilicon 1 etch

types uniquely caught by the AutoSAT recipe

defects detected using 0.16 µm pixel.

setup. AutoSAT recommends optimal segmentation schemes from a pre-defined selection of templates, then automatically optimizes the threshold for each scheme.

The automation reduces recipe development time, and results in more consistent recipes. Figure 5 compares defect detection sensitivity of AutoSAT and mean-range image processing on a 0.22 µm logic device Metal 3 etch level. The defect counts are cumulative totals of nine wafers from nine different lots. Defect capture of particles in dense arrays and defocus defects in particular were improved.

453 289 Mean-Range

70

AutoSAT

60

Using AutoSAT, the 2139 also uniquely detected several defect types not detected by mean-range image processing on this Metal 3 etch level.

Summary

The productivity and sensitivity improvements of the 2139 defect inspection system were evaluated. The job queuing feature improved tool utilization by over 20 percent. Inspection time per wafer using the 0.39 µm pixel was reduced by about 17 percent using the fast edge die mode. The smaller 0.16 µm pixel size increased defect capture relative to the 0.25 µm pixel, and additional sensitivity was achieved using the AutoSAT image processing algorithms. Additional data also showed that SAT reduced the level of nuisance defects such as blister defects on Metal 3 and 4 etch levels.

Defect Count

circle RS#047 50 40 30 20

False

Color

Particle (open)

Defocus

Oxide Hole

Pattern

Particle (PL)

W Puddle

Particle (dense)

Metal Residue

0

Bright Metal

10

Figure 5. Comparison of AutoSAT and mean-range image processing methods on metal etch.

Summer 2000

Yield Management Solutions

71

Defect Reduction F

E

A

T

U

R

E

S

CMP Defect Detection and Process TBI Control using the Surfscan SP1

By Katia Devriendt, Paul Mertens, Wim Fyen, Karine Kenis, Marc Schaekers, IMEC, Dale Guidoux, Grant Sergeant, Stephane Robic, Rene Moirin, KLA-Tencor Corporation

The Chemical Mechanical Planarization (CMP) process is now widely used to provide global planarity of layers during the fabrication of integrated circuits. Successful yield management of CMP requires detection of all critical defects in the presence of noise sources such as film thickness non-uniformity within a wafer or process variation within a lot. CMP defects can be separated into two categories; residual slurry particles or other foreign material on the surface, and microscratches or pits in the surface. Both defect types are known to have a negative impact on device yield. In a joint study between IMEC and KLA-Tencor, an experiment was performed to show how the Surfscan SP1TBI unpatterned wafer inspection system can be used to monitor both types of critical defects. Electrical test patterns were generated on CMP wafers to study the correlation of device yield to defect types.

In our experiments, High Density Plasma (HDP) oxide layers were polished using IMEC’s standard oxide CMP process. After cleaning on a scrubber using ammonia on the brushes, the polished wafers were inspected on a Surfscan SP1TBI. As seen in the Surfscan SP1TBI optics layout (Figure 1), the tool has both a normal and oblique incident beam and two collection channels, wide and narrow. The wide and narrow channels were both calibrated to give similar defect counts using Polystyrene Latex (PSL) spheres. On a standard CMP polish and clean, the wafers also exhibited similar Light Point Defect (LPD) counts in both the wide and narrow collection channels.

We suspect that the LPDs detected in both channels are primarily surface particles, as we would expect particles to scatter into both collection channels, whereas microscratches or surface void defects should scatter preferentially into only one of the detectors. To confirm this hypothesis, we added or “spiked” the standard CMP slurry with 1.5 µm diameter alumina particles.

Another set of HDP oxide wafers were then polished with the contaminated slurry, 72

Summer 2000

Yield Management Solutions

cleaned and scanned on the Surfscan SP1TBI. The wafer scans for each channel are shown in Figure 2. Using an oblique incident “C” polarized beam, the wide channel exhibited a much higher LPD count than the narrow channel. Under review using a CRS confocal laser review microscope, we confirmed that the higher counts Normal Incidence Beam Dark Field Wide PMT

Brightfield Channels SNT Tangential Nomaski DIC

Dark Field Narrow PMT

Ellipsoidal Collector

Lens Collector

Wafer

Figure 1. SP1 TBI optics layout.

Oblique Incidence Beam

SNT Radial Deflection

F

SP1TBI recipe: - Oblique C-UU Full - LSE-diam: min 0.15 µm max 1.0 µm Narrow-channel

Figure 2. Using an oblique incident beam and “C” polarization, the wide-channel exhibited a much higher LPD count than the narrow channel.

detected only in the wide channel were primarily microscratches (Figure 3). To further verify our hypothesis, we deposited approximately 5000 PSL spheres to the wafer containing microscratches. The LPD count increased about 5000 counts in both channels. To be sure that the effect witnessed is not just limited to the properties of PSL spheres, we also measured standard CMP polished wafers that were dipped into a solution of slurry to add typical residual slurry particles. Similar amounts of LPDs were counted in both channels in this case as well. In summary, the microscratch counts were detected predominately in the wide collection channel, whereas surface particles were counted in both the wide collection channel and the narrow collection channel.

In the next phase of the experiment, “snake” and “fork” patterns were deposited on a polished oxide surface to test for intra-level defects represented by (a) shorts between the snake and fork lines and (b) discontinuity of the snake lines (Figures 4 and 5). Inter-level defects characterized as electrical breakdown of the polished

A

T

U

R

E

S

oxide between metal capacitor plates were also tested. Two sets of wafers were polished using a standard slurry and two sets were polished using a slurry contaminated or “spiked” with large silica particles greater than 1 µm to induce a larger percentage of microscratches. One set of the standard slurry polished wafers received a scrubber clean with dilute ammonia and one set was cleaned with ammonia plus an HF wet etch.

No significant difference in the density of intra-level electrical shorts or discontinuities in the standard slurry was detected as compared to the density of defects in the contaminated slurry for either cleaning condition.

CMP condition: - HDP oxide - slurry: fumed SiO2 (ILD-1300) with 1.5 µm alumina particles - cleaning: scrubber only

Wide-channel

E

particle microscratch

microscratch particle Al

a

Al

oxide Si

Al

b Figure 4. Inter-metal defects on

Figure 5. Electrical breakdown

metal meander-fork structures

characteristics of polished oxide

deposited on a polished oxide

(inter-level defects between metal

surface (0.4 µm line/0.4 µm

capacitor plates).

spacing). (a) shorts between meander-forks (b) discontinuity of meander lines.

The effect of cleaning chemistry on interlevel defects was more significant. For the standard slurry polish and the contaminated slurry polish with just a dilute ammonia scrub, the results are acceptable.

But, when applying an HF wet etch to a contaminated slurry polish (more scratches present), the results are catastrophic. The HF etches the oxide surface scratch defects and causes early electrical breakdown between the capacitor plates.

Figure 3. Microscope review confirms the spiked slurr y (right) exhibits a higher number

The study has shown that the Surfscan SP1TBI is an effective tool for monitoring CMP slurry residue and microscratch defects that can lead to device yield problems.

circle RS#013

of microscratches.

Summer 2000

Yield Management Solutions

73

Process Parametrics F

E

A

T

U

R

E

S

Analysis of Phosphorous Auto-doping in P-Type Silicon using Corona Oxide Silicon Techniques

By Brian Letherer and Greg Horner, KLA-Tencor Corporation

Semiconductor fabrication facilities rely on the integrity of the silicon to manufacture submicron devices. Cross contamination of P-type silicon to N-type carriers or vice versa in the near surface region of the silicon can be detrimental to device performance. Semiconductor processing typically includes numerous diffusion and pre-clean steps, any one of which might auto-dope a P-type silicon substrate with phosphorous. In-line monitoring of these near-surface doping effects enhances the ability to diagnose auto-doping problems.

A non-contact Corona Oxide Silicon (COS) measurement technique has the ability to detect cross-contaminated P-type silicon with phosphorous from wet clean benches and diffusion furnaces. Results show COS flatband (Vfb) and oxide total charge (Qtot) measurements are sensitive to various levels of intentional phosphorous contamination implanted into the silicon at pre-oxidation.

Phosphorous at the silicon/oxide interface can pile up and create an electrically active thin “N” skin. Phosphorous from this thin “N” skin is shown to change the electrical characteristics of near surface region of the silicon. The detection of unwanted phosphorus with the use of COS in-line monitoring can greatly reduce the response time when auto-doping problems occur.

Contamination control has long been an integral part of semiconductor manufacturing.

Yield loss due to small amounts of contamination in silicon can cause catastrophic loss of product due to slight changes in electrical behavior of silicon based devices. The source of contamination can be widespread, as well; there are a variety of potential sources in a silicon manufacturing facility. Isolating and eliminating these sources of contamination 74

Summer 2000

Yield Management Solutions

can also be difficult and tedious. Phosphorous, in particular, is used in many areas in a fab as a dopant and can cause significant problems to the near-surface silicon region, the primary region where a device operates.

Detection of contamination problems can be time consuming and timely feedback of detection is also desired to reduce the amount of product at risk. An in-line metrology tool to monitor contamination is essential in a manufacturing environment. The COS, which is commercially available, has the ability to monitor contamination and give timely feedback to ensure the risk of contamination is minimal.

The primary sources of phosphorous are generally POCL3 doping of polysilicon and phosphorous implant. Bare silicon wafers, with high phosphorous content, (test or monitor) processed in wet sinks or high temperature diffusion can readily out-diffuse and will auto-dope wafers with P-type silicon in the same process step or in subsequent process steps. The source of the phosphorous contamination tends to be very localized, as only certain sections of a diffusion furnace or wet-cleaning processes will be contaminated.

Quartzware in diffusion furnaces and wafers that are run continually in the diffusion furnace for thermal mass may retain phosphorous. On subsequent runs phosphorous will out-diffuse at temperatures above 850°C and diffuse into exposed silicon substrates of

F

A

T

U

4

Due to the nature of the low level of doping in the near-surface region after oxidation, there are very few current methods available that can detect unwanted phosphorous in the near-surface region of the silicon.

Many of the technologies employed require that a patterned device must be generated to electrically test for anomalies, such as CV. This requires extra processing and will not allow for timely feedback. COS technology is an inline, non-contact monitoring tool that will provides timely feedback.

COS measurement technique

A KLA-Tencor Quantox COS (Corona Oxide Semiconductor) system was used for all of the electrical characterization work presented here. As in the CV technology, COS analysis requires that an electrical bias be applied to the sample to measure the electrical properties of the near surface silicon and oxide layer. A small amount of charge is precisely deposited on the oxide surface by ionizing moisture and CO2 above the wafer surface5. A sweep is produced in a step-wise fashion by depositing increments of surface charge to bias the underlying silicon from inversion to accumulation.

A vibrating Kelvin probe is then used to measure the surface voltage (Vs) response of the deposited surface charge at each step of the sweep. A high-speed light source photogenerates carriers in the near surface region and the resultant flood of carriers flattens the band bending in the silicon. The resultant surface photo voltage (SPV) is similarly measured during each step of the surface charge sweep and provides a mea-

E

S

0.2

0

0

Dit:from slope

-0.2

SPV (Volts)

2

-2

Once phosphorous has entered the silicon it will accumulate at the near-surface region of the silicon during subsequent oxidation processes3. It has been shown that phosphorous will induce a positive oxide charge in native oxide, prior to an oxidation. In this mechanism P5+ replaces Si4+ in the oxide4. The data obtained in this study supports the hypothesis that very little phosphorous is incorporated in the oxide during a conventional thermal oxidation.

R

Vfb:SPV=O

Vs (Volts)

lesser doping concentration1. Wet cleaning processes can also accumulate impurities, such as phosphorous, from wafers that came from a heavily doped high temperature process, like diffusion POCl3 step. Phosphorous from the contaminated clean step will deposit on the surface of the silicon and create an N-skin2. The phosphorous is then activated in the near surface region of the silicon during successive high temperature process steps.

E

-0.4 Tox:dQ/dVs

-4 -10.0

-5.0

0

5.0

-0.6 10.0

Deposited Charge x1E-8 (C/cm2) Figure 1. A diagram of a surface voltage vs. deposited charge cur ve and a surface photo voltage vs. deposited charge cur ve as measured

by COS.

surement of the silicon band-bending. From these two methods (Vs and SPV), charge versus surface voltage (QV) and charge versus SPV curves can be generated as displayed in Figure 1. From these curves measurements such as flatband voltage (Vfb), total charge in the oxide (Qtot) and density of interface traps (Dit) can be extracted.

Vfb is calculated when the SPV is 0 on the SPV verses surface voltage curve. Qtot is the amount of charge in the oxide at flatband. Dit is derived from the QV curve using the Burglund method.

COS also has the ability to measure near surface doping in the silicon. This is accomplished by biasing the silicon into strong inversion using onto a site. A guard ring is then placed around the site with opposite signed charge to place the silicon into accumulation. A known charge pulse is then applied to the central region into deep depletion. The deep depletion transient response is analyzed to extract both the doping level and the generation lifetime of the near-surface silicon.

Experimental

In this study, phosphorous was intentionally introduced into the silicon to mimic a contamination problem.

Bare P-type silicon eight inch wafers were used with a doping level of 1.5E15 #/cm3. The samples were implanted with various amounts of phosphorous ranging from a control wafer of no implant, to a wafer that received 3E12 #/cm2 dose of phosphorous implantation.

Oxidation was then done in a vertical furnace utilizing a standard CV oxidation process at 900°C, which did not include the use of chlorine, to produce 950 Ă&#x2026; of Summer 2000

Yield Management Solutions

75

F

E

A

T

U

R

E

S

oxide. Wafers were then etched back to varying oxide thicknesses, using an HF wet stripping process. Each wafer was stripped back three separate times to obtain oxide thickness levels of 850, 750 and 300 Å. COS measurements were performed after the etch step, at each thickness level.

The wafers were stripped back to determine the sensitivity levels of measurements to detect phosphorous on thin oxides. In general, higher measurement precision is required to monitor thin oxide layers for potential contamination in the near-surface substrate. We show here that the COS measurements retained excellent sensitivity as the oxide thickness decreased.

n-skin E + + + + +

+ + + + +

– – – – –

– – – – –

SiO2

SiO2

A

B

EF p-Si x

Figure 3. Simplified band diagrams for a) phosphorous N-skin, and b) phosphorous N-skin pulled to the flatband condition by negative surface charge. To first order, the surface charge density at the flatband condition equals the phosphorous dose.

Results

CV versus COS measurements have been well-documented (5). Changes in flatband due to changes in the charge in the oxide and underlying substrate show better correlation with COS compared to conventional CV methods in previous studies.

ative charge density equal to Dphos must be applied to the oxide surface to pull the underlying silicon to the flatband condition (Figure 3b). The resultant voltage scales linearly with Tox and Dphos (the probe-to-silicon workfunction difference and 2nd order band bending effects are neglected in the following equations): Qsurface flatband = DPhos

0 -1

Vfb (Volts)

-2

VFB =

-3 -4 -5 -6 -7 -8 -9 0.00E+00 5.00E+11

950 Å

Note that while Vfb is an excellent indicator of N-skin contamination on relatively thick oxides (Tox>200 Å), the sensitivity drops steadily as the oxide thickness is decreased (see, for instance, the 300 Å oxide in Figure 2).

800 Å 700 Å 300 Å

1.00E+12

1.50E+12

2.00E+12

2.50E+12

3.00E+12

3.50E+12

Phosphorous (#/cm2) Figure 2. Phosphorous implant dose vs. Vfb as measured using COS techniques.

Figure 2 shows the dependence of Vfb on implant dose.

The 950 Å thermal oxides were repeatedly wet-etched to provide measurements at several oxide thicknesses.

The Vfb behavior is similar to the dependence of threshold voltage on implant dose, as outlined here.

Consider a thermal oxide with initial total oxide charge which is much lower than the contamination level that must be detected. We assume that the phosphorous contamination is incorporated in the near-surface region of the silicon, but not in the oxide (as in Figure 3a; this assumption was verified experimentally with SIMS and COS analysis). In CV or COS testing, a neg76

DPhos DPhos • Tox = Cox εox

Summer 2000

Yield Management Solutions

The Quantox is also capable of measuring the total oxide charge, Qtot, a parameter that contacting techniques such as conventional CV are not able to measure.

The Qtot parameter is distinctly different from the Vfb measurement, since it’s sensitivity does not fall as Tox is reduced. Again assuming that the oxide total charge is much less than the dose of contaminant, we find (neglecting 2nd order band bending effects): Qsurface flatband = –Qtot = DPhos The Qtot parameter is often used on thin gate oxides (down to 20 Å), where conventional Vfb measurements provide a poor signal-to-noise ratio. Figure 4 shows Qtot acquired on the same set of phosphorous contaminated samples. As before, the samples were repeatedly wet-etched to demonstrate the sensitivity of the technique as a function of Tox.

F

2.50E+12

Dtot (#/cm2)

800 Å 700 Å

1.50E+12

300 Å

T

U

R

E

S

1.00E+12

5.00E+11

0.00E+00 0.00E+00 5.00E+11

1.00E+12

1.50E+12

2.00E+12

2.50E+12

3.00E+12

3.50E+12

Phosphorous Implant (#/cm2) Figure 4. Phosphorous implant dose vs. Qtot using COS measurement techniques.

Dit does not show any significant increases upon differing levels of phosphorous implantation, except in the case at high dose of phosphorous in the 3E12 #/cm2 range, shown in Figure 5. This shows that the silicon/silicon dioxide interface is not a factor in influencing Vfb and Qtot measurements. The oxidation at post implant was able to pacify any damage that may have incurred at the silicon/silicon dioxide interface during the implant. Upon higher doses at and above 3E12 #/cm2, however, implantation damages to the silicon/silicon dioxide interface creates a significant jump in Dit for all oxide thicknesses. Dit is effected by implant damage but not effected by phosphorous pile up at the silicon/silicon dioxide interface.

Secondary Ion Mass Spectroscopy (SIMS) was used on sister wafers with implant levels similar to the ones used in the study to show the doping profile. The depth of dopant for phosphorous after oxidation on these wafers ranged from 600 to 1500 Å into the silicon.

This shallow depth is due to the accumulation of phosphorous in the near-surface region of the silicon. This 0

Dit (#/Ev cm2)

A

depth was too shallow to be measured by conventional doping techniques, including COS and CV. The pulsed doping measurements, a technique used by COS, were not able to monitor the effects of the shallow phosphorous contamination in dose levels explored in this study.

950 Å

2.00E+12

E

-1

950 Å

-2

800 Å

-3

700 Å

-4

300 Å

-5 -6 -7 -8 -9 0.00E+00 5.00E+11

1.00E+12

1.50E+12

2.00E+12

2.50E+12

3.00E+12

The changes in Vfb and Qtot due to phosphorous implants in the doses used in this study were significant.

These changes will severely alter the device electrical characteristics and parameters. This has been independently confirmed by extended flow experiments that were tested at metal 1 using a conventional parametric test.

Summary

COS measurement technology is an in-line non-contact method that provides timely feedback for monitoring possible phosphorous contamination from various sources.

Vfb maintains good sensitivity on samples with oxide thicknesses down to 300 Å, although the sensitivity is expected to scale with Tox. Qtot measurements retain high sensitivity even on oxides with thicknesses of less then 300 Å. This is in contrast to the Vfb measurements in Figure 2, where the measurement sensitivity decreased as Tox was reduced. The Qtot , therefore, is the preferred monitoring measurement for oxide thicknesses of less then 300 Å.

References 1. “Silicon Processing, Vol. 1” S Wolf and R. N. Tauber, Lattice Press, Sunset Beach CA (1986).

2. In line Charge-trapping Characterization of dielectrics for sub-0.5 um CMOS Technologies, P. K. Roy, C. Chacon, Y. Ma, G.S. Horner Mat. Res. Soc. Symp. Proc. Vol. 473 (1997).

3. “Oxynitridation-Enhanced Diffusion of Phosphorus in <100> Silicon” N. K. Chen and C. Lee, Elect. Chem.

Soc. Vol. 142, No. 6 (1995).

4. Phosphorous-induced positive charge in native oxide of silicon wafers, H. Shimizu, C. Munakta, Appl. Phys. Lett., 64 (26), pp. 3598-3599, 27 June 1994.

5. M.S. Fung and R.L. Verkuil, (Spring Electrochemical Meeting, abstract no. 169, (1988)).

6. Replacing C-V Monitoring with NON Contact COS Charge Analysis, K. Catmull, R. Cosway, B. Letherer and G. Horner, Mat. Res. Soc. Symp. Proc. Vol. 473 (1997).

3.50E+12

Phosphorous Implant (#/cm2) Figure 5. Phosphorous implant dose vs. Dit using COS measurement

Reprinted with permission from SPIE. Presented at SPIE ‘99 Microlithography.

Vol. 3884-14.

techniques.

circle RS#035

Summer 2000

Yield Management Solutions

77

Product News iSupport™

iSupport is a fast, comprehensive and secure on-line customer support offering that enables KLA-Tencor’s technical support and applications engineers to remotely access data from KLA-Tencor tools and operate them in real time to diagnose and rapidly resolve problems when they occur—all via a secure on-line connection controlled by the customer at all times. iSupport is much broader than remote diagnostics, providing continuous, automated monitoring, problem detection and notification, equipment run-time and real-time performance reports and analysis, secure and safe remote diagnostics and problem resolution. With iSupport, any assistance that doesn’t require parts replacement can be quickly and completely resolved on-line. This is accomplished by installing a diagnostic server to monitor KLA-Tencor tools in the customer’s fab. The diagnostic server is connected to KLA-Tencor’s On-line Support Center where authorized support personnel provide immediate help at the first sign of an equipment problem. The ability to provide rapid on-line assistance to our customers, as well as real-time equipment performance and process data will result in higher KLA-Tencor tool productivity, improving our customers’ Cost of Ownership and asset utilization. iSupport connectivity is designed into the most recent KLA-Tencor tools and will be engineered into all future KLA-Tencor product lines. circle RS#033

AIT III

The AIT III is the newest member of KLA-Tencor’s production-proven AIT family, and has the increased sensitivity needed to meet the production pattern tool monitoring requirements of the 0.13 micron technology node. It features improved low-angle illumination and low-angle optics, as well as new noise suppression techniques, to deliver higher throughput darkfield inspection. Customizable hard mask apertures enable optical filtering to enhance defect capture at specific process layers. These features, as well as an additional smaller laser spot size and a collection channel for high angle scatter, improve defect detection on dense patterns as well as enhance defect capture of CMP microscratches and low profile (flat) pattern defects. The AIT III is 300 mm capable and customers can upgrade their AIT II tools to AIT III performance. circle RS#046

78

Spring 2000

Yield Management Solutions