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Critical Dimension Sample Planning for 300 mm Wafer Fabs Sung Jin Lee, Raman K. Nurani, Ph.D., Viral Hazari, Mike Slessor, KLA-Tencor Corporation, J. George Shanthikumar, Ph.D., UC Berkeley
Critical dimension (CD) control is crucial in photolithography and etch processing steps, because of the relationship between gate length and device speed performance. To control the CD, values of lot average and/or lot variance are generally plot ted on SPC charts to detect mean and variance excursions that occur during these processes. An optimal sampling plan and control methodology must not only enable resolution of important (yield-impacting) excursions, but also minimize the time it takes to detect an excursion, thereby minimizing the number of lots exposed to an excursion.
A CD sampling plan specifies what CD measurements are performed, i.e., how many lots, how many wafers per lot, how many fields per wafer, and how many sites per field; as well as which wafers, fields, and sites are measured. The control methodology specifies how CD measurements are used to characterize normal variations and monitor and control deviations. This includes design of appropriate SPC charts and APC (automatic process control scheme with either closed or open loop feedback). A comprehensive methodology was previously presented2 to evaluate the effectiveness of different sampling plans by using the data from a 200 mm advanced logic fab. The effectiveness of a given sampling plan was evaluated by trading off the beta risk (probability of having material at risk) and the alpha risk (probability of having a false alarm). The current paper extends this methodology to the 300 mm domain, discusses potential issues for CD control of 300 mm patterning processes, as well as sampling recommendations for certain conditions. The primary driving force for the 300 mm transition is the anticipated reduction in total production cost per square inch of silicon. The key to achieving this is to increase 60
Spring 2001
Yield Management Solutions
the productivity of the yielding die and wafers at minimum total cost. It is very important to note that the total cost includes not only the cost of producing the wafers but also the cost of controlling the process for minimizing the material at risk. While reducing the total cost of operations, it is critical to optimize the value of in-line defect and metrology inspection. Otherwise, the cost of increased material-at-risk due to poorly optimized inspection methodology will outweigh the savings from reduced investment in process control. A 300 mm wafer has 2.25 times more area than a 200 mm wafer. If all other parameters are held constant, it results in 2.25 times more die per wafer, with correspondingly more material exposed to process excursions. Along with the 300 mm transition, the semiconductor industry is also transitioning from 248 nm to 193 nm lithography, from aluminum to copper interconnect metals, and from silicon dioxide to low-Îş interconnect dielectrics, all driven by ever-shrinking design rules. Although a statistically determined sampling plan is essential in understanding and reducing material-at-risk, in practice, many sampling plans are still determined by historical precedent. Few papers present statistical approaches to determining the optimal sampling plan1. In the current paper, issues and concerns regarding the importance of CD control in a 300 mm fab are presented. A simulation study is presented, where 300 mm CD variations and excursions are simulated and compared