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S O L U T I O N S Process Module Control Strategies for the Semiconductor Industry

SPECIAL SPECIAL ISSUE: A A Focus Focus on on 300 300 mm mm 11 11 COVER COVER STORY STORY — — , M ICROECONOMICSOF OF METROLOGY ETROLOGY MICROECONOMICS YIELD IELD,, AND AND P PROFITABILITY ROFITABILITY IN IN 300 MM MM M MANUFACTURING ANUFACTURING 32 T TS SM MC C’’S S T TR RA AN NS SIIT TIIO ON NT TO O 300 300 M MM M— —A AN N INTERVIEW NTERVIEW WITH WITH D DR R.. N NUN UN-S -SIAN IAN T TSAI SAI 41 41 D DE EF FE EC CT TS SA AM MP PL LE E P PLLA AN NN NIIN NG G IIN N 300 300 F FABS ABS

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300 mm: A Look Forwar d Despite an industry down-turn, 300 mm wafer manufacturing is moving ahead, and this year 300 mm production fabs are coming online. The industry can expect substantial 300 mm growth during the next few years.

16 The Challenges of 300 mm CMP Chemical mechanical planarization (CMP) at 300 mm faces not only the traditional 200 mm challenges but also some new ones, including stringent process-control, metrology, automation requirements, the expense of capital equipment (cost of ownership), and tool reliability. 24 Defect Management for 300 mm and 130 nm Technologies The economic and technical demands of the transition to 300 mm wafers and the ramping of 130 nm generation devices into volume production necessitates not only more stringent inspection and control strategies, but also new ways of inspecting. One method is to mix inspection techniques that traditionally were isolated— such as e-beam and brightfield/darkfield—to create a customized strategy for defect control. 35 Reducing Risk at 300 mm The success of transitioning to 300 mm hinges on minimizing three kinds of risk for manufacturers: investment risk, technical risk, and obsolescence risk. Reducing these risks requires that the equipment supplier and the wafer manufacturer work together and share the burden of process development and assessing equipment capability. This ensures flexibility in processes, enables tool maturity and reliability, and minimizes obsolescence of tools. 41 Defect Sample Planning in 300 mm Fabs While the transition to 300 mm offers opportunities for economies of scale, it also brings new yield-management challenges. Defect Sample Planning, if part of a planning process and layout for 300 mm fabs, can help manufacturers achieve the gains they seek as they move to the new wafer size. 49 Reticle Automation Pathways for 300 mm-Era Fabs Like wafers, reticles face dangers such as operatorinduced defects, random electrostatic discharge damage, or just dropping and breaking. As fabs move to 300 mm wafer production and advanced processes, mask shops are making a parallel move into advanced 2

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Cover image by Mike Garnica and Carlos Hueso, KLA-Tencor

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11 Microeconomics of Metrology, Yield, and Profitability in 300 mm Manufacturing Microeconomic models exist for profitability in the semiconductor manufacturing process, but few include metrology. A new model linking metrology, yield, and profitability shows that despite an increase in metrology cost, a 300 mm fab’s investment in greater metrology capability can pay for itself through higher yields.

reticle technologies. Hence the importance of a reticle automation strategy that provides the necessary reticleisolation technology to protect reticles during transportation and handling.


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300 mm: A Look Forwar d Despite an industry down-turn, 300 mm wafer manufacturing is moving ahead, and this year 300 mm production fabs are coming online. The industry can expect substantial 300 mm growth during the next few years.

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83 Archer 10 Optical system for automated overlay metrology PROLITH 7.0 Lithography simulation software

16 The Challenges of 300 mm CMP Chemical mechanical planarization (CMP) at 300 mm faces not only the traditional 200 mm challenges but also some new ones, including stringent process-control, metrology, automation requirements, the expense of capital equipment (cost of ownership), and tool reliability.

Klarity ProDATA AutoTune™ Auto-calibration analysis for lithography simulation

24 Defect Management for 300 mm and 130 nm Technologies The economic and technical demands of the transition to 300 mm wafers and the ramping of 130 nm generation devices into volume production necessitates not only more stringent inspection and control strategies, but also new ways of inspecting. One method is to mix inspection techniques that traditionally were isolated—such as e-beam and brightfield/darkfield—to create a customized strategy for defect control. 35 Reducing Risk at 300 mm The success of transitioning to 300 mm hinges on minimizing three kinds of risk for manufacturers: investment risk, technical risk, and obsolescence risk. Reducing these risks requires that the equipment supplier and the wafer manufacturer work together and share the burden of process development and assessing equipment capability. This ensures flexibility in processes, enables tool maturity and reliability, and minimizes obsolescence of tools.

Yield Management Solutions is published by KLA-Tencor Corporation. To receive Yield Management Solutions, contact Corporate Communications at:

41 Defect Sample Planning in 300 mm Fabs While the transition to 300 mm offers opportunities for economies of scale, it also brings new yield-management challenges. Defect Sample Planning, if part of a planning process and layout for 300 mm fabs, can help manufacturers achieve the gains they seek as they move to the new wafer size.

KLA-Tencor Corporation 160 Rio Robles San Jose, CA 95134 Tel 408.875.3000 Fax 408.875.4144 www.kla-tencor.com

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Editorial: The Transition to 300 mm—Challenges, Risks and Rewards

23 Yield Management Seminar Series 32 Q & A TSMC’s transition to 300 mm—An Interview with Dr. Nun-Sian Tsai, Senior Director of TSMC’s 300 mm Pilot Line project.

For literature requests, call: 800.450.5308

©2000 KLA-Tencor Corporation. All rights reserved. Material may not be reproduced without permission from KLA-Tencor Corporation. Products in this document are identified by trademarks of their respective companies or organizations.

82 KLA-Tencor Trade Show Calendar

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The Transition to 300 mm Challenges, Risks and Rewards Following several years of an industry-wide effort with billions of dollars of R&D expense, and after an initial false start, the transition to the 300 mm wafer size has finally begun. Currently, one 300 mm pilot line is in production. In addition, recently, two 300 mm pilot lines produced their first chips and plan to move to production in 2001. Furthermore, eight 300 mm pilot fabs have schedules for first silicon in 2001. Overall, there are more than forty announced 300 mm fab plans over the next three years. Interestingly, the recent business slowdown has had little impact on the 300 mm transition. In fact, a number of companies have stated their intentions to continue their 300 mm projects or even move up 300 mm plans. However, some have lowered the initial wafer starts. The transition to 300 mm wafers has coincided with two other major technology transitions, namely, copper/ low-κ interconnect, and 0.13 µm design rules using sub-wavelength lithography. The move to an entirely new interconnect architecture, based on the damascene process with copper wires and low-κ dielectric materials, is designed to enhance the chip performance and reduce cost. This change is accompanied with the introduction of new processes including copper electroplating and copper CMP, leading to new defects such as copper ECD voids, copper CMP dishing and erosions, and microscratches. In lithography, the design rules are far below the wavelength of the laser light source. Sub-wavelength lithography has been made possible with advancements in steppers/scanners, tracks, metrology, reticles and resists. Of particular importance is the implementation of optical extensions such as optical proximity correction (OPC) and phase shift masks (PSM). These transitions require high levels of investment, combined with major innovations, and are accompanied by significant challenges and risks. To reduce the risks of the transition to 300 mm, the industry has initially focused on establishing pilot lines and transferring proven 0.18 µm processes with familiar aluminum interconnect from existing 200 mm manufacturing fabs. The main objectives of these pilot lines include evaluation and verification of process capability and performance readiness 4

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of various tools, understanding of fab automation issues, verification of ROI, identification of gaps, and 300 mm production learning. However, 300 mm fabs are being designed for the subsequent transition to 0.13 µm technology with copper/low-κ interconnect, within the first year of operation. The move to 300 mm wafers is primarily driven by the requirements for lower cost and higher productivity. Larger 300 mm wafers are also suitable for the large die sizes of high value complex products such as SOCs and advanced microprocessors. With approximately 2.25X more area than 200 mm wafers, 300 mm wafers will provide anywhere between 2.2X to 2.5X more die per wafer, leading to an estimated 30% cost reduction per wafer. This expected cost saving is based on several key assumptions including 300 mm/200 mm silicon wafer cost ratio of approximately 3.7X, and 300 mm/200 mm equipment cost ratio of approximately 1.3X. Currently, industry data indicates a wafer cost ratio of 6X to 8X and equipment cost ratio of 1.5X. Although the wafer cost is expected to reduce over the next few years, equipment costs will actually increase with time. It should also be noted that, due to insufficient infrastructure investment, in the interim, silicon supply and cost are of concern. The key question is how can the expected 30% cost reduction target be achieved? Among factors impacting the cost, yield and yield learning rate are important components of the cost equation. Clearly, to achieve the wafer cost reduction goal, the yield of 300 mm wafers should be higher than the earlier targets. In addition, accelerated yield learning is now more important than ever. Rapid timeto-information, as a result of accelerated yield learning, leads to rapid time-to-yield, time-to-volume and timeto-market. All these factors in turn directly contribute to lower cost, a better margin, and a higher return on investment. The cost of operating a typical, leadingedge, high volume 300 mm fab is estimated to be over $100,000 per hour. This clearly indicates that the return on investment as a result of higher yields, accelerated yield learning, and faster yield ramp could amount to tens and even hundreds of millions of dollars.


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Advanced yield management and process control systems and methodologies are essential for enabling accelerated yield learning, rapid yield ramp and fast production ramp, as well as reducing the percentage of materials-at-risk in 300 mm fabs. Due to narrower process windows, 300 mm technology will be primarily impacted by systematic defects and faults. Higher value, 300 mm wafers require increased sampling per wafer to cover the larger sample area, to identify spatial yield problems, and to detect and reduce cost of excursions. As a result, proper 300 mm fab diagnostics planning and 300 mm sampling plan optimization provide significant cost savings and productivity improvements. To handle heavy FOUPs containing expensive 300 mm wafers and to enhance fab productivity, fabwide automation is an essential operational necessity. Therefore, factory automation solutions, including advanced process control, and guaranteed software integration and connectivity are key requirements. In fully automated 300 mm manufacturing fabs, “information flow” and “product flow” will effectively merge. This trend presents a unique opportunity for implementation of an integrated yield management and process control system. Clearly, yield and process control are important challenges for new 300 mm fabs. To address these challenges and to minimize the risks, a comprehensive set of value-added 300 mm defect and parametric control tools and solutions are required. Capabilities provided by these solutions should include leading-edge, high sensitivity inspection and metrology tools together with yield analysis and correlation software solutions that not only address 0.13 µm design rules challenges, but are also extendible to 0.10 µm design rules. In addition, 0.13 µm sub-wavelength lithography module solutions, and copper/low k module solutions are needed in order to facilitate process technology transitions. Furthermore, suppliers need to provide 300 mm expertise, best known methods, and optimized 300 mm recipes through experienced applications and solution engineers. The increased presence of tools and solutions suppliers in 300 mm fabs, as well as providing increased support to customers on 300 mm learning, are critical factors for reducing the risks of the transition to 300 mm wafers. In particular, yield management support in 200 mm to 300 mm process transfer, fab start-up, and fab ramp management is critical for success. The semiconductor industry is going through an unprecedented transformation. The 300 mm wafer fabs of the future will be significantly different from what we know today. Companies and manufacturers that are capable of meeting the challenges of these technology transitions and managing the risks will be rewarded with a stronger business and a successful path to the future.

E DITOR-IN-CHIEF Uma Subramaniam M ANAGING EDITOR Siiri Tuckwood C ONTRIBUTING EDITORS Aparjot Dehal Dave Hattorimanabe ART DIRECTOR AND P RODUCTION MANAGER Carlos Hueso D E S I G N C O N S U LTA N T Michael Garnica C I R C U L AT I O N M A N A G E R Rolando Gonzalez

KLA-Tencor Worldwide C O R P O R AT E H E A D Q U A RT E R S

KLA-Tencor Corporation 160 Rio Robles San Jose, California 95134 408.875.3000 I N T E R N AT I O N A L O F F I C E S

KLA-Tencor France SARL Evry Cedex, France 33 16 936 6969 KLA-Tencor GmbH Munich, Germany 49 89 8902 170 KLA-Tencor (Israel) Corporation Migdal Ha’Emek, Israel 972 6 6449449 KLA-Tencor Japan Ltd. Yokohama, Japan 81 45 335 8200 KLA-Tencor Korea Inc. Seoul, Korea 822 41 50552 KLA-Tencor (Malaysia) Sdn. Bhd. Johor Bahru, Malaysia 607 557 1946 KLA-Tencor (Singapore) Pte. Ltd. Singapore 65 782 6788

Bijan Moslehi, Ph.D. Vice President 300 mm Process Module Control Solutions Spring 2001

KLA-Tencor Taiwan Branch Hsinchu, Taiwan 886 35 335163 KLA-Tencor Limited Wokingham, United Kingdom 44 118 936 5700

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300 mm: A Look Forward by Dean W. Freeman, Principal Analyst, Klaus-Dieter Rinnen, Director and Chief Analyst, Gartner DataQuest

The 300-mm era is beginning to emerge as the industry moves into a new millennium. After an aggressive start and a near stop due to an industry slowdown, 300-mm production fabs are scheduled to come on line in the year 2001. It is anticipated that the growth of 300-mm semiconductor equipment shipments will be strong over the next five years, growing from approx imately five percent of the total semiconductor equipment shipments in the year 2000 to over 60 percent of the total shipments in 2005. While this seems like strong rapid growth, it fits the industry growth curves for the introduction of the nextgeneration wafer size for both equipment sales and the percentage of 300-mm wafers of the total silicon. While this seems like strong rapid growth, it fits within the historical industry growth curves for the introduction of the next generation wafer size and growth of semiconductor equipment sales. It is unlikely that the first phase of 300-mm growth will be affected.

Introduction

The industry has been anticipating the first 300-mm production fabs for nearly three years. The initial estimated dates of first silicon in mass production in the 1998 time frame have given way to a more gradual introduction that has the first production fabs set to come on line in 2001. While this delay has been frustrating to some, it has enabled the industry to develop a more robust set of 300-mm equipment, which might actually accelerate the ramp of 300mm fabs. In previous introductions of wafer sizes one semiconductor manufacturer typically championed the work. At 150 mm, Intel championed the work, while at 200 mm, IBM lead the way. These manufacturers suffered through the immaturity of early tool sets and shouldered a significant portion of much of the development cost for the new equipment sets. At 300 mm, a much different model developed. Several industrial consortiums emerged. Sematech, I300I, and Selete were the proving grounds for the new 300-mm equipment, developing standards, and moving the product development stage from the fabs to the consortiums. The semiconductor manufacturers did 6

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not provide the capital for the development of the new tool sets; instead, they placed the burden upon the semiconductor equipment makers. This model, along with some other factors such as linewidth shrinks and industry slowdown, has produced a much more mature equipment set than the industry experienced at 150 mm and 200 mm. In some cases, the overall equipment effectiveness (OEE) already exceeds that of the 200-mm tool set. This mature tool set has enabled some of the early pilot lines to come on line almost as quickly as they would have with a 200-mm tool set, with reported yields of 300 mm comparable to that of a 200-mm fab line. Economics

An article cannot be written on the business aspects of 300 mm without discussing the increased area of the 300-mm wafer, as well as the potential for increased die output. The well-publicized 2.25 area increase can yield greater than 2.25 times the number of die produced per wafer, thus producing greater than a 125 percent increase in die output per wafer. If we make a simple extrapolation, we can observe in Figure 1 that a 300-mm fab needs only 50 percent of the wafer starts of a 200-mm fab to achieve an equivalent output of die each month. Therefore, some of the 300 mm 5,000 wafer starts per month pilot lines that are coming on line have the capability of producing the equivalent of greater than 10,000 200-mm wafers each month.


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F i g u re 1: Il lust rates the n umber of 300 mm wafers star ts and the equivalent 200 mm wa fer star t s . F i g u re 3: Wafer demand by 2005.

300-mm production costs at 0.13 µm are currently estimated between 70 to 80 percent higher per wafer than for 200-mm wafers, based upon Sematech numbers. Using a die size of approximately 115 mm2, one could expect a cost reduction in the range of 24 percent per die with equivalent yields to that of a 200-mm fab. The cost reduction per die tied together with the potential for much greater capacity is a very compelling reason to move to 300-mm production. This might result in a reduction in the 200 mm fabs projected to start up in the next few years; however, each fab decision is dependent upon the company’s economic situation and whether or not the firm can afford the capital needed to build a 300 mm facility. Figure 2 below illustrates the wafer generation life cycle. At this point in time it appears that the 300-mm régime will follow 200 mm by about 10 to 12 years,

with 300 mm use peaking in the 2012 time frame. While the industry is just starting on 300-mm production, based upon this curve, it is time to begin considering the move to the next wafer size. The question of the next-generation wafer size should be answered by the industry in the next three to five years. Figures 3 and 4 illustrate a more near-term view of the anticipated 300-mm silicon production through 2005. Silicon demand for 300 mm wafers is expected to grow at a compounded annual growth rate (CAGR) of more than 80 percent from 2000 through 2005. By 2005 it is expected that 300-mm wafers will make up over 17 percent of the wafers shipped to the semiconductor manufacturers. With the influence of 300 mm, silicon will grow at a CAGR of 11.1 percent for total MSI of silicon over the

F i g u re 2: Waf er generation life cycle. Wafer si ze den otes when peak usage i s expected .

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F i g u re 5. 300 mm equip ment as a perc entage of tot al semic onduct or F i g u re 4: 300-mm fabs scheduled to come on line, 1998 through 2002.

1999–2005 time frame. The bulk of this growth can be attributed to the 300-mm wafers. This is estimated to be approximately 13.6 million 300-mm wafers in 2005. Wafer Fab Equipment

The current fab count for 300 mm shows three fabs in calendar year 2000, one production and two pilot line. In 2001, eight fabs are scheduled to begin production, two pilot lines and six production fabs. In the year 2002, there are currently 14 fabs scheduled to begin production. There is a high probability that not all of the 2002 fabs will be completed, as the industry is predicted to be entering a slowdown due to excess capacity. There is a good probability that some of these fabs will be built as shells, ready to be completed during the next industry up cycle. In calendar year 2000 it is estimated that 300-mm spending reached approximately $ 2 billion or about six percent of the total spent on semiconductor equipment. In 2001 this number is projected to rise to 17 percent of the total spent on semiconductor equipment rising to between $ 6-6.5 billion. In the year 2005, it is estimated that 300-mm spending will be 65 percent of semiconductor equipment spending, or close to $ 36 billion dollars. While slowdowns in capital spending are foreseen in 2001, 300-mm equipment purchases are not likely to be affected. This will be due, in part, to the need for companies to complete their learning curves and move into the initial production runs, as well as be competitively poised for the 300-mm era. However, as the industry moves into 2002 and early 2003, 300-mm sales will be affected if the industry moves into over capacity. As the industry moves forward into the next upturn, 8

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equi pmen t s ales .

300 mm will be the predominent wafer size driving the industry forward as the demand for devices return. While 300-mm equipment requirements will be spread across all equipment segments, there are several segments in which 300-mm will have greater impact. Factory automation and process control are two very obvious beneficiaries. Factory automation hardware benefits from the difficulty in manually handling 300-mm substrates. Factory automation software should also grow as the drive to make the large capital investments more efficient gains momentum. Process control will benefit from the need to have greater, on-board integrated measurement capabilities and the need for closed-loop process feedback to protect the increased value of the 300-mm wafers. Most 300-mm capacity should be designated for 0.13 µm production. Copper low- κ tools and their associated metrology segments will see increased growth as this technology node emerges. Summary

The industry is moving rapidly into the 300-mm era. By the year 2005, 17 percent of the total silicon manufactured and 60 percent of the capital spent on semiconductor equipment will be allocated for 300 mm. Process control, factory automation, as well as processes critical to 0.13 µm technology, will benefit as a result of 300 mm wafer fabrication. The speed at which 300 mm will be implemented will continue to be driven by the economics of wafer processing and the need for increased wafer start capacity. 300 mm investments should not be affected in 2001 by the current industry downturn while the industry moves through its initial 300-mm production learning phase. As the industry moves out of the current slowdown, 300-mm investment should lead the way into the next cycle.


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M i c roeconomics of M e t ro l o g y, Yield, and P rofitability in 300 mm Manufacturing K. M. Monahan, Ph.D., A. Chatterjee, and G. Falessi, KLA-Tencor Corporation

Simple microeconomic models that directly link metrology, yield, and profitability are rare or non-existent. In this article, we introduce and validate such a model. Using a small number of input parameters, we explain current yield management practices in 200 mm factories. The model is then used to extrapolate requirements for 300 mm factories, including the impact of simultaneous technology transitions to 130 nm design rules, copper interconnect, and integrated metrology. We show that the dramatic increase in value per wafer at the 300 mm transition becomes a driver for increasing metrology capability, despite a concomitant increase in cost. As expected, the model results are strongly dependent on product type (memory, chipset, or microprocessor) and process maturity. Introduction

In this work, we use a simplified microeconomic model for the profitability (i.e., profit per unit of time) generated by the semiconductor manufacturing process1. Let

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where R is the factory overhead rate, W is the number of wafer starts, T is the time interval, Y is the metrology-limited yield entitlement, y is the overall device yield expressed as the fraction of good dies per wafer out, d is the number of dies per wafer, b is the bin yield expressed the fraction of good dies in each performance bin, p is the average selling price per die, C is the manufacturing cost per wafer, i is the product index, and j is the binning index. This business model represents the gross rate of profit attributable to a factory. It does not include variable costs associated with packaging, marketing, or sales of the product. Some of the basic strategies for maximizing gross profit are discussed below. The first term represents the fixed costs associated with capital investment, operation, and depreciation of the facility that are independent of capacity Spring 2001

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utilization. For 300 mm manufacturing, this investment might include 300 mm factory automation, 130 nm pattern transfer technology, copper/low-κ interconnect capability, and factory-wide metrology integration. In the above model, 300 mm factories would be losing significant amounts of money before processing a single wafer. The traditional strategy for minimizing the relative contribution of fixed costs is to reduce manufacturing cycle time and operate near maximum capacity. In a supplylimited environment, this means filling the factory with the highest margin products. In a demand-limited environment, this may require loading the factory with some lower margin products. The latter strategy reduces average margins, but may improve the ratio of profitability to capital investment. The second term in the profitability equation above represents the rateof-profit, adjusted for manufacturing cost per wafer. This variable cost arises from materials, consumables, and other expenses that scale with the number of wafers processed. Offsetting this cost is the factory revenue, which is calculated from the average selling price per die, scaled by dies per wafer, wafer-starts, metrology-limited yield, device yield, and bin yield. Using these input parameters, we develop a heuristic model for metrology and sampling that can help to define strategy for ramping yield in development and for continuously improving baseline yield in production. We have discussed the methodology for containing yield excursions in previous work 2.

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“top-line” revenue. Defect metrology tools, on the other hand, recover value by increasing yield without increasing costs (C), other than those associated with the metrology itself (c). In this sense, the benefits of metrology go directly to the “bottom-line” profitability of the semiconductor manufacturing enterprise. We have shown previously that metrology in the factory should be optimized using stochastic models2. However, the dynamics of metrology, yield, and profitability in the factory are best understood using heuristic response models that are chosen to fit the results of more rigorous stochastic models or, in some cases, actual factory data. For the single-product response model, we make the simple assumption that, starting at 1-y0, killer defects decline by the same fraction with each cycle of learning n, so that the effectiveness of learning declines exponentially. The incremental cost c due to metrology is assumed to scale linearly with the number of cycles of learning, in accord with COO models. If the capability and cost of metrology scale with and , respectively, then substituting into the equation for profitability gives us an expression for the value recovered by metrology: ∆VALUE = (1–y0)(1–e-n )–

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In the limit where the metrologylimited yield entitlement approaches unity, the value recovered is just the improvement in the gross margin of the product. The number of cycles of learning required to reach peak profitability is given by

Metrology, yield, and profitability

Process tools add value by generating output (W/T) at a given level of yield, thereby contributing to the

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We can make a number of qualitative observations with regard to metrology-driven yield improvement, some of which are highly intuitive: • In development, where starting yields are low, the need for metrology is high for all products. Within a single process generation, the optimal allocation of metrology resources is time-dependent. • In production, high value per wafer and relatively low transfer yield increases the need for metrology (microprocessor). Within a process generation, the optimal allocation of metrology resources is product-dependent. • If metrology capability and cost are scaled proportionately (i.e., if is constant), the design of next-generation metrology tools (N+1 and N+2) will be dominated by the requirement for capability. The negative impact of cost on value recovery is greatest when the expected revenue per wafer is low (memory). • Value recovery is greatest when metrology tools are fast (low ), sensitive (high ), and responsive to all yield-limiting defect types (high Y). In virtually all cases, these are conflicting requirements that argue for multiple-tool metrology solutions. Development cycle time is reduced, yield ramps are steeper, and yield entitlements are higher. Results and discussions

In Figures 1-3, the value-recovery model shows gross margin improvement (Y=1) for two virtual products: commodity memory and highend microprocessors. These products are assumed to have ASPs of $5 and $500 per die, respectively. The


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F i g u re 1. Commodity memory — 200 mm wafers.

F i g u r e 2. Commod ity memor y - 300 mm wafers.

F i g u re 3. $500 micro p roc essor - 300 mm wafers.

respective densities are 2000 and 500 dies per 300 mm wafer. Development yields are assumed to start at zero, while production yields at transfer are scaled to account for chip size and product complexity. Metrology capability and cost are estimated for both current (N+0) and future (N+2) generations of metrology

In the case of high-volume production, the model results are strongly differentiated by product type. For commodity memory on 200 mm wafers (Figure 1), the achievable yield is limited primarily by cost. In the case of commodity memory on 300 mm wafers (Figure 2), the additional value per wafer justifies a higher level of metrology (e.g., N+2), resulting in faster baseline yield improvement and a higher yield entitlement (nearly two percent higher in this case). Larger gains will occur as commodity memory manufacturers migrate to embedded logic, DSP manufacturers develop system-onchip products, and microprocessor companies compete for the highestASP market segments. Due to higher average selling price, larger chip size, and lower transfer yield, the economic model for microprocessors is strikingly different. Substantial investment in advanced metrology capability may be justified well into high-volume production. Microprocessor margins are extremely sensitive to metrology capability and relatively insensitive to cost (Figure 3). Taken as a whole, this analysis brings up some significant economic issues: • Assuming optimized metrology capability, 300 mm factories should enjoy not only economies of scale but also higher yields and gross margins. This creates an opportunity for the larger silicon foundries and a threat for smaller semiconductor manufacturers that cannot afford to build 300 mm factories. • In the case where multiple products are manufactured using a Spring 2001

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similar process, monitor reduction strategies intended for the lowest-value products can lead to unacceptable economic risk. Ideally, sample plans should increase for high-value products manufactured on 300 mm wafers. • In the case where multiple factories are equipped identically (copy exact), the benefits of metrology innovation may never be realized, severely limiting the ultimate yield entitlement. Ideally, 300 mm factories should be designed to support seamless upgrades of existing metrology equipment and the introduction of newer metrology tools, with minimal disruption to the process and material flow (copy smart). Given a supply-limited labor market, these introductions may require remote e-diagnostics, e-applications, and e-training for both metrology and process tools3. Multiple tool solutions

Our models generally support multiple-tool solutions for the optimization of yield and profitability. Most copper lines, for example, use a combination of darkfield, brightfield, and e-beam wafer inspection to accelerate yield ramps. With the further segmentation of metrology tools into stand-alone, clustered, integrated, and in-situ systems, the optimal metrology strategy seems less clear, until we consider the economic impact of these technologies. Consider the case of integrated metrology. We assume that these systems will have lower sensitivity, respond to fewer defect types, but enjoy higher sampling rate in comparison with traditional stand-alone line monitors. The value-recovery calculations for production of microprocessors and commodity memory

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F i g u re 4. Integrated metro logy — mi crop ro c e s s o r.

F i g u re 7. Calibrated model — di verging yiel ds.

F i g u re 5. Integrated metro logy — co mmodity

cially for memory products during volume ramp, since these tools are “blind” to a large fraction of killer defects. As a result, factories would not achieve entitlement margins and would risk exposure to nonroot-causable yield excursions.

analysis. This “use-case” scenario illustrates a more general trend toward complete process-module control solutions that include multiple metrology tools 4, networked analysis software, and optimized yield strategies.

• In a supply-limited market, silicon foundries that currently enjoy a “wafers-out” business model, are likely adopters of integrated metrology. However, in a demandlimited market, foundries that do not acquire the most capable metrology tools, will lose customers to foundries with efficient “dies-out” business models or “wafers-out” business models with predictable yield boundaries. Yield prediction is critical to meeting production requirements without creating excess inventory.

The normalized copper yield ramps of several leading-edge semiconductor companies are shown in Figure 6. In Figure 7, we use some of this data to calibrate our microeconomic model, thereby enabling a root-cause analysis of the yield divergence between Companies A and F. By fit-

m e m o r y.

are shown in Figures 4 and 5. In this example, transfer yields start at 0.60 and 0.90, respectively. Based on results for integrated, line-monitor, and combined solutions, we can make qualitative observations about the use of integrated metrology for improvement of baseline yield: • In the case of microprocessors, integrated metrology appears to enhance the effectiveness of more sensitive, stand-alone line monitors by freeing them for more demanding applications. The wafer-to-wafer sampling capability of integrated tools reduces exposure to gross yield excursions. • The use of integrated metrology as a “single-tool” solution creates unacceptable economic risk, espe14

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Copper pilot lines provide another example of success with multipletool solutions. Most copper lines use a combination of darkfield, brightfield, and e-beam wafer inspection for tool monitors, station monitors, line monitors, and engineering

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F i g u re 7. Calibrated model — diverging yields.


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• Finally, we have shown that success in copper yield ramps is critically dependent on both metrology capability ( high αY) and metrology capacity (high n) References 1 . K. Monahan, et al., “Accelerated yield learning in aggressive lithography”, Proc. SPIE 3998, p. 492 (2000). 2 . R. Williams, et al., “Optimized sample planning for wafer defect inspection”, Proc. ISSM’99, p. 43 (1999). 3 . M. Locy, “On-line diagnostics as a key part of process module contro l ” , P roc. ISSM 2000. 4 C. Hayzelden, et al., “Process module control for low-k interlevel dielectrics”, Proc. ISSM 2000.

F i g u re 8. Increasin g Cu c apability—e-bea m in spection.

ting the model first to Company-F data and then forcing it to achieve Company-A yield levels, we identified the likely causes of divergence. The model parameters indicated that Company A had newer, more capable metrology tools and significantly greater capacity. An audit of the metrology tools in each company confirmed these results. Adding metrology capability goes beyond upgrading or replacing older optical tools. One extension of metrology capability that is now common in copper pilot lines is e-beam wafer inspection. E-beam inspection technology is not only more sensitive to many physical defect types (Figure 8) but is also uniquely responsive to new classes of buried electrical defects (e.g., voids and incomplete vias) that are frequently observed in the copper damascene process. As a consequence, e-beam inspection increases the aggregate metrology capability (αY), enabling shorter development cycle-times, accelerated yield learning, and higher yield entitlements.

Conclusions

In this work, we have introduced a simple microeconomic model that links metrology, yield, and profitability in semiconductor manufacturing. These are our findings: • The dramatic increase in value per wafer at 300 mm justifies an increase in metrology capability, despite a concomitant increase in metrology cost • Value recovery by metrology depends strongly on process maturity, product type, metrology capacity, and metrology tool generation • Our model strongly supports optimized, multiple-tool solutions for improvement of yield and profitability • For example, integrated monitors can enhance the effectiveness of stand-alone monitors but are generally not viable as the sole metrology solution in a factory

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To be published in the Proceedings of ISSM 2000, September 26-28, 2000, Tokyo, Japan. About the Author Dr. Kevin Monahan is VP of Parametric Solutions in the Customer Group of KLA-Tencor Corporation. He is currently working on factory-wide, high-volume engineering solutions for the control of photo and etch process modules. Kevin has held a variety of positions within KLA-Tencor, including VP of Technology in a Strategic Business Unit and Director of Strategic Marketing in the E-Beam Metrology Division. Dr. Monahan is known as the founder of the SPIE Conference on Metrology, Inspection, and Process Control; former CTO of Metrologix, Incorporated; and editor of the Handbook of Critical Dimension Metrology and Process Control. He holds a BS in physics from the California Institute of Technology and a Ph.D. in physics from the University of California. He has published more than 100 business and technical papers.

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The Challenges of 300 mm CMP Brian Stephenson, Ebara Technologies Inc.

The transition from 200 mm to 300 mm presents many challenges for semiconductor manufacturers throughout the entire processing flow. From raw silicon to packaging operations, processes and processing equipment must meet the strictest speci fications at ever increasing chip complexity and shrinking design rules. Throw in rapid moves to advanced technologies such as low- dielectric and copper metallization converging at the same time, and the 300 mm transition is even more challenging.

Past transitions from 125 mm to 150 mm, and 150 mm to 200 mm, were considered to be incremental changes, the transition from 150 mm to 200 mm being the most significant as far as equipment goes. For most of these transitions, the industry was not near the processing limits for the linewidths being transitioned. Only recently has IC manufacturing began to push the limits of optical lithography as gate lengths are rapidly dropping below the 0.18 µm level, to 0.13 µm and now sub-0.1 µm levels. Also, front-end and back-end processes and materials have been, up to now, virtually unchanged or experienced relatively slow migration into advancing technologies as the industry transitioned to larger wafer sizes. With the advent of 300 mm, this past model does not appear to be holding any longer. The manufacturers taking the risk now to introduce 300 mm lines are not simply putting in proven, stable technology to ramp up a fab. There appears to be a push to put in the most advanced processes (low-κ, copper, sub-0.13 µm linewidths) at the initial stages to allow faster return on investment: faster chips with higher ASP, and smaller chips on twice the silicon real estate. However, if device and line yields are poor, this strategy is all for naught. Therefore, chipmakers are putting large 16

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pressures on the capital equipment makers to produce equipment with unprecedented levels of integration, process flexibility, automation, and reliability. So, with all of these advanced technologies converging at the 300 mm node, where does that leave CMP? Is it drastically different than the 200 mm processes your familiar with? Well, as it turns out, not really. 300 mm CMP—Is it ready?

The short answer is “yes” with regards to process capabilities. The major CMP players in the market today have demonstrated capability at 300 mm across the board from STI to copper polishing. Companies such as Ebara even have second-generation equipment out in the field being started up in pilot and production lines around the world. So from the process standpoint, there doesn’t appear to be any major hurdles in the transition. However, increasingly tight specifications on uniformity and planarization efficiency will drive further design improvements in 300 mm tools moving forward. This reality, plus a host of new requirements for 300 mm manufacturing equipment, provides the greatest challenges to CMP. Transitioning CMP—The challenges

CMP is already a major process module for most 200 mm manufacturers, with advanced logic manufacturers utilizing CMP for 12 to 15 layers (see Figure 1). For 200 mm, the bulk of CMP is utilized for three process steps: shallow trench isolation, intermetal dielectric


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polish (IMD—usually PETEOS, HDP Oxide, or doped oxide such as PSG or BPSG), and tungsten plug polish. Other processes may include polysilicon polish (usually used in memory manufacturing), tungsten local interconnect polish, and more recently, damascene copper polishing. For 300 mm, all of these processes will be needed, with copper polishing becoming more prevalent.

F i g u re 1. Illustra tive cross-section of 5-level copper metal logic devi ce. Up to 11 diff e ren t CMP p rocess steps wo ul d b e utilized in the c o n s t ruct ion of a devi ce such as this.

Key issues

For 300 mm CMP, the challenges are many. Most of the issues faced in the transition from 200 mm to 300 mm are many of the same issues that CMP continues to face today. Across-wafer uniformity control is one of the primary difficulties with respect to hardware design that doesn’t scale well. Simple scale-up of polishing head design doesn’t guarantee the same performance seen at 200 mm. Typically modification or redesign is required.

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Following are some of the key issues facing 300 mm CMP today. Note that many of these issues are not unique to CMP, but apply to most 300 mm capital equipment in the fab.

Reliability As with previous fab equipment, 300 mm equipment will require improved levels of reliability, especially for CMP. CMP equipment for years has been much maligned for reliability issues. Equipment downtime creates costly disruptions in the production line. With the focus on reducing CoO and increasing ROI in 300 mm, these disruptions become even more undesirable. Other issues, such as wafer breakage, long an issue with most CMP equipment, become unacceptable at 300 mm with not only the value of the lost die on the wafer, but the raw material costs as well. Ever increasing pressure is being applied to CMP equipment makers with respect to reducing wafer scrap and mean time to repair (MTTR), and increasing mean time between failures (MTBF). The main factor for 300 mm reliability right now is simply maturity. Many of the tools in fabs today are still in the alpha or beta phase of development. While some equipment is a scale-up of their 200 mm counterparts, many pieces have been redesigned from the ground up. Larger motors, heavier infrastructure, and beefed-up power distribution mean a lot of new untested parts. Newer, increasingly complicated software designed to meet today’s ergonomic, user-friendly requirements, in addition to expanded host control, means a lot of new software bugs and tool crashes. For the more complex equipment, it will simply take time and effort to work the bugs out of most of these systems. Those companies that kept on the 300 mm course during the pause in the late 90’s are well ahead of the curve with respect to equipment reliability and have worked many of these issues out through extended marathon testing at consortiums such as SC300 and International Sematech.

Polish uniformity control Other issues facing CMP in 300 mm have to do with the increased level of control and automation required. Due to the high costs associated with 300 mm, manufacturers can ill afford the costs of wafer breakage or re-work. Also, yield loss due to process variation, such as post-CMP thickness control, becomes an even more critical issue at larger wafer sizes. If die yields don’t scale, then the advantages of moving to a larger wafer size are lost. The financial toll would be too great to make a successful transition.

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At 300 mm there are two major concerns regarding polish uniformity. One is the polishing head design itself. It is the most critical component in the tool when it comes to polishing uniformity control. In the short term, fabs will require CMP tools that can provide process flexibility with respect to across-wafer profile control. Wafer carriers must be designed to allow polishing profile control across the wafer to compensate for incoming non-uniformity from immature electroplating and dielectric deposition equipment and


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processes. As upstream tools and processes mature, providing better incoming uniformity, the equipment must allow easy process modification to compensate for the changing incoming profiles. Ideally, through the use of in-situ measurement equipment that can determine removal rates across a wafer during polish, the wafer profile can be closed-loop controlled on the fly, mitigating the effects of incoming non-uniformity and polish consumables degradation and variation. Advanced floating head designs, such as floating head or membrane based technologies that have worked extremely well at 200 mm, are having some difficulty transitioning to 300 mm. Machining tolerances are more critical. Doubling the wafer area doubles the frictional forces between the pad and wafer surfaces. The resultant torque produced by these frictional forces can induce unwanted vibrations and uneven pressure distribution. Carriers with configurable pressure profiles will be a necessity for long-term, stable processes at 300 mm. Another early concern was that slurry transport would be an issue at the larger wafer size, starving the center of the wafer for slurry, creating large center-to-edge uniformity issues. However, this has turned out to be not much of an issue as a result of advanced pad grooving techniques and newer wafer carrier designs. Uniformity on oxide <3 percent (1 sigma) @ 3 mm edge exclusion can be achieved using conventional slurries and pads used for 200 mm processes. For conventional slurries, slurry transport does not seem to be a major issue with regards to uniformity.

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when they do occur will become more important, driving the industry to on-board inline defect inspection equipment to detect major defect events such as scratching or incomplete metal removal. In-line defect inspection allows real-time, wafer-bywafer characterization of defect performance of a tool. Given shutdown criteria, the equipment can shut itself down if defects go out of control. This reduces equipment downtime for process monitoring and reduces the fabâ&#x20AC;&#x2122;s scrap exposure in the event of a defect occurrence that could have affected several lots of wafers. Again, these items tie into the theme of aggressive cost reductions for 300 mm by eliminating scrap and enforcing strict process controls which translate into increased line and die yields.

Endpoint, In-line Thickness Metrology (ITM), and Closed Loop Process Control (CLC) Process control for all CMP processes becomes more critical at 300 mm. Losses due to overpolish, underpolish, or missed endpoints at metal polish cannot be tolerated at 300 mm. Figure 2 shows a schematic of an advanced polisher with in-situ sensors and measurement systems. Process sensors that can measure thickness and reflectance across the wafer during polishing are becoming a necessity.

Defectivity Not only does slurry have to be well distributed underneath the wafer for consistent polishing performance, the waste products from the polishing have to get out from underneath the wafer surface. If these products are trapped due to waste transport issues, defectivity problems can surface. Also, if the equipment is not designed to keep pad and wafer carrier well cleaned between wafers, buildup can occur that can lead to scratching issues. With the larger platen sizes at 300 mm, this is made more difficult. Again, with modern pad grooving designs and proper design of pad cleansing/ conditioning components, this does not appear to pose a major issue. For 300 mm, there does not appear to be any major concerns with defectivity above and beyond what is already faced at 200 mm. However, the ability to quickly and accurately detect and react to defect excursions 20

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F i g u re 2. 300 mm CMP tool wi th integra ted cleaning and vari ous o n - b o a rd process sensor s a nd metro l o g y.

For STI and oxide processes, timed polishes are no longer acceptable. Accurate endpointing systems based


Annihilate.

To get your free copy of

With every technology transition, a new army of deadly defects goes on the

"The Art of Defect War"

attack. Their target: your fab’s yield, and its profits. Which means that more than

please visit www.kla-tencor.com.

ever, you need to understand the enemy. Utilize sophisticated new weaponry. And deploy unique, customized attack strategies. All of which you’ll find in our newest publication, "The Art of Defect War." Be sure to get your free copy today. In the battle to control new technologies, it’ll be your secret codebook. ©2001 KLA-Tencor Corporation. Please allow 3-4 weeks for delivery.

Accelerating Yield


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host software control. Because of the strict yield requirements, reduction of human interaction, ergo human error, is paramount to increasing line yields. Recipe control, data collection, error reporting, remote diagnostics, and interfacing with yield-management tools are all examples of the significantly increased requirements out of the gate for the 300 mm equipment set.

Cost Of Ownership F i g u re 3. Potential gain in dishing and erosio n p er f o rman ce b y re d u c ing amount of over polish re q u i red with an accurate endpoint system .

on film thickness measurements are currently being developed and tested. For metal polishing, accurate endpointing, when the wafer is fully clear of bulk metal, is critical in reducing required overpolish. Figure 3 shows the impact of overpolish on dishing and erosion in copper polishing. An accurate endpoint system, allowing endpoint to be called as close to true endpoint as possible, is critical to reducing dishing and erosion to acceptable levels in metal and shallow trench CMP applications.

The cost of 300 mm capital equipment is very high. Therefore another key issue facing equipment manufacturers and fab managers alike is reducing cost of ownership. For CMP, this means pushing to reduce power and water usage, extending consumable lifetimes, and implementing advanced technologies such as fixed or bonded abrasives and slurriless CMP. Other areas of focus are increasing throughput and reliability while at the same time reducing footprint. Most first-generation 300 mm equipment has unoptimized (large) footprints, mainly due to pressures from shortened engineering schedules due to the rapid turn-on of 300 mm activity after a â&#x20AC;&#x153;breakâ&#x20AC;? in the late 1990â&#x20AC;&#x2122;s. These items, while not new to CMP, become requirements (as opposed to options in the past). Summary

In-situ thickness metrology (ITM) provides the capability to pre- and post-read dielectric thickness for closed-loop process control within the CMP process, as well as providing feed-forward capabilities to downstream processes. For example, as we push the limits of photolithography and dielectric etching, film thickness control becomes more critical for the stability of these downstream processes. Knowing film thickness on a per-wafer basis prior to processing can allow on-the-fly process adjustments to improve the process window of these steps. Since CMP requires much of the same information for its own process control, ITM makes it convenient for providing this data.

Automation At 300 mm, automation hits a supercritical stage. Most fabs that make the switch to 300 mm are requiring 100 percent of their equipment set to be enabled for

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The news is not that bad for CMP at 300 mm with regards to process. Most of the process learning from 200 mm will transfer with relative ease to 300 mm. Concerns of slurry transport issues and major non-uniformity problems have not been realized. Uniformity on oxide <3 percent (1 sigma) @ 3 mm edge exclusion can be achieved using conventional slurries and pads used for 200 mm processes. So, for the fab beginning the process toward 300 mm, consumable sets established for 200 mm CMP should transfer with only minor process optimization, reducing risk for their pilot and production lines. The main issues for CMP, which will be more challenging to resolve, are muchimproved reliability through reliable hardware design, more advanced process controls utilizing in-situ sensors, metrology and automation, and further reduction of CoO through reduced utilities usage and advanced CMP technologies such as fixed abrasive or slurriless CMP.


Yield Management Seminar A valuable venue for innovative ideas KLA-Tencor’s Yield Management Seminars (YMS) focus on value-added, integrated process module control solutions for defect reduction, process parametric control and yield management. Key topics include navigating the transition to the 0.13 µm technology node, with special emphasis on copper/low κ interconnect, sub-wavelength lithography, and the 300 mm wafer. To register online for the upcoming YMS, please visit us at: http://www.kla-tencor.com/seminar Date: Time: Location:

Wednesday, April 25, 2001 9:00 am – 6:30 pm Hotel Bayericherkof, Munich, Germany

For information on future YMS, please complete and return the enclosed business reply card.

Call for future papers Papers should focus on using KLA-Tencor tools and solutions to enhance yield through increased productivity and performance. If you are interested in presenting a paper at one of our upcoming yield management seminars, please submit a one-page abstract to: Cathy Silva by fax at (408) 875-4144 or email at cathy.silva@kla-tencor.com.

YMS at a Glance DATE

LOCATION

April 25

Munich, Germany

July 17

San Francisco, California

August (TBD)

Singapore

August (TBD)

Hsinchu, Taiwan

October 17

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Defect Management for 300 mm and 130 nm Technologies Part 1: Advanced Patterned Wafer Inspection Strategies by Paul Marella, Ph.D., KLA-Tencor

The transition to 300-mm wafers and the ramping of 130 nm generation devices into volume production have introduced significant economic and technical challenges for semiconductor manufacturers. In addition to the continuing trend towards using a mix of distinct inspection technologies that can be customized to fit the changing requirements of the fab, revamped defect inspection and control strategies are also required. The first in a three part series, this article explores these new methodologies that include the increasing use of e-beam inspection combined with the application of advanced optical patterned wafer inspection technologies.

Introduction

Industry Trends In the ever-accelerating quest to remain competitive in today’s semiconductor market, manufacturers are turning towards larger wafers of higher capacity, with new process materials and architectures. For the first time in recent memory, the semiconductor industry is witnessing the simultaneous convergence of new process and materials development, shrinking design rules and an increase in wafer size. As one would expect, this places a large constraint on the effectiveness of existing inspection tools and methods that proved to be successful in earlier technology nodes. Shrinking the feature size means less room for error, as evidenced by the requirement of emerging “zero-bias” etch processes. A defect that in previous generations was too small to cause trouble has now become yield-critical. Escalating device complexity places additional constraints on the control required for each process step, and having more process steps translates into the potential for larger accrued error. 24

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In addition to larger wafers and smaller design rules, many leading-edge devices incorporate a new process architecture called copper dual damascene, with high aspect-ratio stacked via and metal structures. These are difficult to etch, difficult to fill, and difficult to inspect for defectivity. New insulating and conducting materials are also part of the challenge: specifically low-κ dielectrics and copper. Requiring new chemistry for deposition, electroplating, and polish, copper devices still lag behind aluminum in yield. 300 mm fabs are expected be more profitable than 200 mm fabs, producing lower cost devices with reduced cycle times and with higher yields. However, replacing 200 mm wafers with 300 mm wafers necessitates automation advances to all process, metrology, and inspection equipment. Recipes that have been optimized for 200-mm production must be transferred smoothly to the 300-mm tools, along with a large body of accumulated knowledge and manufacturing history. With the larger wafer radius, process tolerances have to shrink so that cumulative errors still fall within acceptable limits. Because each wafer contains more die, time-to-volume is an even stronger driver than before. Each individual wafer costs more; hence, a key challenge is accelerating yield learning from development to production.


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Second, economic pressures have acted as the impetus for focusing on earlier systematic defect elimination, solving the defect problems earlier in the product life cycle. These technical challenges earlier have driven a trend towards increased use of SEM-based inspection while still relying heavily on high-sensitivity brightfield inspection in the development and ramp stages. Further, a new trend in process development has been control of defectivity at a specified level in the early stages of technology learning cycles. The goal is to control individual process defectivity in an effort to obtain better correlation of process step-limited yield.

Table 1. Acceler ated f ault learning rates translate into enorm o u s fi nancial gai ns for the 30 0 mm fab.

Add to these technical challenges the economic pressures that ensue with 300 mm fabs costing upwards of $2B, and investors requiring ever-shorter returns on their considerable outlay. Global economic conditions at the start of the new millennium mean that missing the market window by as much as a month may translate to a significant difference on a companyâ&#x20AC;&#x2122;s year-end balance sheetâ&#x20AC;&#x201D;and big differences in the pockets of their shareholders. (Table 1) These numerous and significant challenges require risk mitigation on several fronts. In this series we focus on developing winning defect inspection and control strategies for 300 mm wafers and 130 nm design rules.

Another development is an increase in inspection capacity, a reversal of an earlier drive to reduce capital expenditures on inspection tools, when inspection was perceived largely as a non-value-added expense. As the opportunity cost of lost yield rises in line with the capital cost of the fab, experience has shown that more, not less, inspection is the most cost-effective approach. Thus the industry has seen an increase in inspection capacity, as shown in Table 2 and Figure 1. Finally, increased focus on defect reduction and control in the photolithography area has driven development of new methods, including increased use of automated macro defect inspection, backside inspection, and bright field inspection based photo-cell monitors. This important trend will be explored in more detail in Part 2 of this series.

Defect Inspection Trends For advanced design rules and 300 mm, several trends have appeared in the areas of defect reduction and control. First, time-to-market requirements have created a trend away from using one inspection methodology to detect all defect types throughout the product life cycle. Instead, a mix of brightfield, darkfield, and e-beam inspection has been emerging as the dominant approach. Because of the increasing complexity of the device fabrication processes, a combination solution must be customized to the individual characteristics of the device technology being manufactured. This solution must meet requirements for more complete defect detection, earlier in the process, at lower overall cost of ownership. This trend will be explored in more detail below.

Table 2. Recent data from ICE s hows that expen ditur es on wafer inspection equipment has risen in the transition from 250 nm to 180 nm devices, and from 1 80 nm to 130 n m.

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F i g u re 1. Data from a leading foundry, as they enlarged their inspection cap acity to negotiate a successful tran sition from 25 0/180 nm to 180/150 n m devices. This trend towa rds in crea sing adopti on o f in spection eq uipment has ar isen because its cost can b e jus tified by its re t u rn: faster time to market and hi gher profitability of th e re s u l t i n g devices.

Determining Inspector Mix

Of all the variables that influence a fab’s time to yield, having the right inspection strategy is clearly one of the most important. Effective strategies, tailored to a fab’s unique requirements and applied properly throughout a product life cycle, ensure that issues concerning device yield and reliability are identified early in the process and corrected. As a result, not only can development time be reduced, but also new product and technology transfers can occur faster and at higher yields, accelerating ramp to full volume production. The cornerstone of any inspection strategy is the inspection system itself. The three basic inspection technologies are brightfield, darkfield and e-beam (see sidebars). The objective is to combine these technologies into an overall inspection strategy that delivers the optimum sensitivity/cost of ownership combination for any given application. To sacrifice throughput for unnecessary sensitivity, or to sacrifice needed sensitivity for throughput, would be inefficient and potentially very costly, decisions. (See Figure 2).

F i g u re 2. An op timal production plan has to consider the cost of inspection and the benefi ts of lower ex cursion r ates.

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While combinations of the three main inspection technologies provide the most flexible and cost-effective strategy across all layers in the face of changing inspection requirements, fabs do not want to proliferate more technologies than necessary, with each technology having different matching requirements, automatic defect classification capabilities, recipe set up procedures, etc; a balance must be achieved. To the extent that different technologies share common attributes—such as software for analysis, automatic defect classification (ADC), recipe management, overlay comparison, and matching, as well as diagnostic support—the negatives of multiple inspection technologies can be offset. It is critical that the multiple inspection technologies should be complementary—each should excel in distinct applications, providing the required sensitivity at the lowest cost of ownership for their targeted applications. Multiple technologies provide the maximum range of response to changing inspection requirements. A range of inspection capabilities also provides opportunity for synergy among the various tools, further leveraging the capabilities of each. For example, certain defect types that initially may be detected on a fab’s most sensitive tool during development can later be monitored using a less sensitive but higher throughput tool that has been specifically “trained” to detect them. This reduces the overall cost of inspection, and frees the higher resolution tool for more critical inspection steps requiring its capabilities. It must be noted that this “migration or transfer” to an alternative technology should be based on both cost and utility and not just cost alone. Inspection strategy during development and ramp

As a product progresses through its life cycle, from development through ramp to production, the requirements for inspection also progress (Figure 3). Early in the product life cycle, most defect problems are unpredictable and systematic—particularly when new materials, new processes and/or new device architectures are involved. To move through the development cycle quickly and effectively, inspection equipment must have high sensitivity and high capture of as broad a range of defects as possible. In this phase, the inspector mix will emphasize e-beam and DUV-brightfield inspectors. The fundamental inspection need in this phase is improved “cycles of learning (COL)” to flush out the basic process inadequacies.


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E-beam inspection Unlike brightfield and darkfield optical technologies that measure reflected or scattered light, electron-beam —or e-beam—inspection technologies measure emitted secondary electrons. This gives these tools several key advantages. First, electrons aren’t subject to limits from diffraction, and are therefore able to detect much smaller defects, typically down to as small as 50 nm. The large depth of focus of these tools also enables them to image the bottoms of high aspect ratio trenches and vias, historically a difficult inspection problem. Finally, because electrons carry charge, they can also detect electrical defects, such as failed contacts, using a technique called voltage contrast. No other inspection technology can find electrical defects. This capability alone can make these tools a worthwhile investment. Today fabs typically rely on short-loop experiments lasting one or two weeks to determine electrical defectivity. With an e-beam system, this can be reduced to days or even hours, dramatically accelerating development of new products and technologies. F i g u re 3. Balancin g e-bea m and o ptical inspect ion dur ing the device li fe cycle.

Later, in the transfer and ramp phase, the goal is to reach yield entitlement in the shortest amount of time. More and faster yield learning cycles are critical, and high throughput darkfield inspection tools can help accelerate yield learning in applications where they have the required sensitivity. In the transfer and ramp phase, a mix of the three technologies is typically employed, including brightfield, darkfield and e-beam inspection. The stages of development, transfer and ramp are receiving more attention today because of more stringent requirements for return on investment and narrower market windows for the finished product. During this phase thorough defect characterization is critical, to minimize the probability of encountering unknown defect types during production. In many cases e-beam inspection is the best technology to detect defects in leading-edge devices during development and ramp. The physics of an electron beam provide higher resolution and greater depth of focus than any optical inspection system; thus using e-beam technology for inspection of high aspect ratio (HAR) structures is frequently the most cost-effective choice. These structures are notoriously difficult to pattern and etch, and their topology makes inspecting the bottoms of these structures challenging. Moreover, inspection of HAR structures is a critical requirement for advanced logic and DRAM devices.

The historical disadvantage of e-beam tools has been their slow throughput, which until recently has limited their application to the development fab. However, systems that are up to 100x faster then previous generation tools are now on the market, and as a result they are increasingly finding their way onto the production floor for certain critical applications. Additional speed improvements are on the horizon, potentially revolutionizing the role of these tools in yield acceleration.

E-beam inspection is the only technology that can detect electrical defects during inspection, using its unique voltage-contrast mode. (Figure 4). This makes it indispensable for detection of contact and via 1. Voltage Contrast Detection

2. e-Beam Defect Review

F i g u re 4. HAR defect reduction r e q u i res hig h resolution, material or voltage con trast, and extreme depth of focus. These attr ibutes are commonly as sociated with e-b eam inspection and re v i e w.

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Brightfield Inspection Brightfield inspection systems use a focused beam of broadband or multiple-wavelength light to flood-illuminate the wafer. Analogous to a digital camera taking a photograph, brightfield systems collect reflected light in a high-speed Time Delay Integration (TDI) sensor, where the image is digitized by a small-pixel grid. Multiple images are then compared either die-to-die, or cell-to-repeating-cell to detect differences that may signify defects. Different pixel sizes can be chosen to meet sensitivity and throughput requirements. On-board automatic defect classification (ADC) software quickly classifies defects by type for efficient process monitoring and control. The key to the high performance of these systems is their resolution and contrast, achieved only through high numerical-aperture (NA), small-pixel imaging optics. Cost of ownership requirements are met using massive parallel image processing, which enables high wafer throughput.

problemsâ&#x20AC;&#x201D;which can be significant contributors to product loss, and are a growing yield concern in the manufacture of devices that incorporate copper. A key element for effective use of e-beam inspection in these applications is having appropriate SEM review capability. To take maximum advantage of voltage-contrast inspection, a SEM review system that can employ its own voltage-contrast mode to re-detect the defect is essential. Using coordinates from the inspection, the review SEM can find the defect within a wide field of view, then zoom in for a high-resolution image automatically. In the realm of optical inspection, brightfield systems are widely acknowledged to provide the highest sensitivity and capture of the broadest range of defect types (Figure 5). For this reason they are commonly used in the development phase, where yield issues are first identified and characterized, and control strategies are developed. Once in ramp and production, many of the brightfield inspection layers can be transferred to higher throughput darkfield tools. Recent advances in brightfield systems include adding UV light to the broadband optical source to increase resolution, especially needed for photo and etch applications on 130 nm devices. Further advances in optical noise suppression have enhanced performance on layers with grain or color noise.

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Developer Spot

Microbridge

Metal Bridge on Grainy Layer

Line Thinning

F i g u re 5. Recent adva nces in br ightfiel d technology have ena bled c a p t u re of critical defect types never before captured by optical systems.

Best known methods in development and ramp The goal during the development stage is to capture as many defect types as possible, including unknown defects and any new types that might arise from new materials and processes. Thus the inspection sampling should be dense. Typically all wafers, all levels and all lots are sampled, with a high area of inspection per wafer. Often full-wafer inspections are performed on some wafers in each lot. High-sensitivity inspections are the rule, with e-beam inspection and brightfield inspection carrying most of the load. Their recipes are generally set to small pixels for maximum capture. During development and ramp, defect review is very thorough. The strategy will be modified as the product moves into the ramp phase of its life cycle, and defect problems are largely characterized. Instead of sampling all wafers at high sensitivity, the overall sampling scheme is less dense, with heavy sampling reserved for the critical levels. High sensitivity is still the mode of operation, and review is comprehensive and systematic. The goal is to move through ramp quickly, identifying any remaining problems and solving them before the transition to volume production. During these two phases, killer defect Paretos are under construction; these will comprise the reference Paretos during production.


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Inspection Strategy During Production

When the product moves into production, the major defect problems have been characterized and yield is acceptably high. In this phase, the goal of the inspection strategy is to sustain yields by controlling excursions of known types. To increase productivity, inspection steps are moved to higher throughput tools wherever possible. As a result, the inspection tool mix shifts towards darkfield systems, reserving brightfield and e-beam systems for situations where their unique detection capabilities are absolutely essential. Applications where brightfield still provides the best performance/cost of ownership combination typically include critical etch and lithography applications. In the production phase the e-beam inspector is employed as an auditor, checking for known problems that require its unique capabilities in either sensitivity or voltage contrast. Darkfield inspection has been the dominant technology for many years for monitoring in the film deposition and CMP areas. Recently advances in optics and algorithms have extended darkfield capability, increasing its per-

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Darkfield Inspection Darkfield inspection optics use a laser beam to illuminate the wafer surface at a low angle, thereby minimizing light scatter from the wafer surface and previous layers, and maximizing the scatter from defects and other anomalies. In “double darkfield” systems, the optics that collect the scattered light are also located at a low angle, further suppressing unwanted surface scatter or “noise.” Polarizers, advanced optical enhancements and software algorithms work further to extract the signal from background scatter. Once signals are captured, massive computations isolate defect signals and assign specific x-y coordinates. As with brightfield and e-beam systems, on-board ADC software classifies defects by type. The exact angles at which the illumination and collection optics are placed vary with different implementations of the technology and will affect the overall capabilities of the tool. The noise suppression capabilities of darkfield technology enables high performance on CMP layers as well as rough and transparent films, and recent advances have enabled enhanced capability for inspecting traditionally brightfield layers such as metal etch. The darkfield inspection technology is the throughput leader among the three distinct inspection technologies. For this reason it heavily populates the production areas of the fab.

Photo Deformed Line

CMP Microscratch

formance into etch and photo as well (Figure 6). The key to successful transfer of an inspection step to a higher throughput darkfield system lies in characterizing its ability to capture the yield-limiting defect types detected on the other systems. In many cases today’s darkfield systems can be configured to capture these defect types.

Best known methods for production

Etch Bridging

Embedded Particle in Metal Film

Misaligned Contacts F i g u re 6. Darkfield t echn ology is i deal for capturing many pro d u c t i o n in duced defect types at high t hro u g h p u t .

In the production phase, cost control is paramount. This means adjusting the sampling strategy significantly: the number of levels and percent of lots sampled are reduced, as is the wafer area inspected. For the inspection recipes, the highest sensitivity settings make way for highest throughput, while preserving sensitivity requirements. The lower limit for the sampling frequency is set by the requirement to detect excursions quickly. A mistake that was sometimes made in the past was to underestimate the number of inspection systems required in production. A good estimate for inspection capacity should be refined to account for not only business-as-usual conditions, but also excursions, problem solving and baseline reduction. Managing an excursion includes Spring 2001

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F i g u re 7. Learni ng from line monitoring i s used to optimiz e the tool monitor ing strategy.

process experiments, split lots and increased sampling. These require additional inspection capacity on reserve. While the dominant yield loss mechanism during production is process tool excursions, systematic auditing for known process integration defects (also known as â&#x20AC;&#x153;line monitoringâ&#x20AC;?) complements excursion monitoring to provide the best known method of production defect control. The defect Paretos that were created during development and ramp now form an important reference. The dominant factor in determining an optimal production inspection strategy is to account for the very

important interaction between process tool excursion monitoring and process integration (line) monitoring. The technology used for excursion monitoring must be able to incorporate the learning obtained from line monitoring (Figure 7â&#x20AC;&#x201D;Optimal Production Planning). It is essential for tool monitoring inspectors to have the sensitivity and flexibility to take advantage of this learning.) This is one reason why integrated inspection techniques have not been implemented to date. The candidate technologies for integration to process tools have not shown the capability to capture more than very gross excursions, making the necessary interaction with line monitoring impossible. Integration will become viable when the integrated inspection technology has the sensitivity and flexibility to support this interaction at the 130 nm node. Summary and Conclusions

Tabl e 3. Deployment of a comb in ation of brightfield , d arkf ield , and e-beam in sp ection in the ini tial development phase.

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In reviewing the inspection strategies of several leading logic, memory and foundry IC manufacturers, an internal study by KLA-Tencor found that all have adopted a combination of brightfield, darkfield and e-beam inspection systems. The exact mix and match strategy varies from fab to fab depending on its unique requirements. Table 3 shows the inspection strategy of these leading IC manufacturers in the initial development phase.


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Economic and technical challenges are significant in the transition to production of 130 nm devices on 300 mm wafers. New materials, new architectures and more stringent process tolerances have combined with tighter market windows and more demand for faster return on investment. Defect reduction and control trends have emerged to address these challenges. These include: • Revising the deliverables of process development goals during early technology learning to include reduced defectivity • More focus on early, systematic defect reduction leveraging a mix of distinct brightfield, darkfield and e-beam inspection technologies that can respond to the changing requirements of the fab

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• Increasing fractional expenditure on wafer inspection technologies • More focus on defectivity in the photolithography area The current review is the first in a series of articles that will be published to comprehensively discuss defect control strategies. An optimized strategy needs to include the right technology choice, detection best practice and the subsequent analysis of the data to derive their benefits. This article has focused on utilizing a mix of inspection technologies to meet economic and technical demands. In a subsequent article, we will discuss the analysis methodology that enhances the effectiveness of this defect inspection strategy.

• Increasing use of e-beam inspection to address requirements for additional sensitivity and inspection of high aspect ratio structures

Take the guesswork out of simulation! Chris Mack

www.kla-tencor.com/prolith7


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TSMC’s T ransition to 300 mm

An Interview with Dr. Nun-Sian Tsai, Senior Director of TSMC’s 300 mm Pilot Line Project Dr. Nun-Sian (NS) Tsai is senior director of TSMC’s 300 mm pilot line project. Dr. Tsai joined TSMC in 1989 as an R&D manager. He then went on to hold various positions at TSMC, including Fab 1 fab director and Fab 4 fab director. From 1997 to 1999 he was vice president of operations at Vanguard International Semiconductor Corporation, a TSMC-affiliated company. Prior to joining TSMC, Dr. Tsai worked for AT&T Bell Laboratories from 1983 to 1989. He obtained a Ph.D. in materials science from M.I.T. in 1983.

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What are the primary reasons and main drivers behind your decision to move to the 300 mm wafer size?

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There are three primary reasons that drive our decision. These include lower cost, higher capacity, and higher yield. With regards to cost, the expectation of the industry is that the unit IC cost will reduce by 30% within next two to three years. We have capacity installed with new technology and capabilities. If we continue to add capacity, 200 mm can take us to 0.13 µm, however, 300 mm can take us to 0.07 µm. The third reason is that we believe 300 mm yields will be significantly higher that 200 mm.

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The slow down in 2001 will not impact or slow down our 300-mm activity. We plan to continue with the pilot line, install technology, improve yield, and reduce the cost. TSMC’s strategy is to be ready for ramp up as quickly as possible once the business recovers. The timing of advanced 300-mm production is related to the business aspect. If the business climate is good, we can even run more aggressive technolo gies; if it is bad, we will stick to 0.13 µm design rules.

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In your opinion, what are the key challenges to transitioning to 300 mm?

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Our biggest challenge has been process integration defectivity. Currently, work is underway on

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0.13 µm technology, and there is no experience with 0.13 µm yet that can be shared. We do not see a major issue in transferring processes from 200 mm, 0.18 µm Al interconnect technology to the larger, 300 mm wafer size. Other key issues include fab production and automation. In introducing new process technologies such as sub-wavelength lithography, potential issues include mask OPC, focus exposure, etc. Defects in copper and low-k have been points of concern in 200 mm, and will continue to remain of concern in 300 mm. However, more work has to be done in these areas before key challenges can be clearly identified.


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What are the risks that you are most concerned about in transitioning to 300 mm?

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Yield is the number one risk. We can manage this risk if we are doing things right, and, therefore, get higher yield. Manufacturability for high volume production and process control is also a risk. In 200 mm you have issues like plasma conditions, chamber conditions, CMP dishing and erosion. When we transition to 300 mm we have been very careful to handle recipes. We are more interested in porting 200-mm recipes with long term high volume manufacturing history to 300-mm tools. With this methodology we believe the recipes and processes will be much more stable for processing thousands of wafers in high volume manufacturing. Our suppliers can also do much to mitigate these risks. Suppliers need to have better recipes when they design the 300-mm chamber. Some of them cannot scale up and that is a disaster. Better tool reliability tests for new 300-mm tool components and parts are also required.

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From a business perspective, how do you compare operating a 300-mm fab vs. a 200-mm fab?

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I believe 300-mm fabs will be more productive and have greater ROI than 200-mm fabs after 2002 because there is room for higher profitability and higher yield. Due to more die per wafer, time to volume requirements will be significant. Yield learning and process control are also very important. In this area KLA-Tencor can play an important role to help process parameter correlation to yield and get the process up very quickly.

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At 0.18 Âľm design rules the current 300-mm tools look good. Diffusion and wet bench tools require much improvement in productivity.

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What do you consider to be the major 300mm yield management and process control challenges?

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For 0.18 Âľm technology, to the first order, 1-sigma process uniformities and process windows are similar to 200-mm wafers. Systematic defects are primarily the integration defects, and will require some time to be really cleaned up. From photoresist to etch and strip we have some impact. These processes really need to be cleaned up and taken step by step. We are still studying them. Although the integration defects are only at a few percent, they are prevalent everywhere, both at front end and back end. From our first couple of lots we demonstrated we can achieve better yields than 200 mm, but there is still much room for improvement. We are now looking at improving these few percentages of yield loss resulting from systematic defects. Regarding our requirements for new capabilities and solutions for 300-mm yield management and process con trol, they are really tied to equipment parameter control. We should have the ability to collect data and use statistics, and develop the methodology to tie this to yield and sporadic scrap. The industry should focus on this. A significant level of hardware and software automation will be introduced in

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300 mm fabs. Could you share your thoughts on 300 mm fab automation issues?

How do you rate the process readiness and performance readiness of current 300 mm tools?

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Intra-bay automation is a must. To this end, TSMC has chosen overhead transport systems. Together with mini-environments, automation reduces yield variations. Automation capability is a key differentiator. Information technology should play a very prominent role in networking all the information together. Correlation of data is very important and a lot of work needs to be done in this area. Tools today provide a lot more valuable information and correlation of information such as electrical fault to physical defects is critical. This is an area that should grow in the semiconductor industry.

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What role did you feel that KLA-Tencorâ&#x20AC;&#x2122;s newest defect and metrology systems played in the success of your high yields on the first wafers out.

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Your brightfield inspection tool, the 2350, was instrumental in finding critical defects at STI and photo. Using this tool we were able to get high yields on our first 300-mm lots going out.

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Would you like to comment on any 300 mm topics or issues that we did not cover in our discussion?

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Silicon substrate shortage is a major concern. The companies in this infrastructure are not aggressive enough and investment is low. The whole industry should transition to 300 mm a lot faster. At the same time, I feel that the transition to 300 mm will occur much more rapidly than most expectations.

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Changing the definition of what’s possible.

Until now you’ve assumed that moving to 300-mm wafers was a risk-filled step into the unknown. Lam’s new 2300 etch systems change all that. Now you can develop your processes on 200-mm wafers, then quickly transfer them into 300-mm production. And you get the on-wafer results you need at sub-130 nanometer technology nodes. That’s a combination that enables new possibilities. It’s a new way to think about equipment design. And as risk free a future as you can imagine. For more information on the Exelan™ Dielectric 2300 etch system, the Versys™ Silicon 2300 etch system, and the Versys™ Metal 2300 etch system, visit www.LamBestinEtch.com.

© 2000 Lam Research Corporation. Lam Exelan™ and Versys™ are trademarks of Lam Research Corporation. The Lam logo and Lam Research are registered trademarks of Lam Research Corporation. All rights reserved.


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Reducing Risk at 300 mm By David J. Hemker, Ph.D., Lam Research Corporation

Drivers for the 300 mm transition are the need to reduce costs and increase capital productivity—not the need for new technical capability, although traditional design shrinks will occur concurrently. While the industry continually pushes the limits of technology, it is extremely adverse to risk. This article discusses the means to mitigate the risks of equipment procurement during the 300 mm transition.

Introduction

Minimizing Investment Risk

At 300 mm, IC manufacturers must concurrently manage increased wafer costs often accompanied by smaller geometries implemented in new materials. These tasks, combined with shrinking margins and fierce competition, create a situation where risk and development costs must be minimized in order to justify the transition from 200 mm wafers.

To minimize investment risk, manufacturers must consider initial equipment costs and other areas that are equally important over the long term. These include the state of the industry’s transition to 300 mm wafers and the production readiness of individual tools. Some factors that minimize risk are widely recognized and grouped by the industry under the term “overall equipment effectiveness’ (OEE), and each of these should be evaluated along with yield, which must be high to make the transition feasible. The following discusses each of the factors that reduce investment risk in detail.

Several areas need to be addressed to reduce the 300 mm transition risk. Delivering more mature equipment at release with fully developed 300 mm processes that leverage 200 mm experience is one way. This allows fabs to ramp quickly—without needing to debug new equipment or rework processes. Offering improved uptime and higher reliability on new tools is also important. Since manufacturers are targeting the same percent yield of good die at 300 mm as they currently achieve at 200 mm, addressing process uniformity and edge exclusion issues will be essential. Foundries and multi-product manufacturers will need application flexibility. Finally, minimizing 300 mm process equipment footprint and ensuring adaptability to future processes will be important. We can summarize all these requirements under three categories that must be managed to successfully transition to 300 mm: investment risk, technical risk, and obsolescence risk.

Equipment costs The economics of 300 mm equipment costs were debated back in 1998 in a two-part article by authors at Intel and Lam 1. Representing the IC manufacturers’ viewpoint, Intel considered the increase in capital (the relative cost of tools normalized by wafer output) and the increase in footprint (the relative size of the factory, similarly normalized) while transitioning from 200 mm to 300 mm on a factory-wide basis. From Intel’s viewpoint, in order to be economical, the increase in capital costs would have to be 1.3x or less, and the footprint should not increase. At Lam, we agree that, in the aggregate, 300 mm equipment costs may average a 1.3x increase over 200 mm equivalent equipment. However, to simply apply a 1.3x cost multiplier across all equipment ignores the possibility of broad capability differences among equipment offerings. Additions such as advanced factory automation and in situ sensors may not be available on all tools within an equipment category. Such capabilities should be considered in the cost equation since they impact productivity and yield, which affect overall Spring 2001

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ed as a fab line, or a new fab line is established, and volume production begins. A key strategy some manufacturers are implementing is process integration using 200 mm wafers. This approach reduces development costs by saving on expensive 300 mm wafers. Also, some key 300 mm processes, for example, lithography below 180 nm, are not yet widely available. Since chip manufacturers are bringing up initial 300 mm lines with established 200 mm processes, investment risk can be minimized when 300 mm equipment readily adapts to 200 mm and has a footprint equivalent to 200 mm systems. (Figures 1 and 3.) F i g u re 1. Lam’s na rrower 2 00/300 mm 230 0 footprint conser v e s

Teres System Layout

valuabl e cleanroom sp ace while providin g easy accessi bilit y as c o m p a red to the 2 00 mm Alliance™ footpri nt.

costs. Targeting increased productivity and capability relative to 200 mm, while maintaining a comparable footprint (Figure 1), provides a more comprehensive indicator of value than equipment costs alone.

State of the transition The transition from 200 mm to 300 mm is evolutionary, and the roadmap for production-readiness is short. Twenty-seven 300 mm facilities have been announced since 1999, including both R&D and production, and the number continues to increase (Figure 2). Leveraging 200 mm learning and ensuring equipment maturity will be critical to minimize risk and meet production time lines.

300 mm CMP System Layout

1997 1998 1999 2000 2001 2002 R&D/Pilot Lines in Operation (cumulative)

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F i g u re 3. Lams’ 200 mm Te res™ footprint versus its 200/300 mm

Corporation. Da ta for 2001 an d 2002 a re esti mates).

Te res footprint.

Ready for production

Overall equipment effectiveness

Manufacturers are very conservative when introducing new equipment and technology. First, R&D develops and characterizes unit processes (e.g., CVD, CMP, or etch). Then the processes are introduced on a pilot line to integrate the unit process into the overall process flow. Finally, the pilot line is expand-

Another important component of investment risk is overall equipment effectiveness (OEE), which includes capital investment, footprint, productivity, and uptime.

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Cost of ownership (CoO) is defined as the capital and operational costs required for a given level of produc-


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tivity, expressed as the number of good die per wafer per unit time. The capital investment portion of CoO is reflected in the selling price of the tool and is directly related to the supplier’s development costs. Suppliers can employ modeling to reduce their development costs, then pass the savings on to customers to lower their CoO. For example, gas flow can be modeled throughout the operating pressure range and thermal modeling can be used to understand and control important surface chamber temperatures. Plasma modeling can help optimize the chamber design and the coil configuration for transformer coupled plasma™ product lines. A common platform and common modules will also reduce production costs and CoO. The commonality reduces fab investment in parts inventory and maintenance training. Sensor development costs can also be shared across equipment types. For example multiwavelength interferometry, originally developed for endpoint detection (EPD) for CMP, can be extended to CMP thickness measurement, then adapted for etch-todepth endpoint monitoring. Balancing ease of serviceability with footprint for 300 mm is a particular challenge for suppliers, and advanced, streamlined, modular designs, as described above, are needed. The keys to enhancing 300 mm productivity (wafers/hour) are improving wafer transfer efficiency (less dead time during transfer in and out of load and vacuum transfer chambers) and reducing process times (with good etch rate, efficient endpoint detection, and good CMP removal rate, among others).

Yield Minimizing investment risk for 300 mm includes the assurance that yield will be sufficient to reduce per-die costs enough to justify the transition. Employing CoO formulas, manufacturers are targeting the same percent yield of good die per wafer on 300 mm as they currently achieve at 200 mm. To meet this aggressive goal, equipment suppliers will need to ensure uniformity across the larger 300 mm surface area. They will also need to monitor the wafer’s edge more closely because of the larger number of die in that region. Minimizing Technology Risk

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technology risk. Other means of assuring against technical obsolescence in a tool include its ability to process several device generations, its demonstrated process flexibility, and its maturity at the time of purchase.

Supplier-manufacturer collaboration To minimize technology risk, a new 300 mm tool should be adaptable to at least the next two to three technology generations. Customers have a range of individual, fast-changing roadmaps, and many future equipment requirements are yet unknown. To accomplish this extendibility, significant versatility must be built in, and direction from customers is needed. The responsibility for process development has moved toward suppliers in recent years, while chip manufacturers focus on integration issues. With the 300 mm equipment generation, we are beginning to see manufacturers working with suppliers to establish required process equipment capabilities. A mutual sharing of product roadmaps and greater trust is now emerging that will result in lower development costs and equipment that is better targeted to manufacturing needs. With mutual agreement on key parameters requiring independent control, flexibility can then be designedin-giving process engineers the right adjustable “knobs” to allow adaptation for future process development.

Next-generation readiness Drivers for the 300 mm transition are the need to reduce costs and increase capital productivity2-not the need for new technical capability, although traditional design shrinks will occur concurrently. For example, early adopters of 300 mm are using process flows developed for 180 nm. Other leaders are planning volume production at 130 nm by mid-2001, most likely starting on a 200 mm fab line. They can then rely on a good comparison with their baseline that was established with 200 mm wafers. Their goal is to have fully integrated processes for the next-generation interconnect technology (copper and low-κ interlevel dielectric) for 150 nm and 130 nm. The shrink is required for this next-generation interconnect technology to be fully cost effective. Beyond this, there will be other next-generation technologies, such as metal gate technology with a high-κ gate dielectric.

Strong collaboration between the supplier and manufacturer is one of the best assurances of minimizing

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We are seeing chip manufacturers take one of three approaches to prepare for the 300 mm transition: 1. Initially performing R&D for advanced processes at 200 mm on the dual-capability equipment, then later scaling to 300 mm. This allows manufacturers to take advantage of the most advanced materials and lithography, which are available only at 200 mm, and also to gain experience on new equipment. 2. Integrating the 200/300 mm equipment directly into 200 mm production lines since the equipment is competitive at 200 mm. This strategy provides learning on new equipment that will significantly shorten the ramp for future 300 mm lines, where process scaling is straightforward. This also reduces capital investment risk, should these manufacturers delay transitioning to 300 mm. 3. Employing the versatile equipment directly in 300 mm pilot lines. Because the difference between the 200- and 300 mm systems is minimal-a few parts changes and a straightforward scale-up of recipes-customers learning on the 200 mm equipment are extremely confident about the 300 mm equipment. Also, fewer 300 mm wafers will be needed to qualify processes 3. Regardless of the strategy employed, by the time manufacturers are ready for high-volume 300 mm production, they will have gained extensive experience with the equipment and processes.

Process flexibility

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Tool maturity Achieving tool maturity and reliability by working with customers prior to shipping the first production units is essential. Marathon internal testing, securing key beta sites and addressing all problems that arise, and leveraging proven technologies all lead to the required maturity. During the current transition to larger wafers, suppliers were afforded the time to establish maturity, and this advantage should pay off for manufacturers as they ramp product. Offering built-in 200 mm capability is another way to attain maturity, since it aids in uncovering problems that often do not appear until volume production. Gaining experience at 200 mm is also less costly than learning on 300 mm. Minimizing Obsolescence Risk

Obsolescence risk, a subset of investment risk, is inherent in technology-driven competition. The challenge for suppliers is to be ready for the unknown-to develop equipment with broad capabilities, while still controlling costs. The ability to easily adapt chambers to different processes reduces the threat of obsolescence and may reduce the number of specialized systems needed. The 300 mm generation will also require more sensors for equipment and wafer state monitoring, for factory automation, to leverage increased connectivity (intermachine, intra-machine, fab-wide, fab-to-fab, and fabto-tool-supplier), and to enable sophisticated diagnostics tools. Some of the needed technologies are available and being integrated on equipment. Other technologies are still in development. Process equipment designed with “plug and play” capability will ease the

Process flexibility is essential for minimizing technology risk since the requirements of future technology generations are not fully known in advance. Flexibility is also essential for foundries and multi-product manufacturers. Suppliers will need to adopt proven, flexible technologies, such as a dual frequency confined (DFC) plasma source for dielectric etch. Designing-in process versatility has led to the development of more than 40 integrated process sequences on Lam’s 200/300 mm-capable etch equipment. An example is etching a low-κ dual damascene via first stack in situ (in the same chamber) (Figure 4). Flexibility also enables processes commonly run in separate chambers, such as an ARC-open hard-mask etch and STI4, to be integrated and simplified, which improves both productivity and process results.

F i g u re 4. A low- κ dual damascene via f irst stack etch in situ (i n the same chamber).

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integration of important new technologies as they become available and reduce the risk of obsolescence.

Process conversion Processes become obsolete. For example, many fabs will be replacing aluminum metallization with copper, eliminating the need for aluminum etch chambers. A modular design should be incorporated into new equipment to enable conversion to new processes, when possible. For example, when fabs move to damascenepatterned copper, they will no longer require aluminum etch chambers for interconnect. Being able to convert obsolete chambers—for example, Lam’s 200/300 metal etch chamber converts to a polysilicon etch chamber— will protect capital investment.

In situ sensors To reduce the risk of mis-processing costly 300 mm wafers, in situ EPD and process- and wafer-state metrology are needed to enable equipment to signal when processes are within tolerance or completed, or when equipment is failing. Key technologies now available and being integrated on equipment to enable better process control include broadband optical emission spectroscopy (OES) and bias compensation electrical EPD. OES—The industry-standard EPD method for plasma etch has become OES, which depends on detecting the change in light emission at a characteristic wavelength as the underlying layer is reached. The output of a broadband OES can also provide a process “fingerprint.” Figure 5 shows a broadband OES spectrum of a baseline

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process of record (red curve). The blue spectrum shows the impact of a small change in power to the process. The spectra are a sensitive monitor of tool and wafer state that can help predict the potential for problems and avoid them. On Lam’s 200/300 mm etch systems, a similar technology enables real-time interferometry for monitoring etch steps. This eliminates the uncertainty of timed etch. However, if the exposed area at endpoint is small relative to the total wafer area, as with etching small vias, these methods may not be applicable. Bias Compensation EPD—Bias compensation endpoint sensing (a sensitive, non-optical, EPD method) has been developed to address some of the limitations of OES and timed etch. For the small exposed areas, which are required for certain dielectric etch applications, this electrical technique provides a higher signal-to-noise ratio than optical emission. The endpoint has been detected for exposed areas less than 0.01%5 of the total wafer area, when the nitride at the bottom of an etched via is barely exposed. The endpoint signal is generated at the wafer level rather than by a change in the plasma species. This provides earlier endpoint detection than optical emission.

Factory automation, connectivity, and diagnostics Since 300 mm fabs will be automated, advanced process control (APC) and factory automation capability must be built in or easily ported. Within-tool and external connectivity for data transfer must conform to standards. The system must be adaptable to existing industry standards and advanced standards that are still in flux-as well as to mechanical and electrical interfaces and protocols that are sometimes competing. Integrating widely accepted standards, such as Internet TCP/IP communication links ensures future scalability and adaptability. Specifically, using Internet protocols enables a remote PC browser to view tool operation and diagnose problems-or perform “e-diagnostics.”

F i g u re 5. The impact of a small change i n p ower ( blue cur ve) is comp a red to a bas eline process of re c o rd (red cur ve).

An open-architecture approach reduces the risk of obsolescence by easing the integration of new technologies to enable greater connectivity and speed for accessing, analyzing, and monitoring critical data. Key diagnostics being developed include advanced fault detection and analysis, predictive maintenance capability, integration of metrology and other off-board sensors, and advanced modeling to increase overall OEE.

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Conclusion

In the inherently high-risk, capital-intensive, semiconductor industry, equipment suppliers and semiconductor manufacturers must work together to achieve their mutual goals of minimizing risk and costs. This includes sharing responsibility for process development as well as jointly assessing the requirements for new equipment capability in order to manage today’s aggressive technology roadmaps. Innovative approaches are needed now more than ever to manage risk in ways that will benefit both suppliers and IC manufacturers. Working closely with customers in developing 300 mm equipment, we identified overall risk reduction as the primary challenge in the 300 mm transition. To support risk management, we recommend four broad strategies for equipment development: • Employ extendible, production-proven, technologyincluding current process technologies and securing as much production experience as possible.

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Similar strategies implemented by suppliers in other equipment sectors will reduce overall transition risk and help ensure a successful 300 mm generation for both suppliers and manufacturers. References 1. D. Seligson and J. Bagley, “Two sides of the debate on 300 mm tool costs,” Solid State Te c h n o l o g y, 41(7), July 1998, p. 344. 2. D. Seligson, “Planning for the 300 mm Transition,” Intel Technology Journal, 4th Quarter 1998. 3. N. Bright, “300 mm Begins: Etch Tool Readiness,” Semiconductor International, 23(8), July 2000, p. 136. 4. S. Lassig, C.S. Xu, A.J. Miller; S. Kamath, A. Romano, T. Kudo, “An Integrated Etch Approach as STI Evolves for the 100 nm Regime,” Solid State Te c h n o l o g y, July 2000, p. 157. 5. E.A. Hudson and F.C. Dassapa, “Sensitive Endpoint Detection for Dual Damascene Via Etch,” Plasma Etching Processes for Sub-Quarter Micron Devices, Electrochemistry Society Proceedings, Vol. 99-30, p. 295.

Trademarks

• Provide adaptable equipment-minimizing capital investment risk since timing for 300 mm and new materials and process ramps vary by manufacturer. Equipment that is independent of technology roadmaps-that is, equally capable and competitive at 200 and 300 mm with straightforward process scaling and extendible to 100 nm and beyond-will reduce this risk. • Enable versatile advanced process performanceincluding integrated in situ process capability to allow manufacturers flexibility in choosing processes and materials for 100 nm and beyond. • Leverage 200 mm volume learning-taking advantage of the most advanced lithography and high volume production that is available only at 200 mm to reduce 300 mm production ramp risk. This also eliminates the risk of 300 mm timing.

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TCP is a registered trademark of Lam Research Corporation, Fremont, Calif. About the Author

A 12-year veteran of the semiconductor industry, Dr. David Hemker joined Lam Research Corporation (Fremont, Calif.) in 1998. As vice president of new product development, he directs next-generation etch product, process, and 300 mm development. Previously, Dr. Hemker was vice president of technology for PMT/Trikon, managing research and development, technology, and engineering. He also spent five years in various technology roles at Applied Materials. He received his Ph.D. and MS degrees in chemical engineering from Stanford University, holds five patents, and has authored more than 25 published technical papers on semiconductor processing and thin-film applications.


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Defect Sample Planning in 300 mm Fabs by Dadi Gudmundsson, Natraj Narayanswami, Raman Nurani, Ph.D., Anantha Sethuraman, Ph.D., Mark Shirey, KLA-Tencor Corporation

The move to a smaller design rule and the associated processing methods are automatic byproducts of the demand for ever more-powerful ICs. As a result, there are some anticipated yield management challenges. Coinciding with the most recent IC design rule reduction is the long awaited transition to 300 mm processing which presents several unique yield manage ment problems not emphasized before. This paper presents some of the defect sample planning challenges associated with the 300 mm transition and discusses the fundamentals in surmounting them. A key conclusion is the importance of including yield management in the fab planning process from the beginning.

Introduction

The move to 0.13 µm, and the introduction of new materials and processing methods such as copper, low- κ materials, and phase shift reticles, are byproducts of the demand for more powerful ICs. As a result, the yield management challenges are difficult, but somewhat anticipated for a move to a smaller design rule. Some of the associated defect sample planning aspects, such as employing e-beam inspection in addition to optical techniques, have been explored3. For the first time in recent memory, the semiconductor industry is witnessing the convergence of shrinking design rules, transition to 300 mm, and implementation of new materials in the interconnect scheme such as copper and low-κ dielectric. Although the transition to new materials and smaller design rules are definitely technology enabling endeavors, such efforts are not without their characteristic yield management challenges. However, many of these challenges would have been encountered without the 300 mm transition taking place simultaneously. Supposing no 300 mm transition were taking place, previously established sample planning exercises could be performed effectively, with little or no change in focus, to establish effective yield management strategies. The fact that the

300 mm transition is taking place, along with other transitions, creates unique challenges and opportunities in yield management that warrant a new focus in defect sample planning. This paper has been organized to reflect those challenges and provide some insight and initiatives to surmounting them. At the outset, a brief overview of the 300 mm technological and process induced challenges are presented followed by a discussion on the classical yield management problem (more specifically defect inspection sampling). A recurring theme is that the layout and automation of the 300 mm facility or fab is vastly different from the conventional 200 mm fabs. Therefore, a significant portion of the paper focuses on the description of the issues relating defect sample planning to fab layout and material movement. Defect detection challenges in 300 mm

A variety of new challenges to defect detection are introduced during the move from 200 mm to 300 mm. First, there is the need for detection over a larger surface area. This requires modification of existing hardware. Second, and more importantly, is the use of new materials. This will change both the composition and type of defects encountered, requiring new techniques for their capture and automatic classification. Third, the size of “killer” defects decreases with the move to a smaller design rule, requiring an increase in tool sensitivity. Fourth, new inspection requirements, such as wafer backside inspection, become important, prompting the redesign of inspection tools. Finally, from a broader perspective, there are issues such as the need for seamless Spring 2001

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information exchange between defect detection and review tools, processing of greater amounts of data, and the need for automation of the defect sampling process, in keeping with the overall fab-automation initiative. In addition to the above, it is expected, and initial pilot line/ramp experiences confirm, that excursion rates can be higher. To some degree this is merely the fact that excursion frequency is measured in wafers. If one were to measure the frequency in number of dies between excursions, then the rates may be somewhat similar. However, we are not producing one die at a time and, therefore, excursions will occur at shorter intervals then in 200 mm processing. This may require every lot to be sampled at layers where that was not justified in 200 mm processing. The metrology industry is well on its way in providing the tools and techniques necessary to deal with the above mentioned challenges, but this capability needs to be deployed correctly. With major 300 mm fabs in the planning stages, a unique challenge and opportunity in yield management arises. By including yield management in the planning stage, a fab can be predisposed to deliver superior yields. Further emphasizing the need to include yield management in the planning process is the fact that 300 mm fabs will have processing and inspection tools bound together with various automated material handling systems. This will inherently make fab layouts and material flow less flexible, and emphasizes the need for setting the fabs up correctly the first time. Towards that goal, the following sections address the concepts and methods that should be employed to effectively include defect sample planning in the fab planning stage. Economies of scale and yield management

The fundamental premise of the 300 mm initiative is economy of scale, i.e. to decrease the manufacturing cost per square centimeter of silicon. It is estimated that the manufacturing cost per square centimeter of silicon will be about 30 percent lower. As one would expect, the pressure on improving yield management to produce more good dies at a lower cost is increased. It is, however, simplistic to enforce the same cost performance on yield management needs without considering the whole picture. Using the guiding principle of reducing inspection cost per square centimeter of silicon by 30 percent is not the correct metric in which to base the amount of inspection capacity needed. Instead one should seek to maximize the profitability of the fab 42

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and employ the inspection capacity needed to reach that goal. When calculating that capacity, fabs need to pay attention to several factors that collectively are embodied in a yield management strategy. A fundamental analysis of process tool, material handling, and inspection/metrology capacity planning is required. Furthermore, the impact of inspection on yield and cycle-time needs to be understood to provide a return on investment ( ROI) that is optimal. Strategies will then vary depending on the fab (development or production), device (memory, logic or mixed), and segment (captive or foundry). The transition to 300 mm has a larger impact on the economic aspect of wafer manufacture. Transferring processes with low baseline yield into ramp phase lack economic viability or, better yet, will be fiscal disasters. This further reinforces the value of a high yield learning rate being present early. Preliminary analysis shows orders of magnitude difference in the value of yield learning for 300 mm processing. Table 1 contains some of the parameters used and Figure 1 shows the results. It can be observed that there is a much greater return per yield learning percent increase in 300 mm processing than in 200 mm processing. Although a high yield learning rate is not only dependent on the available inspection capacity, a lack of inspection capacity can certainly be the limiting factor in the yield learning process and would most definitely be the differentiator in the long run between leading edge companies and the rest. ASP/cm2 of Silicon

$40

Wafer starts per week

1000

Die Size

1.5 cm2

Starting D0

0.65/cm2

Fault learning rate per month

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Tabl e 1. Parameters in yi eld learn ing rate anal ysi s 1 .

After the ramp-up phase is finished, the excursion control mode of yield management takes over for the full production phase. Again the 300 mm fab is faced with the dilemma that while the initiative provides considerable economies of scale in chip production, each wafer is much more valuable and that greater amounts of material are at risk to excursions than in 200 mm production. Calculating the relative value of 300 mm yield losses relative to 200 mm yield losses in the full production phase is much simpler than for the ramp up


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to locate them in the process, and how frequently to perform the inspections. To answer that, an effective method involves the trade-off between the cost of inspection operations, both fixed and variable, and the cost and/or risk of yield loss due to undetected yieldlimiting defects and process excursions.

The main decision parameters are: • Placement of the inspections (which process steps/process tools) • Type of inspections (test wafer, product, or in-situ inspections) • Inspection frequency (percent lots to sample, number of wafers per lot, area per wafer) • Inspection sensitivity to use F i g u re 1. Comparison of opport unity gai ned in 200 mm and 300 mm p rocessing f or a r ange of increased yield learn ing rat es. The inset explains th e definition of an increased yiel d learning rate, a traditional yield lea rning r ate i s in green an d an incr eased yield lear nin g ra te in orange.

phase. Utilizing the applicable inputs from Table 1, and assuming that the wafers starts per week are 4000 in this phase, we can calculate the value of lost materials each month relative to the same in 200 mm processing (see Figure 2). Numerous results in sample planning analysis2, 3, 7 have shown that the amount of inspection capacity to be used should be based on the value of the materials that can be saved. Given the vast value difference shown in Table 2 it is expected that greater inspection capacity will be needed for the full production phase in 300 mm processing. KLA-Tencor has a well established methodology to do sample planning for both the full production and ramp up phase of the fab. This methodology has the capability to address the 300 mm defect sample planning challenges. The following paragraphs address this methodology and its application to fab planning.

• Which parameters to track and respond to (Statistical Process Control scheme) • The fraction of defects to review • Inspection tool capacity All these parameters are inter-related and each one gives rise to a set of variables that need to be understood. KLA-Tencor’s Sample Planner 3 (SP3) cost model provides the framework and tools to analyze critical fab parameters to develop an optimal inspection strategy with reasonable effort. By joining it with analysis performed during fab planning, the fab plan can be deviced to have inherent advantages in yield management. In its simplest form, the cost model methodology is based around a recurring in-and-out of control cycle occurring at each step in the process. A cycle starts where each step in the process is assumed to have an in-control mode of operation, which delivers a high

300 mm defect sample planning

It has become well accepted that defect inspection tools play an important role in a fab’s yield management strategy. While few manufacturers currently operate without some type of defect inspection, many IC manufacturers tend to view inspection as non-value added and are overly conservative when planning inspection capacity. It is here that the sample planning problem arises, i.e. what types of inspections to perform, where

F i g u re 2. Examp les of the value of yiel d l osses to ex cursions for 200 mm and 300 mm proces ses duri ng the full production phase.

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F i g u re 3. Typica l questions pos ed i n a sa mple planning analys is.

yield. After a random length of time an excursion takes place, causing lower yields. At this point the inspection sampling strategy determines how quickly the excursion is caught and fixed, restarting the in-and-out of control cycle. It is sought to minimize financial loss by catching the excursions quickly, i.e. minimizing the time between excursion start and detection. It is here that accounting for yield management during fab planning is relevant. A significant portion of the delay to excursion detection is simply the time to get lots to the inspection tools. If a fab has badly placed tools and/or automated material handling systems that cannot accommodate the extra handling loads due to yield management, detection delays can be unnecessarily long and costly. Planning to prevent this type of problems is simply a classic sample planning problem with a greater focus on material handling and cycle-time modeling to provide the data needed that characterize a fab layout. Therefore, outputs of material handling and cycle-time modeling performed during fab planning need to be made available to sample planning analysts, who in turn can give feedback on the current fab plan strengths and weaknesses in excursion detection. Note also the importance of having short detection delays to achieve the accelerated, and very valuable, yield-learning rates.

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Fab planning with sample planner 3

Involving SP3 in fab planning requires the fab to provide good models for material-handling and cycle-time estimation. Then, by combining the outputs of these models with pilot line or applicable 200 mm data to characterize process variance and defect/excursion behavior, SP3 can quantify the yield losses to excursions. Typical analysis may involve the comparison of farm and hybrid layouts, see Figure 4. A farm layout is where all the metrology tools are kept in a separate bay while a hybrid layout has the metrology tools in the same bay as the process tools they are monitoring. A good materials handling model will be able to provide the travel times as a function of the track layouts, number of stockers, number of automated vehicles, the load on the system, etc. Joining that with a cycle-time model that accounts for processing and queueing times, a comprehensive estimation of how long it will take lots to reach their inspections is realized for both the farm and hybrid layout. SP3 can than use these results to quantify which layout will cause greater yield loss to excursions. Assuming that the material handling system and the number of inspection tools used is the same for both layouts considered, the differentiation comes down to the losses due to excursions. The analysis


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Conclusion

The economies of scale that are achieved with the 300 mm initiative have a flip side when it comes to yield management. The value of the material on each wafer is greater and more sensitive to excursions than ever before, calling for much more careful planning and deployment of inspection capacity. This is particularly relevant given the level of automation that is planned for 300 mm fabs that make it harder to alter layouts after the fact. Unless a fab correctly accounts for yield management during fab planning, there is risk of giving a fab an inherent handicap in yield management and losing considerable amounts of material to excursions. Those losses can significantly affect the gains foreseen from the economies of scale that drive the 300 mm initiative. References

F i g u re 4. Typical layout s compared in fab planning . F arm layout (left) has all metrology tools i n one bay, Hybri d l ayout ( righ t) h as metr o l o g y tools distributed to f unct ional ar e a s 4 .

can clearly involve greater complexity where the cost of different material handling options and inspection tool capacity needs to be accounted for as well. Initial 300 mm work and past experience have highlighted the following as the main drivers for inspection capacity: • Fab output (square centimeters of silicon/week) • ASP/product • Excursion frequency, types, magnitude, and yield impact • Tool capability/sensitivity • Material handling in fab/distance to inspection tools

1. Chatterjee, A. Personal Communication, Nov-Dec 2000, K L A - Te n c o r, San Jose, CA. 2. Elliott, R., et al. Sampling plan optimization for detection of lithography and etch CD process excursions. Pro c . SPIE 2000, vol. 3998, p 527-536. 3. Nurani, R., Gudmundsson, D., Preil, M., Nasongkhla, R., S h a n t h i k u m a r, G. Critical dimension sample planning for sub-0.25 micron processes. Proceedings of the 10th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, September 8 - 10, 1999. 4. Nurani, R.K., Gudmundsson, D., Stoller, M., Shanthikumar, G. Intelligent Sampling Strategies for Combined Optical/E-beam inspection. Yield Management Solutions, Vol 2, Issue 2, Spring 2000, p 28. 5. Wright, R. et al., “300 mm Factory Layout and Automated Material Handling”, Solid State Te c h n o l o g y, D e c e m b e r 1999. 6. Campbell, E. et al., “Simulation Modeling for 300 mm Semiconductor Factories”, Solid State Te c h n o l o g y, O c t ober 2000. 7. Williams, R.R., Gudmundsson, D., Monahan, K., Nurani, R., Stoller, M., Shanthikumar, G. Optimized Sample Planning for Wafer Defect Inspection. IEEE Intern a t i o n a l Symposium on Semiconductor Manufacturing, Santa Clara, C a l i f o rnia, October 11-13, 1999.

• Inspection tool throughput/queueing

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Reticle Automation Pathways for 300 mm-Era Fabs by Tony Bonora, Michael Brain and William Fosnight, Asyst Technologies, Inc.

As we advance further into the era of state-of-the-art fabs optimized for 300 mm wafers and the complex semiconductor products they contain, a sharper emphasis is being placed on reticles and their importance to the advancement of semicon ductor manufacturing. Defect sizes considered critical to semiconductors only a few years ago are now becoming critical for reticles. Moreover, the area of a reticle is much larger than that of a semiconductor die, resulting in a significantly lower allowable defect density. Thus, reticle manufacturing and handling methods need to advance to ensure that defects do not become yield-limiting.

Reticle manufacturing and handling

A reticle starts out as a “blank” of high-quality glass or quartz. From the blank supplier’s site, it must be transferred safely and cleanly to the reticle manufacturer for patterning. Reticle manufacturing consists of most of the same processes used in manufacturing a single layer of an integrated circuit (IC): film, photo, develop, etch, strip/clean, and inspect. After the reticle is manufactured, it must again be safely and cleanly transported to the IC manufacturer, where it will be stored, transported, and used within the facility. Throughout this process, numerous opportunities exist for the reticles to be damaged, through dropping, breakage, contamination, electrostatic discharge (ESD), mishandling, etc. Thus, it has become critical to have a strategy for isolating reticles and automating their movements to ensure that reticles are delivered safely, cleanly, and economically to the correct location at the optimal time. Most of today’s reticle handling is reminiscent of 150 mm-wafer manufacturing methodologies. Examples include manual substrate handling using “picks,” a vast array

of tool-loading requirements and orientations, tools that load the substrates in fixtures, and paper lot travelers. Tool suppliers resort to operator loading of special fixtures or cassettes, making mask shops especially vulnerable, as defect-density requirements tighten with the advent of advanced reticle technologies such as phaseshift and 157 nm lithography. Meanwhile, IC manufacturers have been subjected to ever-shortening life cycles of lithography technologies, which has forced them to endure the burden of using custom, and often expensive, reticle carriers that require custom automation and storage solutions. However, a reticle-automation strategy can be pursued that does not necessitate customized components and includes a comprehensive collection of modular, fully integrated products. Implementing reticle isolation and automation technology

Reticle isolation technology is fully analogous to the standard mechanical interface (SMIF) technology used to isolate wafers within IC manufacturing facilities. The key components of a reticle system incorporating both SMIF and automation technology include pods (closed, contamination-free carriers), SMIF-based interfaces (I/Os) for reticles, as well as robots, sorters, tracking devices and transport technology. Spring 2001 Yield Management Solutions

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allows tool suppliers to have one solution capable of working with both pods. Although IC manufacturers have opted for the smallerfootprint RSP-150 until the advent of 230 mm reticles, reticle manufacturers have decided to stay with the SRP, which can also contain any known reticle size format, including next-generation lithography (NGL), extreme ultraviolet (EUV) and scattering with angular projection electron-beam lithography (SCALPEL). RSPs with 200 mm wafer supports have been provided to support these development efforts. The advantage of the RSP being able to handle all reticle sizes outweighs its larger footprint for reticle manufacturers since they require far less reticle storage than IC manufacturers. F i g u r e 1. The Asyst Reticle SMIF-Pod (RSP) 20 0 mm p rovides conta minati on control by p rotecti ng r eticles durin g ha ndlin g and storage.

The Reticle SMIF Pod (RSP), capable of containing either a single 6-inch or a single 230 mm reticle, has been adopted by Semiconductor Equipment and Materials International (SEMI) as standard E100 and operates with the existing 200 mm SMIF interface standard (E19.4), which has been developed to fit myriad semiconductor tools. Asyst’s 200 mm RSP is shown in Figure 1. The first reticle manufacturers to adopt SMIF are blazing the trail for “hands off” manufacturing. Their efforts are paying off for all reticle manufacturers as reticle equip ment becomes increasingly available with SMIF integrated by the equipment OEM. Equally important, reticle equipment suppliers are freed from having to focus on resource-consuming custom-automation requirements. They can instead concentrate on improving and tuning the process and metrology technology that is their key source of differentiation. IC manufacturers belonging to Sematech’s I300I consortium (on 300 mm technology implementation) also decided to adopt the RSP as the standard for all 300 mm facilities, but because 230 mm reticle introduction has been delayed, they have standardized, for the time being, on a smaller-footprint, single-reticle pod based on 150 mm SMIF. This pod is known as an RSP-150. Some fabs intend to use 150 mm SMIF pods capable of storing up to six reticles. This pod is also being standardized and is known as an MRSP, or multiplereticle SMIF pod, such as Asyst’s MRSP-150. The RSP-150 and MRSP-150 (Figures 2 and 3) both work with the same 150 mm SMIF interface (E19.3). This 50

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F i g u r e 2. The singl e-reticle pod (SR P) is a smal ler-footprint RSP based on 150 mm SMIF.

F i g u re 3. The multi-ret icle pod (MRP) is a 150 mm SRP capable of storing up to six r e t i c l e s .


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Since reticle manufacturers are faced with many more types and configurations of equipment with which to integrate SMIF, the RSP offers an additional advantage. The proliferation of SMIF at 200 mm has resulted in a greater number of 200 mm SMIF interface solutions being developed to accommodate the wide variety of tool configurations. These solutions enable existing and future reticle manufacturing equipment to be more easily provided with reticle SMIF. Numbers released by DuPont Photomask suggest the semiconductor industry loses $200 million per year due to reticle damage caused by electrostatic discharge (ESD), a key consideration during the development of the SEMI-standard reticle SMIF pods. Isolating the reticle from all unpredictable and variable means of handling is fundamental to an effective ESD control strategy. Reticle sorters allow the management and handling of reticles within an IC fab while isolating the reticles from this and other mechanisms of operator damage. The reticle sorter may also be used to transfer reticles from the RSP to the RSP-150 at the reticle manufacturer prior to shipment to the IC manufacturer. Indexers, such as those in Asystâ&#x20AC;&#x2122;s SMIF-INX family (Figure 4) include an integrated SMIF port to provide contamination control while minimizing equipment footprint.

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dard and allows device makers to access multiple reticle-carrier suppliers. Lithography functional areas, traditionally difficult to automate, will now integrate carriers that can be easily automated in a variety of ways. This offers opportunities for improving reticle management and equipment layouts. Both reticle and IC fabs alike are trying to converge upon a single-reticle carrier design to facilitate equipment designs as well as lower costs for themselves and suppliers. A common carrier format for reticle and IC manufacturing facilities opens the door for a carrier that functions as a shipper between mask and IC fabs, simplifying operations and offering superior reticle protection. Furthermore, the common carrier can be maintained for shipper reuse, according to preliminary data presented by Intel and Asyst at SPIE 2000. The overall cost of ownership for a standard reticle carrier will be comparable, if not lower than for custom boxes in use today. Furthermore, due to the stringent technical requirements of storing and transporting next-generation reticles, the move to a new carrier

Integrated reticle-handling vision

As leading-edge device manufacturers move toward using more sensitive 193 nm and 157 nm reticles, the industry-wide need for a more sophisticated reticle carrier has finally opened a window of opportunity to capitalize on the many benefits afforded by standardization and automation: 1. Standardized carriers improve factory efficiency and lower costs associated with reticle storage and management. 2. The move toward standard carriers helps simplify equipment design and removes much of the burden of carrier design, manufacture and support from lithography equipment suppliers. This frees supplier resources to concentrate on core technical competencies in support of meeting the demand for shorter development cycles. 3. A standard carrier enables equipment suppliers to order off-the-shelf configurations for tool interfaces based on the well-established SEMI E19 SMIF stan-

F i g u re 4. Asystâ&#x20AC;&#x2122;s SMIF-INX family of indexers includes this unit, optimized fo r 150 mm reticle SMIF.

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architecture is unavoidable. Next-generation stockers will likely be required to maintain the reticles in an oxygen-depleted environment. Additionally, IC makers will be presented with new challenges in safely scheduling, managing, and transporting highly sensitive and costly next-generation reticles. These challenges, however, lead the way to operational improvements long sought after, but never realized, due to IC makers’ desires to minimize design impact on lithography equipment. Automated reticle tracking

To protect a reticle is to ensure that it is not damaged during transport and handling. Utilizing industrystandard carriers facilitates the use of the automated tracking systems currently deployed in over a hundred semiconductor fabs. These automatic identification and tracking systems utilize a tag-device attached to each pod. The identity of the material is written into this tag using either infrared (IR) or radio-frequency (RF) communications. Some tags have a liquid crystal display for the operator to immediately see what is in the pod and where it should go next. When the pod arrives at a process or metrology tool or automated material handling system, the tag is read automatically, and software (the function of which is to ensure correct handling) prevents inadvertent loading of the wrong reticle into a reticle production tool or fab stepper. Reticles in storage can be quickly located to ensure that they are at the right place at the right time. Handling history can be recorded in the tag, much as history is often manually recorded on paper travelers, to automate functions such as controlling the re-certification of reticles in use. One such system is the Asyst SMART-Tag, shown on the MRSP-150 in Figure 4. Automated material handling systems

The size of 300 mm wafers, their value, the increased number and complexity of process steps, the increased

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cost of the facility and equipment itself, and chipmakers’ competitive pressures to improve their own manufacturing economics, will place demands on a fab’s automated material handling system (AMHS) requirements that even today’s most advanced 200 mm fabs will be unable to fulfill. A number of key issues will drive AMHS needs for 300 mm. One that is critical to productivity is photolithography bay automation. It does no good to get the right lot to a stepper on time if the reticles for that process step aren’t available. An AMHS that can also deliver the correct reticle to the correct stepper, at the correct time, will enhance tool productivity for any fab that has a broad variety of products. Conclusion

As the semiconductor industry looks forward to the 300 mm era, IC manufacturers are looking to advance to the next level of automation: standard interfaces, closed carriers, auto-ID capabilities, and automated transport systems. All of these contribute to true hands-off manufacturing, which helps eliminate the possibility of operator-induced defects, random electro static discharge (ESD) damage, particle contamination, and misprocessing. The semiconductor industry made a big leap to automated material handling and product protection in obtaining cassette-to-cassette automation for 200 mm wafers. This enabled standard cassette loading, diminishing the need for direct wafer handling by operators who now handle only the cassettes in most fabs. The references to semiconductor manufacturing point up the opportunity for reticle and IC manufacturers to “leapfrog” the 200 mm-wafer era substrate automation and proceed directly to standardized, automated reticle transport and handling consistent with the isolation technology approach of 300 mm wafer facilities.


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Challenges for the Sub-0.18 µm Era by Didier Lamouche, ALTIS Semiconductor

The primary challenge for the sub-0.18 µm era lies in bringing the semiconductor industry to maturity. In this paper the concept of a mature industry will be discussed, the gaps between the present state of our industry and a mature version will be explored, and suggestions for how to drive the maturity of the industry will be offered.

Familiar classical predictions of the challenges of the sub-0.18 µm era include the following:

out of the door and accelerate the yield curves, it is worthwhile to look ahead to see what challenges accompany sub-0.18 µm technology.

• Lithography will push the limits of optical resolution.

Our immature industr y

• Plasma etch and deposition will be challenged by issues of aspect ratio and selectivity. • Planarization will be a key challenge, as CMP becomes the pervasive technique, and brings issues of uniformity and end point control.

Figure 1 illustrates how the industry has been progressing since 1993. This chart shows the area of silicon needed to make up 256 MB of memory, whether from sixteen 16 MB chips, (Luna E and the ES chips, 1993-1997); four 64 MB chips (Prism, La Tierra and Viper, 1997-1999), or one 256 MB chip (Cromus, 1999). The silicon area needed for 256 MB of DRAM is shrinking rapidly—and the latest generation of chips is a factor of two smaller than Cromus.

• Silicon area efficiency will emerge as an important issue, as feature size continues to decrease, and the I/O density begins to limit the shrinking of the overall device. While each of these technical arguments has merit, the more general topic of the maturity of the industry has received less attention. For that reason, this article will bypass the classical arguments and focus on the larger perspective. To discuss the challenges for sub-0.18 µm device manufacturing does not imply that all problems for the pre-0.18 µm technology node have been solved. Most fabs today still struggle to scale the reliability curves for technologies that remain above 0.18 µm. As the industry works to get more chips 54

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F i g u re 1. The sil icon area re q u i red to comprise 256MB of DRA M using 16MB, 64MB or 256MB chi ps has shrunk dramat ically since 1993.


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F i g u re 2. Lar ge growth rates and rap id swings ar e a key indicator o f the immaturi ty of the s emicond ucto r i ndus tr y.

Looking at the industry from a different perspective, Figure 2 reveals the immaturity of our industry more directly. This chart shows the year-to-year growth or recession of our industry since 1978. Growth rates of 20%, 30%, or even 40%, are followed by brutal recessions of 10% or 20%. These swings are typical of an immature industry. When a mature industry like the automobile industry has a good year, they grow at 5% to 10% per year globally; a bad year would be characterized by 5% recession. A focus on yield is one key element that differentiates an immature industry from a mature one. In the manufacturing environment, mature industries like the automobile industry or the tire manufacturing industry focus more on reliability and defects than on yields. No one would imagine GM or Ford throwing away 20% of their cars at the end of the manufacturing line. At the other end of the scale, an emerging industry is not ready to focus on yield; it is focused on having a working product. In this learning phase, 5% or 10% yield is acceptable. In between the mature and emerging industries are the growing, immature industries where yield is extremely important—such as the semiconductor industry. These industries have yields in the range of

20% to 80%. The fact that our industry is preoccupied with yields is a key proof that it is not mature yet. In the early 1980s when the design rule was 1 µm, some people predicted that sub-micrometer devices would not be manufacturable. Twenty years later, we manufacture 0.15 µm products. Another interesting study by an American scientist calculated the global revenue of the semiconductor industry, under the assumption that the industry would grow at 20% per year indefinitely. His conclusion was that the revenue of the total semiconductor industry would exceed the world GDP in 2040, which is by definition impossible. Given that the industry has to saturate one day, what will happen to the yield? Figure 3 shows the yield learning that has been achieved since 1990 for DRAM technology. The vertical axis shows the wafer yield, and the horizontal axis gives the number of wafers that were expended before that level of yield was achieved. The desirable part of the curve is in the upper left-hand region—the fewer wafers needed to get to higher yield, the more cost-effective the product ramp. This chart shows that the trend is becoming steeper and moving towards the left: yields that used to take years, now take months. Another way to represent the same information Spring 2001

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is that the number of wafers needed to achieve a given yield has decreased a thousand-fold in 15 years. Key market stimuli

Yield learning is an unavoidable race—one cannot simply stop when an industry has become mature. How quickly will our industry become mature? To answer that question one should look in detail at the boundary conditions and the stimuli that the current market is applying to the semiconductor industry. Four types of stimuli are important to the advanced semiconductor business; the first one is a decrease in product cycle. Even the consumer applications today tend to use more and more advanced semiconductor technologies. Five years ago only industry applications— high end personal computers or main frames—were using the advanced 0.5 µm technologies. Today, consumer applications are driving the race to produce leading-edge technology. For example, cell phones are equipped with 0.25 µm technology, and the product cycle of a cell phone is six to nine months. If a new phone is introduced too late for December sales, the impact on yearly revenue is significant. A yield bust in October would cause the cell phone manufacturer to

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miss a whole year of revenue. Shorter product cycles result in no time for yield learning. Second, investment rates are growing. Today a new fab costs US$1.5 billion. Consequently, rapid recovery of the initial start-up investment provides a strong stimulus to the semiconductor industry. Third, the race to function integration, or so-called “system-on-a-chip”, is about to explode. Even though today most applications based on multiple-chip solutions are cheaper than an equivalent integrated solution on one chip, performance will drive the integrated solution to dominate. The main driver again is consumer applications, especially the wireless phenomenon; the marketplace has an insatiable demand for smaller and smaller telecommunications appliances that enable instant, round-the-clock connectivity and remote data access. This is driving the integration of many different functions: DRAM, flash, high power devices, RF capabilities. The fourth market stimulus is the fast production ramp, which is really a consequence of the other three. Fabs need to be ramped up almost before they get started. Together these four stimuli drive the industry to a faster and more difficult yield ramp.

F i g u re 3. The yield lea rning t hat has bee n a chieved since 1990 fo r DR AM tech nolo gy has been dramatic, as th e number of wafers re q u i red to meet a given yield has b een reduced one thousa nd-fold .

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F i g u re 4. This ex ampl e from an embedded DR AM product at ALTI S demonstra tes that ma stering th e DRAM (ES products) and logi c components is not eno ugh; the challenge lies in the integra tion of the two.

Recommendations for success

The market stimuli of shorter product cycles, growing investment, function integration, and fast ramps are driving the need to migrate from a yield learning culture during the manufacturing phase towards failure mode prediction before the manufacturing ramp. This migration is driven primarily by function integration. Figure 4 provides an example from an embedded DRAM product at ALTIS. The vertical axis is the desired yield, and the horizontal axis is time in years or quarters. This chart shows good yield learning throughout shrinks from 0.5 µm to 0.45 µm to 0.4 µm to 0.35 µm, and yields were attained and stabilized well above 80% for a long time period. At the same time, ALTIS had a pure digital logic technology running at 0.35 µm, which was very stable also in the lower 90% yield range. However, when a new design was introduced that merged those two technologies into a new one called embedded DRAM—the first instance of a system-on-a-chip solution —ALTIS experienced a yield bust from which it took six months to recover. The message is that mastering the DRAM and logic components is not enough; the challenge lies in the integration. To enable future suc-

cess in integration, the key is to transfer one’s mindset from yield learning to failure mode prediction. The defect problems that were responsible for this yield drop were defects neither attributable to the DRAM nor to the logic, but rather to their integration. Failure mode prediction includes understanding various topology effects such as pattern density variations on a chip, focusing on local areas which might be sensitive to yield problems, and building more redundancy. Powerful CAD packages can be used to simulate materials properties and stacking of the various layers. Simulation of the 3D environment may point to specific topology problems, identifying local areas where problems might occur, so that additional redundancy can be built in. Alternatively, the inspection sampling strategy can be changed to monitor certain problem areas on the chip more carefully. The second challenge has to do with the manufacturing ramp—maintaining the maximum yield demonstrated during the development phase while the products are ramped. This challenge requires process control, tool control, tool and process fingerprinting and duplication, and very fast feedback loops. The graph on the Spring 2001

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left in Figure 5 compares a typical volume/capacity ramp with a non-competitive yield ramp. During the non-competitive yield ramp, yield busts occur from time to time, typically while ramping the capacity. These yield busts are particularly damaging with short product life cycles. In the future, the industry will need competitive yield ramps as shown on the graph on the right in Figure 5. In this example the yield is high from day one in the development phase, and the yield is maintained during an aggressive ramp, while new tools and products are introduced. The product cycle time drives this new requirement. The third challenge is the cost of capital. We have to invest $1.5 billion to put a new fab online. Depreciation is calculated on a five-year period; however, five years is more than the duration between two down cycles. Thus we need to get the cash out of the fab in less than the depreciation period, or we need to change the depreciation rule. Clearly, maximum return on investment means that yield busts cannot be tolerated. Instead, we must transform the yield learning culture to a failure

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mode prediction culture, and learn to accomplish a volume ramp while keeping the maximum yield. In conclusion, it is clear that a revolution in thinking is needed to bring our industry closer to maturity. Once it matures, we will not talk about yield or yield ramps any more. In the meantime, the yield ramps have to become steeper and steeper. As a consequence, the companies who win the semiconductor race will have to lead the yield learning race. The first key challenge and success factor is migration from a yield learning approach to a failure mode prediction approach, so that maximum yield is obtained before the manufacturing ramp. The second is the ability to maintain maximum yield during the manufacturing ramp. A key to failure mode prediction lies in simulation techniques that bring together the design and process in order to anticipate which device types could fail when they are integrated on a chip. Maintaining maximum yield during your manufacturing ramp up may require better process control, faster feedback loops, or better tool fingerprinting.

F i g u re 5. The graph on the left com pares a typical volume/capacity ramp with a non-competitive yield ramp ha ving an ob vious y ield bust . T he graph on t he ri ght shows the future re q u i remen t for competit ive yiel d r amps, where th e yield is high beginning in th e devel opmen t phase, and is mai ntained duri ng a n a ggressive ramp .

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An Interview with Didier Lamouche Chief Executive Officer of Altis Semiconductor.

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Are you suggesting 2040 as the year when the semiconductor industry will be mature?

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I think maturity will come much sooner than 2040. While the automobile industry took something like 60 years to become mature, I think the semiconductor industry will mature much faster. The key difference is in the penetration rate of the technology. The number of applications for our products is enormous and growing every day. To keep this growth, we have to become mature very fast—within 10 or 15 years.

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You have emphasized yield prediction, but you have not indicated what tools we might use to accomplish this. What priority do you place on wafer inspection tools and software to calculate yields?

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When you want to ramp up the yield curve on a product, you may encounter specific design or process related problems like junction leakages, and topology effects that might leave some residue that causes shorts or open contacts or voids. Failure mechanisms are really dependent on the design and integration of functions. I would emphasize CAD techniques that include layerby-layer simulation of your design, simulation of the growth of the layers, deposition of films, and uniformity of the films and of the edge.

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Didier Lamouche is Chief Executive Officer of ALTIS Semiconductor, a newly formed joint venture between IBM and Infineon, located south of Paris, France.

The simulations will help predict which local areas on the chips are more likely to be difficult to etch, or are more likely to be susceptible to pattern density effects. Then, before you place the product in production, either you address the sensitive areas by internal redundancy, or you focus your inspection tools on this specific area to control it very tightly and to catch any excursions.

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To address the two different approaches for success—the prediction of failure modes and keeping the yield up when you are in ramp or sustaining phase—do you recommend different organizations working in these two specific areas, or having a single organization working on both parts?

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I think the ideal organization would have one group focused on the product integration, process integration, and yield understanding, and another one focused on the operations, tool maintenance, etc. Such an organization would be best equipped to ramp up very quickly and to surmount the challenges that I have been describing.

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Critical Dimension Sample Planning for 300 mm Wafer Fabs Sung Jin Lee, Raman K. Nurani, Ph.D., Viral Hazari, Mike Slessor, KLA-Tencor Corporation, J. George Shanthikumar, Ph.D., UC Berkeley

Critical dimension (CD) control is crucial in photolithography and etch processing steps, because of the relationship between gate length and device speed performance. To control the CD, values of lot average and/or lot variance are generally plot ted on SPC charts to detect mean and variance excursions that occur during these processes. An optimal sampling plan and control methodology must not only enable resolution of important (yield-impacting) excursions, but also minimize the time it takes to detect an excursion, thereby minimizing the number of lots exposed to an excursion.

A CD sampling plan specifies what CD measurements are performed, i.e., how many lots, how many wafers per lot, how many fields per wafer, and how many sites per field; as well as which wafers, fields, and sites are measured. The control methodology specifies how CD measurements are used to characterize normal variations and monitor and control deviations. This includes design of appropriate SPC charts and APC (automatic process control scheme with either closed or open loop feedback). A comprehensive methodology was previously presented2 to evaluate the effectiveness of different sampling plans by using the data from a 200 mm advanced logic fab. The effectiveness of a given sampling plan was evaluated by trading off the beta risk (probability of having material at risk) and the alpha risk (probability of having a false alarm). The current paper extends this methodology to the 300 mm domain, discusses potential issues for CD control of 300 mm patterning processes, as well as sampling recommendations for certain conditions. The primary driving force for the 300 mm transition is the anticipated reduction in total production cost per square inch of silicon. The key to achieving this is to increase 60

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the productivity of the yielding die and wafers at minimum total cost. It is very important to note that the total cost includes not only the cost of producing the wafers but also the cost of controlling the process for minimizing the material at risk. While reducing the total cost of operations, it is critical to optimize the value of in-line defect and metrology inspection. Otherwise, the cost of increased material-at-risk due to poorly optimized inspection methodology will outweigh the savings from reduced investment in process control. A 300 mm wafer has 2.25 times more area than a 200 mm wafer. If all other parameters are held constant, it results in 2.25 times more die per wafer, with correspondingly more material exposed to process excursions. Along with the 300 mm transition, the semiconductor industry is also transitioning from 248 nm to 193 nm lithography, from aluminum to copper interconnect metals, and from silicon dioxide to low-Îş interconnect dielectrics, all driven by ever-shrinking design rules. Although a statistically determined sampling plan is essential in understanding and reducing material-at-risk, in practice, many sampling plans are still determined by historical precedent. Few papers present statistical approaches to determining the optimal sampling plan1. In the current paper, issues and concerns regarding the importance of CD control in a 300 mm fab are presented. A simulation study is presented, where 300 mm CD variations and excursions are simulated and compared


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to data from a 200 mm advanced logic fab1. Finally, CD sampling requirements for a 300 mm fab for excursion monitoring are evaluated. We will demonstrate that use of a sampling scheme optimized for 200 mm patterning processes will result in increased material at risk in a 300 mm fab, thus emphasizing the need for characterizing and optimizing the CD sampling plan for 300 mm fabs. F i g u re 2. The area increas e in 8 to 12 inch wafer diameter transiti on

CD control for 300 mm

is much hig her than t hat of 6 to 8 inch wafer diamet er transition.

A primary requirement for designing an optimal CD control methodology is to characterize and understand baseline spatial CD distributions across the lot, wafer, and field. Below, we outline some anticipated characteristics of a 300 mm intra-wafer CD distribution based on variation signatures observed in 200 mm processes.

Stronger radial effects on baseline CD values Cross-wafer CD variations have a variety of sources, from direct causes such as etch-rate spatial non-uniformity, to those less direct, such as incoming film-reflectivity variation. These result in different baseline averages of the exposure fields on the wafer, as was reported in a case study 1. An example of a simple radial crosswafer CD variation is shown in Figure 1, with a typical (200 mm) 9-field intra-wafer sampling plan superimposed on the distribution. If such a variation signature were extended from a radius of 100 mm to 150 mm, the center-to-edge CD variation would be correspondingly amplified, resulting in a wider (and shifted) CD distribution.

Figure 2 graphically shows that the increase in the wafer area for the 8 inch to 12 inch transition is about 125 percent whereas the increase in the wafer area in the 6 inch to 8 inch transition is only about 69 percent. Considering the fact that the device speed and performance are strongly influenced by CD, the amplified radial variation observed for 300 mm could cause significant deviations from specification near the wafer edge. Of course, these are the very die that are required to realize the potential benefit of the larger substrates. It is important to characterize the spatial distribution of the baseline field averages by appropriate sampling plan and analysis for 300 mm processes; then, one can devise control and process improvement methodologies to reduce systematic variation signatures, such as the radial example presented here.

Higher baseline field-to-field variation: Need for Generalized ANOVA As discussed above for a 200 mm to 300 mm transition, one might expect an increased cross-wafer range of CDs, resulting in increases in both systematic (different field means) and random field-to-field variances. When a traditional nested ANOVA analysis technique is employed, higher systematic field-to-field variation has a greater chance of providing negative numbers for random wafer-to-wafer variation, as was shown in1. Thus, for reliable estimates of 300 mm variance components, it is necessary to use the Generalized ANOVA presented in 1 for separating the systematic variations from random variation.

Impact of wafer level excursion on 300mm Y/mm X/mm

F i g u r e 1. Baselin e CD values across the di e showing stro ng radial e ff e c t s .

A previous paper1 discussed several CD mean and variance excursion types based on data from a 200 mm wafer fab. Some of those types are re-presented in Figure 3a and 3b under different groups. Observe that the occurrence of the first type affects CD deviations on all the fields on a wafer, either uniformly or with a certain pattern. Some of these examples include wafer Spring 2001

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F i g u r e 3a. Di ff e rent types of wafer level excursions.

wedge excursion and all-fields-down (where the CD values of all the fields on the wafer are far below the lower process control limit). The occurrence of the second type affects CD variation only on single field or on smaller subset of fields on a wafer. Some of these examples include one-feature-up excursion, and one-featuredown excursion in a field (see Figure 3b). Also, note that this type of excursion could occur randomly in any set of fields on the wafer. Excursions in both categories will become major issues in 300 mm fab. More area on 300 mm wafers can cause higher variation than in 200 mm wafers. The impact of these two groups of excursion types on a 300 mm wafer will be different and need to be studied. Consider the case of wafer wedge excursion. There can be higher CD variation on the 300 mm edge fields as compared to 200 mm edge fields. This tells us that the excursions in the first category can cause more para-

F i g u re 3b. Dif f e rent types of field level excursions.

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metric yield problems in 300 mm fab than in 200 mm fab. Therefore, it is critical to minimize risk for 300 mm wafers.

Impact of field level excursion on 300 mm Because of the increase in the number of fields for a 300 mm wafer (see Figure 1), a given wafer has a greater chance of exposure to field level excursions before detection. Also, several lots may be at risk if there is a significant delay in detecting such an excursion. In a later section, we present the impact of using the 200 mm sampling plan in such scenarios and recommend a new 300 mm sampling plan. To detect field level excursions on 300 mm wafers, it may be important to control CDs at the wafer level or even within the wafer level, suggesting evaluation of lot-level SPC charts. In summary, both baseline characterization and excursion detection should be examined more thoroughly in


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a 300 mm fab because of the greater material-at-risk in each wafer. The higher field-to-field variation expected across a 300 mm wafer will necessitate a baseline sampling plan that effectively resolves all significant variation signatures, as well as separates systematic (meanshift) from random variations. A simulation study: Optimal 300 mm sampling plan for excursion detection

As discussed in the previous section, it is essential to have optimal sampling plans for both baseline characterization and excursion detection. In this section, we focus on the sampling plan for excursion detection. First, we investigate application of the optimal 200 mm sampling plan for monitoring excursions in a 300 mm patterning process, and show that this direct transfer could cause significant increase in material-at-risk. We then propose and evaluate an improved 300 mm sampling plan that matches material-at-risk levels of the 200 mm sampling plan.

Assumptions

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8*2.25=18, and 18 respectively. This will lead to an excursion occurring every 30.8 (=50*32/52) lots on the average in an equivalent 300 mm fab, essentially doubling the excursion frequency Baseline averages and CD shifts during mean and variance excursions were extrapolated from the 200 mm fab data. Extrapolation was done by assuming that the CD values on a wafer follow a smooth radial pattern. The most natural definition of a 200 mm sampling plan in 300 mm fab is to assume that the same measurement tool capacity is used by both of the fabs. To ensure this, the number of fields sampled in a 300 mm fab should be equal to the number of fields sampled in a 200 mm fab multiplied by the ratio between the arrival rate at a measurement tool for the two fabs. In this analysis, the underlying assumption was that the ratio was equal to one. Results

200 mm wafer fab with 200 mm sampling plan and 300 mm fab with the same 200 mm sampling plan

Data from a 200 mm fab case study data is used for this evaluation1. As part of this case study, the optimal sampling plan in 200 mm fab was found through KLA-Tencor CD Sample Planner software. We denote the optimal 200 mm sampling plan as X wafers per lot, Y fields per wafer, and Z sites per field. It is assumed that the die size of a wafer is 1.3 x 1.1cm, and 6 die are in a field. This assumption gives 138 die (23 fields) on a 200 mm wafer, and 366 die (61 fields) on a 300 mm wafer. Baseline statistics and excursion statistics of CD values from the 200 mm fab case study was used. Because of the increase in wafer area, field-level excursion frequency (see the previous section, â&#x20AC;&#x153;Excursion Detectionâ&#x20AC;? and Figure 2) will increase by 2.25 times. However, we assume that excursion frequency in the first category remains same. Then, the mean time to an excursion in 300 mm fab, when expressed in terms of number of wafers or lots, will be much less than the mean time to an excursion in 200 mm fab. For example, suppose an excursion was seen in every 50 lots on the average in a 200 mm fab. Also, suppose that there are two types of wafer-level excursions, wafer wedge and all-up excursions, and that there are two types of field-level excursions, say feature-A-up and feature-B-down excursions. Assume that the average number of occurrences of these excursions is 8, 8, 8, and 8 respectively. Extending this from 200 mm to 300 mm, the expected number of occurrences of these excursions will become 8, 8,

F i g u re 4. Usi ng 200 mm sam pling scheme for C D contr ol on 300 mm waf ers results in hi gher mater ial-at-risk.

Figure 4 presents the results of a 200 mm and 300 mm wafer fab with the 200 mm sampling plan. The vertical axis represents the average fraction of material-at-risk, i.e., the average fraction of lots that will be exposed to undetected process excursions. This is a function of the excursion types, their frequency of occurrence, their magnitude and the effectiveness of the sampling plan and control methodology in detecting process excursions. For this analysis, we assumed that the lot average and lot standard deviation of the CD values were used on SPC charts to monitor the CD variations. The horiSpring 2001

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zontal axis represents the average fraction of false alarms, which happens when the SPC chart provides a signal while the process is in control. It can be observed from Figure 4 that for a false-alarm fraction of two percent, the fraction of material-at-risk increases by almost 50 percent from using the 200 mm sampling plan in 300 mm fabs. It is clear from this result that the 200 mm sampling plan can lead to very high material-at-risk in the 300 mm fab. Thus, an entirely new sampling plan is required to reduce the material-at-risk in the 300 mm fab. It is important to emphasize that a one percent saving in material-at-risk could result in significant financial returns in a 300 mm fab. For example, assume that a fab has 5,000 wafer starts per week, 200 die per wafer on a 200 mm wafer and an equivalent 450 (=2.25*200) die per wafer on a 300 mm wafer, and $100 selling price per die. Then, one percent material-at-risk has a revenue potential of $1 million a week for the 200 mm wafer, whereas the 300 mm wafer has a revenue potential of $2.25 million a week, which translates into $117 million a year. Assume a very conservative yield benefit estimate of 10 percent, which is the difference between the baseline and excursion yield, and a baseline yield of 50 percent. Saving one percent materialat-risk will result in a net benefit of $2.6 million a year for the 200 mm fab, and $5.85 million a year for the 300 mm fab. Note that the excursion yield is generally much lower than the baseline yield. Also, the selling price for lower performance chips can be much lower. Hence the yield benefit of reducing material-atrisk by one percent can be much higher. This additional dollar saving needs to be weighed against the cost of any increase in capacity of CD measurements.

300 mm fab with 200 mm sampling plan, and a recommended 300 mm sampling plan KLA-Tencor’s CD Sample Planner was implemented to determine a sampling plan that would reduce the fraction of materials-at-risk close to that of a 200 mm fab. Since 2.6Y number of fields gave the desired fraction of materials-at-risk, the CD Sample Planner suggested using X wafers, (2.6)Y fields, and Z sites, as a 300 mm sampling plan. Figure 5 displays the results. Conclusions

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F i g u re 5. New 300 mm sa mpling p lan wit h mo re fields on the wafer reduces t he material-at-risk to the level of 200 mm waf er.

mined using quantitative statistical methods, such as KLA-Tencor’s CD Sample Planner. More frequent occurrence of certain excursions, a stronger spatial impact of these excursions, and higher field-to-field variation within a wafer are all expected for 300 mm patterning processes. These concerns will reinforce the necessity of more accurate characterization of baseline and excursion statistics through appropriately selecting the sampling plans and control methodology. The utility of carrying an optimal 200 mm sampling plan into the 300 mm fab was evaluated under certain conditions. It was shown that there could be almost 50 percent increase in the fraction of material-at-risk when the fraction of false alarm is held fixed at two percent, by simply implementing the 200 mm sampling plan for a 300 mm fab. Considering the more severe effects of certain types of excursions in 300 mm wafers, this 50 percent increase may cause significant yield loss. Clearly, a careful examination of 300 mm sampling plans is warranted to ensure realization of all the benefit of the larger wafer size. References: 1 . R . E l l i o t t, R. N u r a n i , S . Le e , L . O r ti z, M . P r e i l, G. Shanthikumar, T. Riley, and G. Goodwin, “Sampling plan optimization for detection of lithography and etch CD process excursions,” In Proceedings of SPIE Metrology, Inspection, and Process Control for Microlithography XIV, vol. 3998 (2000) pages 527-536. 2 . B. Charles et. al., “Current state of 300 mm lithography in a pilot line environment,” SPIE conference on Pro c e s s , Equipment, Materials and Contro l, vol. 3882,140-153. 3 . A. J. Maltabes et. al., “ Integrated Metrology: The next logical step for increasing fab pro d u c t i v i t y. ”


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Intelligent Control of the Semiconductor Patterning Process: A NIST ATP Program Update by Matt Hankinson, Ph.D., KLA-Tencor Corporation

This overview provides highlights from the first two years of the Intelligent Control of the Semiconductor Patterning Process NIST Advanced Technology Program (ATP). The three-year, $18 million program is focused on applying Advanced Process Control, including sensors and metrology, statistical analysis, and process control, to reduce variation in polysili con gate critical dimensions.

The patterning process (lithography and etch) is the most expensive process module in the semiconductor manufacturing process, accounting for almost half of the wafer processing equipment costs. The aggressive reduction in features sizes makes patterning one of the most difficult areas to control, and patterning is largely responsible for determining final device yield and product performance. At the same time, the ongoing reduction reduces the device tolerances and the process window, while demanding the patterning of more difficult features. If the process is not manufacturable at high yields, this will significantly increase cost per part. However, if the process can be tightly controlled, then it is possible to manufacture higher-value parts at high yield.

with control algorithms and high-speed data analysis techniques to gain process control in the patterning module. These solutions are being developed and tested by the program team members and suppliers, enabling the semiconductor and related industries to purchase these integrated solutions as products for current or next-generation patterning equipment. Benefits that will be realized as a result of this project include: a) increased product yield as a result of improved repeatability of the patterning tool set; b) increased production efficiency as a result of reduced set-up time and reliance on test wafers; and c) increased productivity by replacing off-line metrology with new in-line metrology. The work in this program will be applica ble to future patterning generations and other potential breakthroughs in patterning technology.

The goal of the Intelligent Control of the Semiconductor Patterning Process project is to improve the gate linewidth uniformity in the wafer patterning process. Technological advances in semiconductor manufacturing are determined by the width, or critical dimension (CD), of the lines that are printed on a wafer. Limits on CD capability are set by the uniformity of the patterning process; a series of processing steps that includes photolithography and etch. It is proposed that a significant reduction in variance can be accomplished by developing and using measurements in the patterning flow, along

We have assembled a team of chip manufacturers, equipment manufacturers, sensor suppliers, software suppliers, and universities to implement a coordinated approach to improving CD uniformity.

Program Overview

This program is conducted by researchers in each of the partner organizations. KLA-Tencor Corporation provides overall technical coordination, with input and wafer processing by Motorola. Contributions from FSI International, a manufacturer of lithography equipment, Lam Research, a manufacturer of etch equipment, and KLA-Tencor, a process control and yield management company, assure that professional and commercially viable approaches will be taken to this work. The involvement Spring 2001

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algorithms for both lithography and etch, and the evaluation of sensors needed to measure control inputs in situ. The selected sensor technology covers the broad wavelength spectrum, DUV (248nm) to IR (25 (m). These sensors will be evaluated for measuring attributes of resist chemistry during processing, wafer surface patterns, etch plasma chemistry, and etch exhaust chemistry, for use as possible control data sources. Model-based feed-forward and feedback control algorithms will be developed to reduce variability in key processing steps for the patterning module.

F i g u re 1: Ga te CD C ontrol Team Part i c i p a n t s

of five universities, University of Michigan, Stanford University, University of California at Berkeley, University of California at Irvine, and University of Wisconsin completes the team (see Figure 1). A number of other companies are involved as subcontractors to the program. The NIST Advanced Technology Program provides support through their funding and technical guidance. Approach

Research in this program is folded into three principal focus areas: Focus Area 1: The first focus area is characterizing variability in the patterning process. This work is focused on a thorough analysis of sources of CD variability. Process sensitivity and controllability of each source are determined for the lithography (resist coating and processing, exposure, reticle, metrology), etch, and etch metrology. Subsequent tasks consist of various modeling approaches relating CD variability to process conditions, and the evaluation of metrology techniques designed to observe these conditions. Metrology techniques including electrical linewidth, scatterometry, and spectral reflectometry, in addition to the existing CD-SEM technology, are used to study wafer variation. The work is being performed in the semiconductor manufacturerâ&#x20AC;&#x2122;s fab, the resist processing and etch labs, and the metrology lab, as well as technology development at the universities. Focus Area 2: The second focus area is reducing variability in the patterning process. Tasks in this focus area are directed to the development of control 66

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Focus Area 3: The third focus area is system integration. This focus area addresses integrating sensors, metrology tools and control algorithms into the process equipment and a commercially viable manufacturing control system. The architecture is based on the APC Framework implemented in Catalyst. Results

There are four basic categories to the results: 1) statistical analysis of time series and variance components; 2) sensor technology for monitoring process parameters; 3) metrology techniques for measuring wafer state and critical dimension; and 4) feed-forward and feedback control algorithms. We are conducting an analysis of sources of CD variation. A detailed CD error budget model is built using baseline process variation statistics and sensitivity studies to measure the impact on CD (see example in Figure 2). A variety of process parameters are measured during the patterning process to establish the baseline variation. We collect this data in conjunction with wafer measurements to correlate process variation with CD variation. Statistical analysis includes assessing nested variance components with systematic and random effects, and spatial and temporal variation. For each nested level (lot-to-lot, wafer-to-wafer, across-wafer, across-field, and across-chip) we separate the systematic and random variation using spatial models and fixed effects. Sensitivity studies of key process parameters are then combined with the baseline statistical variation to construct a model of the impact of each parameter on CD variation. We have also made progress in hidden Markov models for analyzing sensor data. This framework uses a stochastic state-based representation of the process to reduce false alarms and the detection latency by incorporating prior expectations about state changes. The technique can be automated for pattern-based change-point detection.


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for process control applications in lithography.

F i g u re 2: Sources of C D Variation Paret o Char t

The sensor technology progress includes a diode-laser absorption technique for monitoring the concentration and temperature of plasma chemical species. This method tracks the standard optical emission techniques, but has advantages in minimizing cost and window transmission. A broadband RF impedance sensor was also developed and analyzed under various process conditions. This sensor provides chamber condition information for fault detection and optimal maintenance cycles. The plasma etch process was characterized using both sensors. These sensors will be used for further process monitoring applications and possible inclusion in real-time control schemes. CD metrology techniques in this program include scatterometry, electrical linewidth, and spectral reflectometry. Different CD scatterometry techniques have been evaluated and compared with CD-SEM for correlation studies. An in-situ reflectometry method was developed to measure resist CD during plasma etching. Integration methods have also been investigated

We have investigated various strategies for feed-forward and feedback control using CD measurements from the developed resist profile to adjust lithography and etch parameters (see Figure 3). The adjusted parameters initially included dose and etch time, but will be extended to additional parameters. We have also quantified the impact of metrology delay and measurement error on the controller performance. The benefit of wafer-to-wafer control strategies was simulated against lot-based controllers. Despite the low wafer-towafer variance in typical processes, significant benefit is observed from wafer-to-wafer control by quickly centering overall mean for the cassette. Process simulation tools such as PROLITH are used to test control strategies using realistic process parameters. We are also integrating lithography simulation tools for advanced model-based process control strategies. Finally, we have investigated issues related to the collection, storage, and query of sensor, equipment and wafer data for applications in analysis and process control. This work has led to major improvements in the database performance. The program is expected to conclude in mid-2002 with the definition of a comprehensive gate CD control system. We would like to acknowledge the time, resources, and expertise provided by the NIST Advanced Technology Program under project number 98-01-0167, as well as our partners, KLA-Tencor, Lam Research, FSI International, University Michigan, Stanford University, and finally our many participants including Motorola, U.C. Berkeley, U.C. Irvine, U. Wisconsin, On-line Technologies, Domain Logix, and Dynamic Intelligence.

F i g u re 3: Con trol Schematic

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Multi-Beam High Resolution UV Wavelength Reticle Inspection by C.C. Hung, C.S. Yoo, C.H. Lin, Taiwan Semiconductor Manufacturing Company W. Volk, J. Wiley, S. Khanna, S. Biellak, D. Wang, KLA-Tencor Corporation

A new reticle inspection system with three parallel scanning laser beams for UV imaging for both contamination and pattern inspection has been developed to detect defects on advanced reticles for DUV steppers and low k1 lithography for 0.13 µm and extensions to 0.10 µm design rules. The development of the new three-beam architecture at UV wavelength has significantly increased system throughput while improving the resolution of the imaging optics for inspecting advanced reticles including Halftone, Tri-Tone, and Alternating PSM’s and reticles with aggressive OPC. The system is capable of running multiple inspection algorithms simultaneously in transmitted and reflected light to achieve concurrent pattern and STARlight™ inspection, thus improving both sensitivity and inspection thoroughness with a single inspection. These improvements enable fast inspections of reticles for 4X lithography design rules at 0.18 µm, 0.15 µm, and 0.13 µm.

Initial simulations were performed to optimize performance of optical components and a new defect detection algorithm. The simulations identified that with the optics changes to achieve three beam scans and with new algorithms, the inspection was more sensitive to all defect types including on edge contamination defects, which can be particularly difficult to detect. Using both PSL and programmed defect test masks and real production reticles, initial observations of the nature and the frequency of defects detected with this 100 nm sensitivity instrument will be presented. With more defects to review, the system software provides concurrent or remote defect review so time to disposition defects does not effect system inspection capacity. With smaller defects to review, the quality of defect review images has a direct impact on the effectiveness and ease-of-use of reticle inspections systems. The smaller review pixel with the system, combined with a suite of review imaging tools, yields high quality images for defect dispositioning. 68

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Introduction

Reticle inspection has become a key aspect of integrated circuit (IC) manufacturing. As IC design rules shrink below 180 nm, reticle linewidths fall below 700 nm and Optical Proximity Correction (OPC) features present an even greater inspection challenge, as they can be as small as 100 nm. The implementation of low k1 lithography into wafer production is becoming more common as industry design rule roadmaps are accelerating. Reticle inspection systems with smaller linewidth capability, higher sensitivity, and extended capability for OPC and PSM inspection are a critical component to obtaining high yields in low k 1 lithography. Through the use of OPC and phase shifting techniques on reticles, DUV lithography has been extended to support 0.18 µm, 0.13 µm, and 0.10 µm design rules allowing low k 1 lithography to be used as a standard practice. As this practice has become more widely used, it has resulted in reticle specification change — the requirement of a post pellicle pattern inspection in the mask manufacturing operations as a final and comprehensive final check for pattern and contamination defects


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on critical layer reticles. Thus, more inspections are required in the mask manufacturing operations because pattern inspections must be run after pelliclization. New inspection system designs now must not only meet the needs of the next generation design rules for sensitivity and OPC and PSM inspectability, but must also have significant throughput increases to keep the cost per inspection at a production worthy level. The work discussed was a result of the Joint Development Partnership between TSMC and KLA-Tencor to develop a highly productive reticle inspection system for next generation design rules. Inspection is a specific problem created by the new applications of aggressive OPC. Next generation, most advanced reticles using OPC assist features challenge today’s inspection systems. Current inspection systems such as the 305UV system were originally designed years ago when OPC was not widely used in new device designs. As we move into 0.13 µm design rules, OPC assist features will be used as standard practice and inspections must tolerate and inspect these features without false or nuisance defects. In Figure 1 a defect map is shown from the current 305UV reticle inspection system with the 150 nm pixel using the AOP algorithm

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from the inspection of a 0.15 µm / 0.13 µm design rule reticle with aggressive OPC assist features. This map shows an unmanageable number of false and nuisance defects totaling 1400, caused by sub-resolution assist features. Less than 1% of the defects are real defects. If the inspection were to be de-sensed we would not only reduce the false defect count, but also reduce the real defect count, which is unacceptable for the inspection of such advanced reticles with high mask error enhancement factors. This inspection issue must be solved for aggressive OPC inspection for 0.13 µm design rules, otherwise reticle inspection will be a roadblock for advanced reticle designs. System changes

KLA-Tencor’s STARlight inspection tool is today’s industry standard for reticle contamination inspection. The STARlight architecture has been extended to the new TeraStar system, which is designed to meet pattern and contamination inspection requirements for 0.13 µm design rules for production, and 0.10 µm design rules for research and development. The term Tera represents the system’s ability to inspect one tera-pixel (one million x one million pixels). The term Star is an acronym for Simultaneous Transmitted and Reflected Light, meaning that both the transmitted light response and the reflected light response are used on the system for defect detection. To meet these requirements, the new TeraStar inspection architecture includes1: • an increased numerical aperture as a standard feature, improving the inherent resolution of the system and thus improving its defect detection sensitivity • replication of the UV beam into three parallel scanning beams, significantly increasing the system throughput • a new optics bench with improved alignment features • reduced system vibration to increase the signal-tonoise ratio to improve defect detection capability • a new die:die algorithm, XPA, operating on a new image computer for multi-beam inspection of pattern defects for better OPC inspectability • a new STARlight algorithm, TR412, for multi-beam contamination inspection

F i g u re 1. 305UV Defect Map p15 0 pixel AOP315.

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Using this new architecture, the TeraStar inspection system was developed. The optical characteristics of inspection were identified to be different with multiple inspection beams, and therefore it was critical to system design to perform the following: • investigate the differences of multi-beam and single beam UV inspection through computer simulations. • based on these findings, create new algorithms for optimizing defect sensitivity with the new multibeam optics.

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• evaluate each of the algorithm options developed and determine which has optimum performance. The new optics architecture is shown in Figure 2. Like the 300UV system, this system also uses active beam steering for better reliability and performance. Unlike the 300UV system, all subsystems of the TeraStar are included within the inspection station, with the exception of the user interface. This is a table top monitor and keyboard placed nearby the system. All facility components and image computing components are within the inspection station

F i g u re 2. Multi-beam optics over view an d concurrent a lgorithm s fo r pattern and cont amination defect detection.

System Changes and Associated Benefits Challenges Detect smaller contamination Inspect smaller design rules Inspect OPC assist bars/slots Inspect half tone PSMs Inspect Tri-tone PSMs

Software New multi-beam UV algorithms Methods to tolerate assist features Improved overall signal:noise ratio On edge defect detection optimized Multi-edge calibration for Tri-tone PSM

This development project was different from others because it focused on increasing defect sensitivity through reducing the K d of the inspection system by improving algorithms and signal:noise ratio (see Figure 3). Most 70

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Results Inspects 0.13 µm, 0.10 µm designs Contamination sensitivity of 0.10 µm Hard defect sensitivity of 0.10 µm Zero false defects on OPC assists Tri-tone PSM inspection

other projects have focused on moving to either a smaller inspection wavelength or to a higher numerical aperture for increasing system sensitivity.


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F i g u r e 3. The K d factor a nd the relationshi p b etween λ, NA and defect size.

Observations

Simulations were previously reported for UV inspection1, where the behavior of the single beam UV inspection system was studied with respect to image quality, sensitivity, and advanced OPC and PSM capabilities. Figure 4 illustrates the results of optical simulations of the single beam UV inspection on a binary reticle across a chrome/quartz edge. The vertical axis is the reflected light signal and the horizontal axis is the response position offset in reference to the chrome edge at 0.5 µm. The simulations modeled the optical path of the two inspection systems to the finest detail. Figure 1 shows a clear difference in near-edge signal modulation between the 488 nm STARlight system and the 364 nm UV STARlight system. This difference is called the UV on Edge Effect (UEE). Because of this difference, new algorithms were investigated for the implementation and optimization of UV inspection. For this project, simulations were performed for the new multi-beam UV optics to study the UV on Edge Effect. Figure 5 illustrates the results of optical simulations of the multi-beam UV inspection on a binary reticle across a chrome/quartz edge. The reflected light edge response of the new multi-beam system is better than previous generation systems. With this smoother transition across an edge, the algorithms will perform more reliably and will have better repeatability of finding defects on the quartz side of an edge. This improvement is targeting transmission and contamination defects near edge.

F i g u re 4. UV ins pection optical si mulation results across a c h ro m e / q u a r tz edge.

In addition to optimizing the inspection algorithms for the UEE, the XPA algorithm was optimized for the inspection of aggressive OPC features, including assist features. The design rule of the reticle image shown in Figure 6 is 0.15 µm. At DUV lithography the k1 for this process was less than 0.45, which would cause this programmed OPC defect to print to the wafer. This pin dot defect class may not be new to reticles. But, at the low k 1 lithography and in aggressive OPC these defects will cause yield excursions in wafer fabs. Many OPC programmed defect images were used to help optimize the algorithm performance using the algorithm test bench, a key development to for fast feedback on algorithm changes to allow fast algorithm optimization. Spring 2001

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image and the transmitted reference image. The images of four defects are shown in Figure 7. Defect A is a very small chrome extension on a primary feature next to neighboring OPC assist features. The new generations of Tera algorithms, including XPA, are not vulnerable to sub-resolution OPC assist features. Assist features do not degrade the inspection system performance. Defect B demonstrates the system’s capability of detecting small defects on OPC assist features. This particular defect is a chrome extrusion on the inside of assist feature facing a primary feature.

F i g u re 5. Multi-beam UV inspection optica l s imula tion results acros s a c h ro m e / q u a r tz edge.

Initial characterization

The sensitivity of the TeraStar inspection system has been initially characterized. Using the new XPA algorithm, the inspection issues caused by OPC assist features at the 0.13 µm design rule are no longer a barrier for inspection. Figure 7 shows the defect map of the 150 nm pixel inspection on the same TSMC OPC reticle with 0.15 µm and 0.13 µm design rules with aggressive OPC assist features as was shown earlier in Figure 1 using the current generation 305UV inspection system. On TeraStar, with the XPA algorithm and the 150 nm pixel, there are no false defects and 26 real defects, which is more than twice the real defects found on the current generation 305UV system. There are four defect images shown in the review screen image for the die:die pattern defects detected. The review screen shows both the transmitted test

Pindot between OPC serifs line ends.

F i g u r e 6. Scanned UV In spec tion image of OPC.

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Defect C shows that even short assist features will not impact the inspection’s ability to run without false or nuisance defects. TeraStar tolerates even short OPC assist features without de-sensing the inspection to real defects on the primary geometry of the reticle. Defect D shows the system is tolerant not only of thin chrome assist features, but also of thin clear assist features with out false or nuisance defects, and without de-sensing the inspection performance. This defect is very small, but if it were located on the other side of the assist feature may impact CD. Immediately following this inspection of the TSMC OPC reticle, a sensitivity verification test used the same sensitivity settings for the XPA algorithm and was run on the Verithoro 5491 test reticle with the 150 nm inspection pixel. System sensitivity was verified at 100 nm using this test reticle. The programmed defects on the Verithoro 5491 test reticle are sized using the 8100XP-R reticle CD SEM system. The Verithoro 5491 is the standard acceptance test plate which monitors system sensitivity to chrome defects, and monitors system susceptibility to false and nuisance defects. It is currently used for testing the 150 nm pixel inspection on the current generation 305UV systems. It uses geometry as small as 540 nm and has may defect types as illustrated on the right side of figure 8. In Figure 8 the results show that the system fully meets its sensitivity specification of 100 nm for all programmed defects types on the Verithoro 5491 test reticle. The new TeraStar target specification is 100 nm defect sensitivity, and is shown by the red line. In this case, the defect sensitivity using the XPA algorithm meets or exceeds the 100 nm sensitivity requirement for each defect type.


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F i g u re 7. Defect ma p a nd images from Tera Star inspection of the TSMC OPC reticle from Figure 1.

Using the same die:die sensitivity data from the TeraStar system, the sensitivity chart, (Figure 9) compares the 305UV system performance to that of TeraStar. As expected, the 305UV system, with the current AOP315 algorithm, performs to the 120 nm defect sensitivity specification with the 150 nm inspection pixel. The new XPA algorithm of TeraStar significantly improves defect sensitivity at the same 150 nm inspection pixel. By design, the XPA algorithm has a better defect:pixel performance ratio.

available on the older 488 nm wavelength inspection system). By using the VT5491 test mask for this test, the sensitivity is compared. The linewidth capability of the XPA algorithm is also compared to the XPA algorithm. TeraStar outperforms the 300 series in sensitivity, while also running the VT5491 test reticle with no false or nuisance defects. A total of 116 false and nuisance defects appear on the 300 series because the APA algorithm was not designed to run such small geometry when the system was developed years ago.

The next sensitivity test compares the mid-range, die:die sensitivity of the TeraStarâ&#x20AC;&#x2122;s 250 nm pixel inspection to that of the 300 series 250 nm pixel (the smallest pixel

XPA does not have the same three pixel wide linewidth limitation as the older generation algorithms.

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TeraStar performance specification for defect sensitivity down to 100 nm

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TeraStar performance 300 Series performance

Actual

F i g u re 8. Sens itivity verification of th e TeraStar usi ng VT5491 test

F i g u r e 9. Sensitivity verificat ion of the TeraStar using VT 5491 test

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reticle.

Other inspections

During the development of the TeraStar system, many advanced reticles were inspected as part of the standard in-house characterization. Many reticles were of 0.15 um and 0.13 um design rules. Figure 11 shows the capability of the XPA algorithm to detect CD defects. The defect shown is a 80 nm CD defect over a number of SRAM cells probably caused by a large area resist thickness variation. The difference image is a selection on the review menu to help enhance the CD defect area and highlights all the defective pixels found by the inspection system. The XPA algorithm has better sensitivity to CD defects compared to the AOP algorithm of the 300UV series.

TeraStar actual performance 305UV performance TeraStar performance specification

F i g u re 10. Sensitivity co mparison of the TeraStar us ing V T5491 test

On the same reticle shown in Figure 12, the TeraStar system found stitching errors, which are misplaced shots from the pattern generator, using the new XPA algorithm. The stitching error can be seen in the right image and is a vertical offset on five horizontal edges. Shown in figure 12 is the transmitted light image of the test and reference die.

reticle.

The TeraStar system is also capable of inspection of PSM reticles. Shown in Figure 13 is a defect on an embedded attenuator reticle. This reticle is a tri-tone 74

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Transmitted Image - Reference Die Transmitted Image - Test Die

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Difference Image between Die

F i g u r e 11. CD d e f e c t .

Conclusions

The results of the TeraStar development program: • Freedom from inspection limitations caused by aggressive OPC designs on advanced reticles. • Improved defect sensitivity to 100 nm through improving Kd — signal:noise and algorithm performance.

F i g u re 12. Stitch ing error c aused by pat ter n genera tor.

• Linewidth capability is better than previous generations reticle inspection systems for die:die inspection, not just by pixel, but the linewidth:pixel ratio is improved significantly. Defect sensitivity is maintained at smaller linewidths. • Multiple inspection beams and concurrent inspection drives the cost per inspection and cost of ownership lower for the TeraStar reticle inspection system. These capabilities are a perfect fit for comprehensive final post-pellicle inspections at the mask shop or an incoming inspection in wafer fabs.

F i g u r e13. Chrome extension on top of attenuat or.

reticle, and the defect shown is a chrome extension on top of a high transmission MoSi attenuator material.

Acknowledgment

The authors would like to acknowledge Steve Hentschel and Chris Aquino of KLA-Tencor. Reference 1 . “High Resolution UV Wavelength Reticle Contamination Inspection”, F. Kalk, W. Volk, J. Wiley, S. Watson, E. Hou., SPIE Vol. 3748, p. 513-519.

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Impact of Reticle Corner Rounding on Wafer Print Performance by Chris A. Mack, KLA-Tencor

Pattern fidelity of features on the wafer is critical to the functionality of a device. Among other error sources, the feature quality on the reticle is presumed to be a key contributing factor to wafer pattern fidelity. Of course, optimization of final pattern fidelity is dependent on the imaging and process of both the mask and wafer, as well as on their relationship to one another. This paper examines the key parameters that contribute to wafer pattern fidelity through simulation. Results from this work will be used to predict the acceptable amount of corner rounding on the reticle, and to define proper metrics of reticle shape. Pattern shapes such as isolated corners, contact holes, and line ends will be examined. For line end shortening, the influence of both the imaging and the resist process is discussed..

Introduction

In wafer lithography it is convenient to assume that the reticle is an ideal representation of the design data, and that corner rounding of the final printed wafer pattern is due only to the diffraction limitations of the imaging and other processing effects, such as PEB diffusion. In reality, however, the reticle itself suffers from corner rounding which must, to some lesser or greater degree, affect the printed wafer results as well. How does reticle corner rounding contribute to loss of wafer pattern fidelity? How much reticle corner rounding is acceptable? Does reticle corner rounding affect the focusexposure process window of the wafer patterns? How much does the resist process contribute to corner rounding? How does corner rounding relate to effects such as line end shortening? These are important questions to answer, considering the cost trade-offs associated with printing reticles with less corner rounding1 and the impact of wafer pattern fidelity on device performance. Since firmly establishing the implications of mask corner rounding for all pattern types and sizes is a daunting task, a first 76

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step is to consider simple cornered mask features such as an isolated corner, a contact hole, and the end of an isolated line. It is well known that when contact hole wafer dimensions are less than about 1.0λ/NA (where λ is the imaging wavelength and NA is the objective lens numerical aperture), the nominally square holes print as circles on the wafer due to the diffraction limits of the imaging tool2. It seems logical that, in this common and important case, the shape of the printed wafer results is not directly affected by the amount of corner rounding on the mask. It is not clear, however, how mask pattern shape affects the size and process window of the wafer patterns. Using KLA-Tencor’s PROLITH/3D lithography simulation software and Klarity ProDATA with the SEM Image Analysis Model for examining actual reticle patterns, this paper examines the key parameters that contribute to wafer corner pattern fidelity through theory and simulation. The impact of reticle corner rounding on the printed wafer patterns will be examined for conventional and attenuated phase shifted contact holes of various pitches. Results from this work will be used to predict the acceptable amount of corner rounding on the reticle, and to define the proper metric of reticle shape. Finally, the impact of the resist process on corner rounding, and line end shortening in particular, will be described.


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Theory

In the Fourier Optics view of imaging, light passing through a photomask propagates to form a diffraction pattern that is the Fourier transform of the mask transmittance. The diffraction pattern is made up of “spatial frequency” components, high frequencies corresponding to large diffracted angles. The objective lens then acts as a low pass filter, throwing away frequencies higher than the cut-off of the lens (the numerical aperture divided by the wavelength, NA/λ). Any feature on the mask can be broken up into its frequency components, knowing that the higher frequencies will inevitably be lost. A good example is a corner, a 90° junction of two edges of chrome. The sharp corner represents an infinite range of spatial frequencies. Once the diffraction pattern passes through the lens, however, the loss of the high frequency components results in an image with a rounded corner. How much does the corner round? For an isolated corner imaged with coherent light, the radius of the corner of the aerial image is about 0.36λ/NA. The use of partially coherent imaging changes the amount of corner rounding, but only slightly. The lithographic impact of this corner rounding often depends on the proximity of the corner to other features, in particular to other corners. Consider two corners next to each other, that is the end of a line. If the linewidth is more than twice the corner rounding radius (i.e., about 0.7λ/NA), then each corner will have only a small influence on each other. If the linewidth is less than this amount, the rounding of the two corners will overlap, resulting in line end shortening.

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The actual effects are somewhat more complicated due to the coherent interaction of the aerial images from each corner. A more extreme case is the interaction of four corners to make a small island or contact hole. The result is familiar to anyone who has ever printed such features: square contact hole mask patterns (less than about 1.0λ/NA in width) always print as round holes on the wafer2. Since the result is inevitable, this type of corner rounding is not considered a problem. For small contact holes, the aerial image projected by the imaging tool is governed essentially by the point spread function (PSF) of the tool. Defined as the image of an isolated, infinitely small pinhole on the mask, the PSF determines the smallest contact hole that could be printed with conventional imaging. For an ideal, diffraction limited imaging tool, the width of the PSF is about 0.66λ/NA3. Thus, contact holes on the mask with sizes less than this value will not print smaller than the PSF, but will be limited by the PSF width. In fact for contact holes near this limit, the main impact of changing reticle size is simply a reduction of the peak intensity of the contact hole image, which will be proportional to the area of the reticle contact. With the above description in mind, if two small contact holes have different shapes but the same area, it seems likely that they would produce similar aerial images. To test this idea, consider the two extremes of contact hole corner rounding, a square and a circle. The area of the two are kept constant by making the width

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F i g u re 1. Diff ractio n pat ter ns for ( a) a square contact hol e mas k pattern, and (b) a ci rcular cont act hole ma sk pattern.

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of the circle equal to √4/π times the width of the square. As a common and important example, consider a nominal 150 nm contact hole (wafer dimensions) imaged by a 0.7 NA, 248 nm imaging tool (making k1 = 0.423). We can begin by simply examining the diffraction patterns of the square and circular contact holes. The square will produce a diffraction pattern that is the product of two sinc functions, while the circle will produce a Bessel diffraction pattern (Figure 1). Examining a horizontal cross-section of the diffraction patterns in more detail (Figure 2), one can see that the central portions of the two diffraction patterns are nearly identical. The differences lie mostly in the high spatial frequency region.

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The diffraction patterns of Figures 1 and 2 pass through the low pass filter of the objective lens, cutting off all spatial frequencies greater than NA/λ and less than -NA/λ. The product of this spatial frequency cut-off and the nominal contact hole width is k1. Thus, for the example given here with k1 = 0.423, the cut-off of Figure 2 occurs at ±0.423. One can see that in this narrow region of low spatial frequencies the two diffraction patterns are nearly identical. Thus, one would also expect the resulting aerial images to be nearly identical as well. Aerial image simulations, contact holes

Aerial image simulations were performed using PROLITH/3D v6.1 using the High NA Scalar model4 and λ = 248nm, NA = 0.7, no aberrations or flare, σ = 0.4 or 0.7, and 4X reduction. All mask contact hole patterns were adjusted to have an area of 150X150 nm, with corner rounding varying from a corner rounding radius of 0 (square mask) to 84.6 nm (circular mask). Pitch was varied from dense (300 nm), to semi-dense (450 nm) to isolated (1500 nm). For the attenuated PSM case, the background intensity transmittance was six percent and only the semi-dense pitch was examined.

F i g u re 2. Comparison of horizontal cross-sections of the Bessel (circ u l a r mask) and the sin c (square mask) diff raction pat ter n s .

Figure 3 shows a representative aerial image result. As a function of reticle corner rounding radius the resulting aerial images varied only slightly. In fact, the only variation was in the value of the peak intensity at the center of the contact hole. Figure 4 shows the peak intensity as a function of corner radius, with a total variation of only 1.4 percent. In fact, all of the cases studied showed identical trends where the only perceptible change in the

F i g u r e 3. Aerial image res ults as a function of cor ner rounding radius (σ = 0.4, iso lated binar y contacts) shown at two di ff e rent graph scal es.

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Resist simulation results, contact holes

Three-dimensional resist simulations were carried out with PROLITH/3D using the conditions given above and using 410 nm of UV6 resist on 60 nm of AR2 on silicon and with a 125°C, 60 second post exposure bake. A typical example (Ď&#x192; = 0.4, isolated binary contacts) comparing square and completely circular contacts is shown in Figure 5. There is no perceptible difference

F i g u re 4. Varia tion of the p eak intensity of the a erial i mages of Figure 3 as a fun ction of corner roundin g s hows only a 1.4% chan ge.

aerial image was an increase in the peak intensity as a function of corner rounding. The worst case range of intensities was 2.3 percent (for both the dense contact and the semi-dense attenuated PSM contact). Although there was no perceptible change in the widths of the aerial images as a function of corner rounding, this small change in peak intensity has some impact in the final printed results.

F i g u re 6. Variati on of t he resist cont act hole C D for the aeri al images of Figure 3 as a func tion of corner roundi ng shows a 2.5% ch ange.

in resist profile shape and only a slight difference in resist contact width. Figure 6 shows how the critical dimension of the contact hole varies with the amount of corner rounding. Interestingly, the 1.4 percent variation in aerial image peak intensity leads to a 2.5 percent variation in resulting CD, showing the importance of the image center intensity in determining linewidth.

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Of course, the effects of mask corner rounding on the printability of the pattern in resist at nominal dose and focus tells only a part of the story. Figure 7 shows exposure latitude (CD through exposure) both in and out of focus for the same square and round mask patterns as the previous figures. Other than the 2.5 percent offset in contact width, the process responses of the two mask patterns are nearly identical. Thus, mask corner rounding seems to have no affect on the size of the process window for these features. Aerial image and resist simulations, line end shortening

(b) F i g u re 5. Resist profi le simulat ions for (a) a square mask, and (b) a p e rfectly circular mask, both with the same contact hole area on the mask.

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F i g u r e 7. The process res ponse (exposure la titude in and out of focus) of the con tact holes for both squar e and round ma sk pattern s s hows t hat ma sk corner rounding for these fea tures d oes not significantly a ffect the size of the conta ct hole process wi ndow.

90º corners. But as these corners pass through an imaging process of limited resolution, the corners will, by necessity, round. If the feature width is less than the sum of the two corner rounding radii, the end of the line will pull back due to this corner rounding. Thus, line end shortening can be used as a measure of the effects of corner rounding in a more easily measurable way. The primary corner rounding, and thus line end shortening, mechanism is the diffraction limits of aerial

F i g u r e 8. L a rger numeric al aper t u re s reduce the loss of image f idel ity due to dif fra cti on, producing less line end shor tening (18 0 nm line, λ = 2 48nm, σ = 0.5).

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F i g u re 9. P a rtial coherence sh ows a somewh at discontinuous imp act on th e aeria l i mage line end shor tening (18 0 nm line, λ = 248nm, NA = 0.688).

image formation. As an example, a 180 nm isolated line imaged at 248nm with a numerical aperture (NA) of 0.688 (giving a scaled feature size of k1 = 0.5) and with a partial coherence of 0.5 will produce an aerial image with nearly 50 nm of line end shortening (LES). The amount of corner rounding is a strong function of k1. Figure 8 shows the effect of NA on the line end shortening of the aerial image of a 180 nm sized structure. Obviously, a higher NA (just like a lower wavelength or larger feature size) produces less LES. The influence of partial coherence (Figure 9) shows an enigmatic behavior that is characteristic of its seemingly unpredictable impact on partially coherent imaging. Does the resist affect the final degree of line end shortening? Interestingly, development contrast seems to have only a small influence on the amount of LES of the final resist patterns. Diffusion during PEB, on the other hand, has a very significant effect. Figure 10 shows the simulated result of increasing diffusion length (for an idealized conventional resist) on the line end shortening. The diffusion length must be kept fairly small in order for diffusion to only marginally impact the line end shortening. The reason for the large effect of diffusion on line end shortening is the three-dimensional nature of the diffusion process: at the end of the line, chemical species from the exposed areas can diffuse from all three sides of the line end (as opposed to one direction for a line edge).


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Further, simulations through focus and exposure show that the amount of mask corner rounding has very little effect on the size of the resulting process window.

F i g u re 10. D i ffusion can h ave a drama tic effect on line en d short e n i n g (180 nm line, λ = 248n m, NA = 0. 688, σ = 0 .5).

Results and conclusions

In this paper, the impact of mask corner rounding on the wafer printing results was examined for a specific high resolution contact hole pattern: 150 nm contacts printed at 248 nm with NA = 0.7. The pitch of the contacts was varied between dense and isolated, the partial coherence was changed from moderately low (0.4) to moderately high (0.7), and semi-dense attenuated PSM contacts were also examined. For each contact hole type, the amount of mask corner rounding was varied between a perfectly square contact and a perfectly circular contact, being sure to keep the area of each mask pattern equal. All contact mask patterns were studied using simulation to predict the printed wafer results.

From these results, one can draw several conclusions. First, although the impact of mask contact corner rounding radius on final resist CD is small, it is not negligible. If the corner rounding radius on the mask varied by about 20 nm across the plate, the results would be a 1 percent final wafer CD variation for the conditions shown here. Thus, the control of corner rounding uniformity should be considered in the mask making process. Second, the key conclusion is that the impact of mask corner rounding is completely dwarfed by the effect of the area of the contact hole on the mask. The peak intensity of the aerial image of a small contact hole is proportional to the area of the contact hole on the mask (“small” being defined as on the order of or smaller than the width of the point spread function of the imaging tool). To first order, the area of the mask contact hole pattern is the only variable of importance. In fact, it has been proposed that, for small contact holes, the effective mask critical dimension be defined as the square root of the area of the mask pattern5: effective mask contact CD = √contact hole area When printing small contact hole mask patterns, all efforts should focus on controlling the effective mask contact hole CD. For this reason, Klarity ProDATA with the SEM Image Analysis option has been equipped with the capability to perform such area measurements and effective contact CD calculations (Figure 11). Using

Aerial image simulation results show that mask corner rounding produces only a slight variation in the shape of the aerial image. Rounder contacts are slightly brighter than squarer contacts of the same area. Clearly, the square corners have the effect of diffracting a little more light into higher spatial frequencies, reducing the total energy passing though the objective lens. The impact is reasonably small, with peak intensities of the resulting images varying by only 1.4 percent to 2.3 percent over the range of pitches studied. Note that the widths of the aerial images are unaffected by the mask corner rounding. Resist images show essentially the same behavior as the aerial images. The small variation in aerial image peak intensity results in a somewhat larger variation in final resist CD. The shape and cross-section of the resist images remain unchanged with mask corner rounding.

F i g u r e 11. Klarity Pro D ATA wi th the SEM Image Ana lysis option can automatica lly calcula te the effective contact CD from a KLA-Te n c o r 8250R SEM image th rough a combination of i mage pr ocess ing and edge detection t o create a critical s hape r e p resentation of the feature .

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the KLA-Tencor 8250R SEM, images of reticle patterns can be automatically analyzed by Klarity ProDATA for corner rounding and contact area, as well as comparison with design or wafer images. Two major mechanisms produce line end shortening. The fundamental limits of diffraction round the corners of aerial images producing a foreshortened line end for small features. This aerial image shortening is compounded by diffusion, attacking the line end from three sides. The result can be a significant amount of line end shortening that is both image and process related. References

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2 . C. A. Mack and J. E. Connors, “Fundamental Diff e re n c e s Between Positive and Negative Tone Imaging,” O p t ical/Laser Microlithography V, Pro c . , SPIE Vol. 1674 (1992) pp. 328-338, and M i c rolithography Wo r l d , Vo l . 1, No. 3 (Jul/Aug 1992) pp. 17-22. 3 . C. A. Mack, “The Natural Resolution”, M i c ro l i t h o g r a p h y Wo r l d (Fall, 1998). 4. C. A. Mack, Inside PROLITH: A Comprehensive Guide to Optical Lithography Simulation, FINLE Technologies (Austin, TX: 1997). 5. C. A. Mack, C. Sauer, S. Weaver, and J. Chabala, “Lithography Performance of Contact Holes - Part II: Simulation of the Effects of Reticle Corner Rounding on Wafer Print Perf o rmance,” Photomask and X-Ray Mask Technology VII, P ro c . , SPIE Vol. 4066 (2000) pp. 172-179.

1. S. We a v e r, M. Lu, J. Chabala, D. Ton, C. Sauer, and C. A. Mack, “Lithography Performance of Contact Holes - Part I. Optimization of Pattern Fidelity Using MPG and MPGII”, these pro c e e d i n g s .

KLA-Tencor Trade Show Calendar March 12-13

FLAVS/FSM, Orlando, Florida

March 28-29

SEMICON China, Shanghai, China

April 1

Photomask Japan, Yokohama, Japan

April 19-20

AEC/APC, Dresden, Germany

April 24-26

Quality Expo, Rosemont, Illinois

April 24-26

SEMICON Europa, Munich, Germany

May 27-30

ECS/ISTC, Shanghai, China

June 4-6

IITC, San Francisco, California

July 16-18

SEMICON West, San Francisco, California

July 18-20

SEMICON West, San Jose, California

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Product News Archer 10

Latest in KLA-Tencor’s suite of optical metrology overlay tools, the Archer 10 incorporates several significant improvements in automation, throughput, productivity and precision over previous generation systems. This system is one of the industry’s most competitive cost-of-ownership overlay solutions for 300 mm manufacturing at the sub-0.13-micron node. The Archer 10 provides the increased precision and accuracy lithography process engineers need to control their overlay error budget for sub-0.13-micron device production. Its industry-leading throughput of up to 150 200 mm wafers per hour and 120 300 mm wafers per hour represents a 30 percent increase over previous generation tools. Features include new optics components such as a digital camera, improved algorithms, better optics lenses and a fragmented optics sensor.

PROLITH 7.0

PROLITH 7.0, the latest version of KLA-Tencor’s industry-leading PROLITH lithography simulation software, contains many enhancements to functionality, ease of use, execution speed and accurate lithography simulation from mask to wafer. PROLITH 7.0’s new Simulation Queue allows monitoring and parameter adjustment mid-process without affecting the entire simulation, as well as naming and saving the complete simulation set for future work. Connection to Klarity ProDATA V.12 AutoTune(tm) module produces more precise, accurate analysis of experimental data using PROLITH 7.0 models as the data-fitting function, fine-tuning uncertain simulation parameters to match measured results to a given lithographic process. With these significant new process analysis and lithography modeling capabilities, PROLITH 7.0 provides the increased speed and accuracy to optimize the simulation process and reduce time to market, maximize yields and increase lithography capital utilization.

Klarity ProDATA AutoTune™

AutoTune, the new auto-calibration analysis module option for KLA-Tencor’s Klarity ProDATA software, combines ProDATA’s data-fitting and analysis capabilities with the physically correct lithographic model simulations of PROLITH 7.0. This package gives users a model with enough physical relevance to ensure the applicability of simulation results for developing and optimizing the most advanced lithography processes. By automatically adjusting and fine-tuning uncertain simulation parameters for the best match between PROLITH 7.0 simulations and a given set of experimental lithographic data, AutoTune more accurately simulates the lithography process. Extrapolation from one data set to another is reliably straightforward and can be done without the need and expense of running every case experimentally. This extendibility provides enormous time and money savings for the industry. Spring 2001

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When it comes to copper yield, we have all the right elements. Especially if you’re interested in getting to high-volume copper production faster than anyone else. In fact, we recently helped a major fab do just that. By getting fast and accurate feedback on a yield-limiting problem in their 0.13µm copper process, engineers were able

For more about how we helped a leading copper fab dramatically shorten its time to yield, visit www.kla-tencor.com/copper.

to decrease defectivity by 10X in a single month. Which let them ramp to production faster. And hit ROI sooner. But helping accelerate yield is our specialty. So it’s no wonder that more successful fabs are turning to us. Must have something to do with our chemistry. For more information, please visit www.kla-tencor.com, or call 1-800-450-5308. ©2001 KLA-Tencor Corporation

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