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The Limiting Factor Yield Loss in Lithographic Patterning at the 65-nm Node and Beyond Kevin M. Monahan, Brad Eichelberger, Matt Hankinson, John Robinson, and Mike Slessor, KLA-Tencor Corporation

Parametric yield loss is an increasing fraction of total yield loss. Much of this originates in lithography in the form of pattern-limited yield. In particular, the ITRS has identified CD control at the 65 nm technology node as a potential roadblock with no known solutions. At 65 nm, shrinking design rules and narrowing process windows will become serious yield limiters.

Pattern-limited yield

Pattern-limited yield is perhaps the greatest challenge to semiconductor manufacturing at the 65 nm node and beyond. The root-cause is a design-to-process yield gap originating from the interaction of more complex designs with shrinking lithographic process windows1. Using past trends and pinning to recent yield data, we can generate a model for pattern-limited yield2, as shown in Figure 1a. Projection of pattern-limited yield to the 32 nm technology node indicates a need for innovation in addressing a growing design-to-process yield gap in early production. On the other hand, the

projections for mature defect-limited yield are still relatively high. An 85 percent yield entitlement for mature 140 nm DRAM production would lie directly on the curve, yet the yield-dollar impact of 3-6 month pattern-limited yield delays can cost manufacturers tens of millions of dollars per product. Memory speed deficits and time-to-market delays impact initial average selling price and die cost, drastically reducing ROI for 300 mm factories. Below, we expand on the specific cost and performance issues for each semiconductor manufacturing segment3.

Memory Reduction of cost per bit at memory manufacturers is traditionally accomplished by design rule shrinks and, more recently, by 300 mm wafer manufacturing.

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Figure 1a. Rapidly shrinking process windows have created a pattern-

Figure 1b. CD limited yield is a key contributor to yield loss in early

limited yield crisis in early volume production. Future designs must take

volume production. In addition to losses from gate leakage and device

into account much tighter margins if they are to yield on silicon.

speed, there is an increasing contribution from “hidden error�.

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Shrinks generate bit cost reductions as high as 45 percent per year. In addition, a 30 percent cost advantage may be realized with 300 mm wafer manufacturing assuming yields are comparable to those on 200 mm wafers. As a result, memory makers constitute the largest single market for 300 mm equipment, estimated to be $1.8B in Q3 of 2004. Companies that cannot manufacture on 300 mm wafers or yield at 90 nm design rules will find it difficult to remain competitive. Key challenges at 90 nm will be device yield, speed distribution, and return on investment. Achieving high pattern-limited yield in early production is becoming more difficult due to higher aspect ratios and the increased number of layers with critical CD and overlay requirements.

Furthermore, PC markets are driving bandwidth requirements steadily upward to better match the capabilities of state-of-the-art microprocessors. Since memory markets are relatively inelastic, poor forecasting and subsequent overproduction can drive prices down rapidly, diminishing return on investment. In early 2003, overproduction created such severe price erosion for DDR memory that, for a while, it was less expensive than its low-bandwidth SDR counterpart.

fortunate few build 300 mm factories that are either wholly owned or joint ventures. After the memory makers, foundries constitute the second largest market for 300 mm equipment, estimated to be $1.4B in Q3 of 2004. A single 300 mm factory with capacity of 30K WSPM is expected to cost about $3B, generate product revenue of $6B, and provide foundry revenue of $2.4B. At the 130 nm technology node, 300 mm production yields are now at parity with 200 mm yields.

The cost and performance risk is primarily at 90 nm and beyond, where yield is no longer limited by random defects. At these dimensions, yield is limited by patterning error arising from the interaction between more complex designs and shrinking process windows. The growing design-to-process yield gap will require more design for manufacturability (DFM), more APC, and more sophisticated stand-alone and integrated metrology to reduce time-to-correction. At 90 nm, mask costs of $1.2M per set are likely to be overshadowed by design costs, which are estimated at $30M per product. At 65 nm, both design and mask costs could double and drastically reduce profit margins and ROI for low-volume chips.

Microprocessor

Fabless

Profitability in microprocessor production is a strong function of product performance, and small improvements can result in large price increases. While automated yield management and integrated production scheduling are rigorously practiced, advanced process control (APC) has emerged as the key to rapid improvement in performance. For APC, using available process and metrology tools, incremental ROI typically ranges from 10 to 100. The most common example is gate CD control with feedback to lithography or feedforward to etch. Going forward, pattern-limited yield will become increasingly dependent on aggressive L-effective control schemes that include spacer, implant, and anneal modules and that also attempt to modify upstream disturbances. Key benefits are improved factory throughput, optimized device speed, and consistent parametric yield. In addition, APC is expected to ease the transition to manufacturing on 300 mm wafers. Future implementations may incorporate both cross-wafer and cross-field control, with the goal of eliminating nearly all systematic process variation in both CD and overlay. Pattern-limited yield entitlements should improve significantly as a result.

Fabless semiconductor companies rely on foundries to make their products. Such reliance creates an inherent business risk since there is no guarantee of timely manufacturing capacity or high yield on first silicon.

For example, a foundry achieving 80 percent yield may only guarantee half of that amount to the fabless customer, exposing the customer to a 100 percent variation in die cost. For this reason, some fabless companies partner with more than one foundry and become adept at parametric yield analysis and prediction, especially for short-run production. Since parametric specifications for drive current, gate leakage, threshold voltage, and contact resistance depend on lithography and etch processes, pattern-limited yield in short-run production is a key determinant of profitability. Indeed, one fabless company holds the patent for a novel “sea of ring oscillators� used to correlate device speed and CD variation across a full-field chip4. In future generations, these large chips will have more than one billion transistors. DFM is, therefore, a key strategy for both fabless companies and their foundry partners. DFM is especially important, since performance improvement through process is becoming progressively more difficult. The key challenges are that threshold voltage is no longer scaling with shrink factor, gate delay is no longer scaling at the historical 25% rate, off-current scaling is nearly flat, and total power dissipation may actually rise at the

Foundry Die cost at foundries is expected to fall as more companies implement 90 nm manufacturing, and as the

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65 nm technology node. From a business perspective, however, fabless companies enjoy the advantage of relatively low fixed manufacturing costs. At low and medium volumes, fabless FPGA products are highly competitive with their ASIC counterparts.

Lithography Lithography is a cross-cutting technology for virtually all semiconductor manufacturing segments. The cost of lithography is concentrated in two areas: the cost of the exposure platform and the cost of the mask technology needed to support it. Resolution enhancement technology (RET) for masks is based on a myriad of complex OPC and PSM options. The incremental ROI for RETs is simply the ratio of the yield-dollar-benefit to the cost, but optimum ROI is strongly dependent on type of product, average selling price, and production volume.

In general, a high-volume, high-performance microprocessor would justify substantial attention to RET. On the other hand, yield might be traded for lower mask cost on a short-run foundry product. Some of the lost yield may be recaptured in less expensive ways by matching masks to specific scanners that have suitable process windows. Too frequently, CD and transmission errors on masks combine with dose and focus errors on scanners to reduce CD-limited yield. Future APC systems may be able to control dose and focus across the scanner field, compensating for mask and lens errors simultaneously.

In summary, the primary ROI risk in semiconductor manufacturing is at 90 nm and beyond, where yield is no longer limited by random defects. At these dimensions, yield is limited by patterning error arising from the interaction between more complex designs and shrinking process windows. RET complexity is now so high that learning delays have been increasing development cycle time in every major segment. Achieving high pattern-limited yield in early production is becoming more difficult due to higher aspect ratios and the increased number of layers with critical CD and overlay requirements. While it is true that advanced process control is expected to improve wafer processing at the 90 nm node and to ease the transition to volume manufacturing on 300 mm wafers, future implementations will need to incorporate both cross-wafer and cross-field control5, with the goal of eliminating nearly all systematic CD and overlay variation.

In addition to the above considerations, the lithographic patterning roadmap has stalled and Moore’s Law is in jeopardy. Key economic insertion points for 157 nm and 8

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EUV lithography have been pushed out to the 45 nm and 32 nm nodes, respectively. If newly developed immersion technologies are successful, it is likely that 193 nm lithography will be extended for three full generations, including the 45 nm node. Immersion lithography at the 193 nm wavelength provides a substantial depth-of-focus benefit even at 90 nm design rules, but the DOF advantage erodes rapidly at smaller feature sizes6. Strong RET strategies and focus-exposure control will still be required to extend lithographic capability beyond 90 nm.

Economics of pattern-limited yield

Parametric yield loss is an increasing fraction of total yield loss, and pattern-limited yield accounts for most of these losses [Figure 1a]. In particular, the ITRS has identified CD control at the 65 nm technology node as a potential technology roadblock with no known solutions. At 65 nm, shrinking design rules and narrowing process windows will become serious yield limiters. In high-volume production, corrections based on lot averages will have diminished correlation to device yield because APC systems will dramatically reduce error at the lot and wafer levels. As a result, cross-wafer and cross-field errors will dominate the systematic variation on 300 mm wafers. Much of the yield loss will arise from hidden systematic variation, including intra-wafer dose and focus errors that occur during lithographic exposure. In addition, corollary systematic variation in the profiles of critical high-aspect-ratio structures will drive requirements for vertical process control.

Figure 1b shows CD-limited yield as a function of gate CD error. The response surface is pinned to foundry yield data at 180 and 130 nm. Predictions at 90, 65, 45, and 32 nm are projections based on ITRS scaling.

ITRS scaling of the yield roll-off characteristic may be optimistic since it assumes consistent improvements in transistor design, such as raised source-drain, fully depleted SOI, high-k dielectrics, and three-dimensional gate structures. Yield roll-off, in this case, is slightly asymmetric with respect to gate leakage at low CD and speed loss at high CD. A mitigating feature of logic yield curves is the plateau near “zero error”, which creates a relatively stable region for speed binning. A feature of more concern is the gradual deterioration of the yield entitlement at “zero error” that occurs with each successive technology node. There are four sources of hidden systematic variation that contribute to “zero error” yield loss: unobservable error, unsampled error, unmodeled error, and uncorrectable error.

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Figure 2a. A bimodal CD distribution, above, shows a 90 nm nominal

Figure 2b. Data from an Archer MPX focus monitor shows how it can

CD with two peaks deviated from the mean by ±6 nm. The root-cause

be used for root-cause analysis of bimodal CD distributions. In this case,

is often traced to hidden focus or dose error across the wafer or field.

stepper scan direction is binned with 100% accuracy and purity.

In the following example, all four types of hidden systematic error were eventually detected. First, CD-limited yield was compromised by the unmodeled bimodal CD error shown in Figure 2a. Development of a simple scan-direction model for the lithography tool allowed engineers to parse the CDs into two groups associated with the plus and minus scan directions. Previous cross-wafer measurement plans sampled only a single scan direction, failing to detect the bimodality and putting product at risk due to unsampled CD error.

After a sensitive focus-exposure monitor was added to the line, the root-cause of the bimodal CD distributions was found to be previously unobservable focus error, similar to that shown in Figure 2b. An intra-field focus map also revealed uncorrectable focus errors due to lens aberrations.

The economic consequences of hidden systematic error and CD offsets can be severe, as shown in Figure 3a.

First, “zero error” yield loss creates a systematic, increasing baseline with each technology node. Second, due to the sharp roll-off of the CD-limited yield function, losses due to other CD errors increase non-linearly with magnitude. Third, the loss from CD error increases non-linearly from node to node; consequently, a 6 nm offset at the 65 nm node could have several times the effect of the same offset at the 130 nm node. The revenue impact of CD-limited yield on a medium-sized logic factory is shown in Figure 3b. A CD offset of 6nm at the 90nm node could result in annual losses in excess of 20 million dollars.

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Figure 3a. Estimates of CD yield losses using the model of Figure 1b,

Figure 3b. Estimates of revenue losses for a logic product using the

pinned to foundr y data at 130 nm. The yield impact of the 6 nm

yield data shown in Figure 3a. At 10,000 WSPM, 100 dies per

deviations shown in Figure 2a could be greater than 5% at the 90 nm

wafer, and $30 per die, annual losses could exceed $20M at the

node.

90 nm node.

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Spectroscopic Ellipsometry

Figure 4a. Grating-based focus-exposure monitor based on LES, a sensitive technique for detecting hidden focus-exposure error with an

Figure 4b. Principle of CD metrology based on spectroscopic ellip-

overlay metrology tool (e.g., Archer MPX).

sometr y, an ultra-sensitive technique for detecting hidden CD error with thin-film metrology tool (e.g., SpectraCD 100).

Solutions for pattern-limited yield

In this work, we have discussed potential CD yield losses and the dire economic consequences if no action is taken. Now, we show how sensitive focus-exposure monitors (Figure 4a) and spectroscopic ellipsometry (Figure 4b) can be used to reduce the impact of hidden error and CD offsets on pattern-limited yield.

Most failures in CD control originate from underlying root-cause errors that change the “effective dose and focus” during lithographic exposure. As a consequence, we are seeing a trend toward indirect CD control using focus and dose monitors. In addition, hidden profile errors in device structures are now contributing more significantly to yield loss. As a result, we are seeing a second trend toward the use of spectroscopic ellipsometry for inline CD and profile metrology. Below, we briefly discuss the origins and strengths of both strategies for uncovering systematic error and increasing CD limited yield.

Indirect CD control using LES focus-exposure monitors

Currently, many first tier semiconductor manufacturers are driving to monitor focus-exposure directly on production wafers. The objective is to control CDs without impacting productivity. In response to this need, optical overlay platforms have been adapted to provide simultaneous inline monitoring of focus, exposure, and overlay7. Unique dual-tone, line-end-shortening (LES) targets have been designed to decouple focus and exposure measurements [Figure 4a]. Small LES grating targets (about 13x22 µm) can be placed at multiple locations in scribe lines to monitor focus-exposure variation across the field and across the wafer. Relative to 10

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device CDs, these targets have much higher sensitivity to focus-exposure variation (e.g., < 0.5 percent in dose and 30 nm in focus from just one measurement). About 50 percent of CD variation can be traced to focus deviation, so improved focus control inevitably leads to more stable dose-based APC performance. At one time, the non-monotonic focus behavior of LES targets was thought to be a serious challenge, but the introduction of new targets is solving that problem. In addition, when multiple LES measurements are used in focus-exposure matrices, “best focus” repeatability can approach 1 nm.

Across the wafer, LES targets enable monitoring of systematic focus excursions due to reticle scan direction, wafer stage direction, and wafer topography, as shown in Figure 5a. In most cases, focus excursions are binned with better accuracy and purity than the CD variations they cause [See Figures 2a and 2b]. The corresponding cross-wafer dose map in Figure 5b has a distinctly different signature that is related to edge-die effects.

Many of these focus and dose effects are correctable by means of shot-to-shot control. Since focus and dose have different signatures, both may be required for root-cause analysis of anomalous CD distributions.

Across the lithographic field, LES targets enable monitoring of focus tilt and curvature, as shown in Figure 5c.

Fortunately, focus tilt is a cause of yield-affecting bimodal CD distributions that is correctable by adjusting the “scanning wedge” in lithography tools. The corresponding cross-field dose map in Figure 5d has a distinctly different signature, possibly due to variations in speed along the scan direction and illumination uniformity along the slit direction. Eventually, these effects will be correctable by means of cross-field dose

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Figure 5b. Corresponding MPX dose monitor data showing cross-wafer

due to alternation of scan direction as the stepper moves from field to

dose variation due to edge-die effects. Focus and dose typically have

field. Defocus is a root-cause of CD error.

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Figure 5c. MPX focus monitor data showing cross-field focus variation

Figure 5d. Corresponding MPX dose monitor data showing cross-field

due to lens aberration and scanning wedge effects. Such variation

dose variation due to non-uniform scan speed and slit illumination.

can produce yield-affecting CD and profile errors.

Both focus and dose are required for root-cause analysis.

control. Once again, since focus and dose have different signatures, both may be required for root-cause analysis of anomalous CD distributions.

costly use of off-line analysis requiring SEM and TEM cross-sections. Responding to this need, optical film thickness platforms based on SE technology [Figure 4b] have been adapted to provide simultaneous inline monitoring of CD, sidewall angle, depth, and film thickness. Typical applications of SE profiling technology include the complex stacks and layouts associated with shallow-trench isolation, multi-layer gate structures, sidewall spacers, and contact arrays. At one time, the applications to sidewall spacers and contact arrays

Vertical process control using spectroscopic ellipsometry

Currently, many first tier semiconductor manufacturers are seeking to monitor device profiles directly on production wafers. The objective is to avoid destructive and

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Figure 6. Spectroscopic ellipsometr y results for contacts showing ability to detect hidden profile error with high precision. Extremely low static precision noise floor (~0.1 nm) of the SE system enables measurement of resist faceting and footing in addition to CD, while dynamic precision supports intra-wafer and wafer-to-wafer comparison. SE line monitors help prevent yield loss due to small, sloped, resistive contact openings.

were thought to be a difficult challenge, but most of the problems associated with these measurements have been solved.

Gate stack profiles are a perennial application of SE [Figure 7] because of the association of notching, bowing, and undercut with yield loss due to drive current deficiencies and gate leakage. In the case of traditional top-down SEM metrology, such yield-affecting fine structure is typically unobservable, hidden systematic error. Subsequently, these profile variations are known to affect subsequent sidewall spacer and implant steps. Remarkably, given the small size of the fine structure and the lower information content, static and dynamic precision are still typically less than 0.4 nm 3-sigma, providing the sensitivity to detect nanometerscale etch offsets that can tie all the way back to lithography.

A third SE application that is being used quite extensively is the measurement of shallow-trench isolation profiles [Figure 8]. Nitride, oxide, and silicon profiles in the stack are known to correlate with oxide fill-voiding, poly wrap-around, and other sources of yield loss.

Due to signal-to-noise requirements, some of the most

Contacts are an especially important application of SE [Figure 6] because of the association of small, sloped, or footed openings with excessive contact resistance and yield loss. In the case of traditional top-down SEM metrology, yield-affecting fine structure in contact profile is typically unobservable, hidden systematic error. In contrast, the low static noise floor (~0.1 nm) of the SE system enables precise measurement of faceting and footing in addition to CD. The low dynamic noise floor (~0.2 nm) enables accurate cross-field and cross-wafer comparison. Both elliptical and rectangular contacts can be measured in any orientation, and virtually any â&#x20AC;&#x153;hole-elementâ&#x20AC;? can be measured and used for process control. In Figure 7. Spectroscopic ellipsometr y results for gate stacks showing ability to detect hidden profile error addition, an expanding variety with high precision. The low static and dynamic noise floor of the SE system enables measurement of notching, of rectangular, triangular, and bowing, and footing in logic gate structures. SE line monitors help prevent yield loss due to profile errors paired layouts are now supported. that affect subsequent sidewall spacer and implant steps.

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• Introduction of a predictive yield model for gate level CD control that can be pinned to actual factory data and that includes yield limiters due to hidden systematic error.

• Parsing of hidden systematic error into unobservable, unsampled, unmodeled, and uncorrectable error.

Figure 8. Spectroscopic ellipsometr y results for shallow-trench isolation showing ability to detect hidden profile error with high precision. The low static and dynamic noise floor of the SE system enables measure-

• Demonstration that 2-6 nm CD and profile offsets due to hidden error can lead to tens of millions of dollars per year in lost factory revenue.

ment of bottlenecking and notching in complex STI structures. SE line monitors help prevent yield loss due

• Application of an LES focus-exposure monitor for indirect CD control, showing superior binning and root-cause analysis for bimodal CD distributions.

to oxide-fill voiding and poly-silicon shorts.

critical measurements, including profile rounding and silicon recess, are unique to spectroscopic ellipsometry.

With traditional top-down SEM metrology, and even some of the newer top-down reflectometry techniques, • Application of spectroscopic ellipsometry for vertical such yield-affecting structural variations constitute unprocess control, showing superior sensitivity to yieldobservable, hidden systematic error. Another compelling affecting profile variations in contact, gate, and STI argument for SE is cost-of-ownership. In this application, structures. the SE system replaced an AFM, a CD SEM, and a dedi1.6 1.6 cated film-thickness tool, and Non-paraxial Non-paraxialmodel model performed their tasks with WetRES sin θ greater precision, accuracy, and 1.4 ≅ DryRES n sin θ overall equipment effectiveness.

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WetDOF sin 2 (θ D / 2 ) ≅ DryDOF n sin 2 (θW / 2 )

1.2

Conclusions and recommendations WET DOF / DRY DOF

In this work, we have examined two relatively new strategies for indirect CD control and vertical process control, respectively.

At 65 nm and beyond, we see product-wafer focus-exposure monitors and SE-based vertical process control as key solutions for improving pattern-limited yield in lithography and etch.

Several of the concepts summarized below are unique to this work:

DOFwindfall DOF windfallatat90 90nm nm

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Strong F-E Strong F -Econtrols controls required required Strong required StrongRET RETstrategy strategy required

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WET RESOLUTION / DRY RESOLUTION Figure 9. Plot of the normalized DOF for water immersion lithography at 193 nm versus normalized resolution using a non-paraxial model. The DOF windfall at 90 nm will be short-lived as design rules are pushed to 65 and 45 nm. In addition to RETs, strong focus-exposure control strategies will be required to maintain yield. It is likely that FE control will extend to the cross-wafer and cross-field levels.

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As a final note, although much hope has been attached to the success of immersion lithography, it is unlikely that the temporary DOF windfall expected at the 90 nm node will propagate to the 65 nm node [Figure 9].

At 65 nm and beyond, extreme RETs will still be needed for resolution8; small process windows will still drive strong F-E control strategies9; and higher aspect ratios will increasingly require vertical process control10.

Acknowledgement

This paper was previously published in the SPIE Proceedings, vol. 5378, pp. 204-214.

References 1. K. Monahan, “Microeconomics of Process Control in Semiconductor Manufacturing”, Proc. SPIE, Vol. 5043, pp.

57-71, February 2003.

2. K. Monahan, “Microeconomics of Yield Learning in Semiconductor Manufacturing”, Proc. SPIE, Vol. 5043, pp. 4156, February 2003.

3. K. Monahan, “Chairman’s Introduction to the ISSM 2003 Cost and Performance Workshop”, ISSM 2003, September 29, San Jose, California.

4. Xiao-Yu Li, Feng Wang, Tho La, Zhi-Min Ling, Ji-Fu Kung*, M.H. Wang, Horng Nan Chern, and Chia-Pin Lee, “An Effective Method of Characterization of Poly Gate CD Variation and its Impact on Product Performance and Yield”, Proc. ISSM 2003, pp. 259-262, September 30 – October 2, San Jose, California.

5. Rolf Seltmann, Rolf Stephan, Martin Mazur, Christopher Spence, Bruno La Fontaine, Dirk Stankowski, Andre Poock, and Wolfram Grundke, “ACLV Analysis in Production and Its Impact on Product Performance”, Proc. SPIE, Vol. 5040, pp. 530-540, February 2003.

6. So-Yeon Baek, Daniel C. Cole, Mordechai Rothschild, Michael Switkes, Michael S. Yeung, and Eytan Barouch, “Simulation Study of Process Latitude for Liquid Immersion Lithography”, Proc. SPIE, Vol. 5040, pp. 16201630, February 2003.

7. S. Hannon, H. Kennemer, K. Monahan, B. Eichelberger, B. Dinu, C. Nelson, H. Pedut, “Product-Wafer Focus-Exposure Monitor for Advanced Flash Memory“, Proc. ISSM 2003, pp. 354-357, September 30 – October 2, San Jose, California.

8. A. Hand, “Tricks with Water and Light: 193nm Extension”, Semiconductor International, Vol. 27, pp. 38-81, February 2004.

KLA-Tencor Trade Show Calendar March 15-17

SEMICON China, Shanghai, China

March 16-17

Diskcon Asia-Pacific, Singapore

April 12-14

SEMICON Europa, Munich, Germany

April 13-15

SPIE Photomask/Japan, Yokohama, Japan

June 6-8

IITC, Burlingame, California (USA)

June 6-9

Information Storage Week, Tokyo, Japan

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