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The Dollar Value of Accelerated Shrinks Kevin Monahan, Adil Engineer, Georges Falessi, Matt Hankinson, Sung Jin Lee, Ady Levy, Mike Slessor, KLA-Tencor Corporation
Previously, we have developed a simple microeconomic model that directly links metrology, yield, and profitability. The model has been used to explain the effect of metrology on gross margins in 200 mm and 300 mm factories. The same model can be adapted to evaluate the relative economic impact of accelerated design-rule shrinks in demand-limited markets. Using examples relevant to the high-volume production of memory products, we demonstrate that metrology-driven shrinks are still the most cost-effective way to improve profitability. We also describe the means by which these shrinks can be achieved in high-volume factories.
Introduction
In this work, we use a simplified microeconomic model for the profitability, or rate of profit, generated by the semiconductor manufacturing processi. Let P = −R +
∑ WT (Y y d b i
i i i ij pij
−bij Ci )
ij
where R is the factory overhead rate, W is the number of wafer starts, T is the time interval, Y is the metrology-limited yield entitlement, y is the die yield expressed as a fraction of the entitlement, d is the number of dies per wafer, b is the bin yield expressed as the fraction of good dies in each performance bin, p is the average selling price per die, C is the manufacturing cost per wafer, i is the product index, and j is the bin index. This business model represents the gross rate of profit attributable to a factory. It does not include variable costs associated with packaging, marketing, or sales of the product. Some of the basic strategies for maximizing gross profit are discussed below. The first term represents the fixed costs associated with capital investment, operation,
and depreciation of the facility that are independent of capacity utilization. The traditional strategy for minimizing the relative contribution of fixed costs is to reduce manufacturing cycle time and operate near maximum capacity. In a supply-limited environment, this means filling the factory with the highest margin products. Demand-limited environments may induce loading the factory with low-margin products. Such cases reduce average gross margins and can generate actual losses during times of rapid price erosion. Table 1 shows April 2001 estimates of yield-normalized cost per die, revenue per die, revenue per megabit, and revenue per wafer for several DRAM products. The 16-, 64-, and 128-megabit chips were nearly perfect commodities at one dollar per 16 Mb. Gross margins were negligible for 180 nm design rules. Since April 2001, average selling prices have sunk below the cost of manufacturing2. Table 1
Cost and Revenue in Dollars
Date: 4/12/01 16Mb SDRAM 64Mb SDRAM 128Mb SDRAM 128Mb DDR 128Mb RDRAM 256 Mb SDRAM
Cost($) 1.00 2.00 4.00 5.00 6.00 8.00
Price($) $/16Mb 1.02 1.02 2.15 1.08 4.35 1.09 7.90 1.98 10.00 2.50 13.95 1.74
$/Wfr 2040 2150 2175 3950 5000 3488
Gross Margins 180 nm 0.02 0.15 0.35 2.90 4.00 5.95
150 nm 0.33 0.76 1.57 4.43 5.83 8.39
Table 1.
Winter 2002
Yield Management Solutions
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