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Surfscan SP2: Enabling Cost-Effective Production at the 65 nm Node and Beyond Wayne McMillan, KLA-Tencor
Each time the semiconductor industry has moved forward to the next node, and looked beyond to future nodes, new materials have played important roles in enabling the shrinking of critical dimensions. The 65 nm and 45 nm nodes will likely be marked by the introduction of metal oxides, organic porous and nonporous low-k dielectrics, metal gates and new silicides. Engineered substrates, such as silicon on insulator and its derivatives, will see significantly increased market adoption.
New materials on the horizon
Integration of organic low-k dielectrics with copper dual-damascene interconnect structures will be one of the challenges in the back end of the line. While critical for their insulating properties, low-k dielectrics have less desirable mechanical properties, such as poor hardness and elasticity. This means the films have a higher probability of delaminating, deforming and, thus, generating defects under the load of the multilayered interconnect film stacks. Also in the back end, new etch stop and capping layers may be introduced to solve other issues, and new slurries and CMP techniques are likely to arise. In the front end, the 65 nm and 45 nm nodes promise not only new materials, but also new structures. Some manufacturers, such as Intel and TSMC, are looking at moving to a tri-gate or “3D” transistor1 (Figure 1). This radical new design would use silicon dioxide and, potentially, a high-k dielectric, as the gate insulator. High-k dielectrics, such as hafnium oxide, zirconium oxide, or lanthanum aluminate, would be introduced in order to reduce current leakage—a serious issue as gates become smaller and thinner. As usual, however, the benefit doesn’t come 14
Summer 2004
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without penalties: high-k materials have the drawback of mobility degradation for carriers in the channel below, creating serious problems for setting the threshold voltage. Furthermore, high-k dielectrics seem to be incompatible with polysilicon, forcing a simultaneous material switch to metal gate electrodes. Intel has reported that at the 45 nm node, they will move from doped polysilicon for the gate electrode, to two different metals for the NMOS and the PMOS transistors. Other manufacturers, such as UMC, are planning to remain with planar transistors and address the 65 nm node requirements solely through a change in materials. They will introduce high-k dielectrics and metal gates followed by selective epitaxial growth (SEG) in the
Figure 1. Tri-gate or “3D” transistor. Source: Intel.