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Advanced Substrates and Devices for Nanoscale CMOS Bich-Yen Nguyen, Aaron Thean, Ted White, Alexander Barr, Bruce Xie, Stefan Zollner, Mariam Sadaka, Xang-Dong Wang, Anne Vandooren, Leo Mathew, Melissa Zalava, Da Zhang, Debby Eades, Zhong-Hai Shi, Victor Vartanian, Shawn Thomas, Tab Stephen, Brian Goolsby, Ran Liu, Thien Nguyen, Veer Dhandapani, Jack Jiang, Raghav Rai, David Theodore, Mike Kottke, Rich Gregory, Michael Canonico, Ross Noble, Sriram Kalpat, Michael Mendicino, Marius Orlowski, Joe Mogab, Suresh Venkatesan, Freescale Semiconductor
The semiconductor industry has achieved exponential growth over the last thirty years, largely due to its ability to continually scale the CMOS transistor dimension to meet demands for density and performance. As device dimensions reach the sub-50-nanometer level, serious doubts are being raised regarding the ability to scale the gate lengths of conventional bulk silicon transistors below 30 nm. This has led to the integration of new materials and device architectures into CMOS devices. In this paper, we will discuss the progress and challenges of strained Si and SiGe materials being introduced into nanoscale CMOS devices.
Introduction
It becomes more difficult to scale CMOS transistors and still maintain high drive currents, while simultaneously dropping the supply voltage (Vdd) to prevent raising the electric field (which reduces carrier mobility) and avoid reliability issues. The threshold voltage and gate oxide thickness cannot be scaled at the same rate as Vdd without leakage currents exceeding stand-by power requirements. Thus, the maximum gate overdrive factor, Cox(Vdd-VT), is rapidly reduced with transistor scaling.1 At the same time, higher channel doping concentrations and more abrupt, shallower source-drain junctions have been used to control short channel effects (SCE) at very short gate lengths. These factors cause detrimental effects, such as degraded mobility, higher dopant fluctuations, and increased series resistance. In order to circumvent some of these scaling issues, new materials and device architectures are being integrated into CMOS devices to maintain the historic CMOS performance 48
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trend. These include enhancing carrier mobility by using biaxially stressed strained silicon (Si) with relaxed silicon germanium (SiGe) virtual substrates2 or uniaxially stressed Si using tensile or compressive stressors.3 Though the strained-Si (sSi) augmentation of conventional MOSFETs seems minimally disruptive, the use of SiGe virtual substrates in CMOS devices introduces new process and device issues that need to be addressed in order to prove successful manufacturability. Strained Si and silicon germanium channel engineering
When a thin Si layer is grown pseudomorphically on a relaxed SiGe alloy buffer (Figure 1) with its larger lattice spacing than that of Si, the Si layer conforms to the SiGe template by expanding laterally and contracting vertically. The resulting biaxial stress enhances the transport properties of the Si layer due to the altered band structure and electronic properties. It reduces inter-valley and inter-band phonon scattering, hole effective mass due to band warping, and preferential thermal population of electron states with light transport effective mass. Improvement of both electron and hole mobility by using the biaxial tensile sSi as a transistor channel has been demonstrated. However, sSi by