Magazine summer03 photocell article

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Micro Photocell Monitoring Finds the Killers Chris M. Jones, Chidam Kallingal, Mary Zawadzki, Nazneen Jeewakhan, Nazila Kaviani, and Prakash Krishnan, Cypress Semiconductor

For some critical layers—gate, contact, and local interconnect—the transition to 193 nm resists has been a requirement to developing 100 nm design rule technologies. As with previous technology node transitions, the materials and processes available are undergoing changes and improvements as vendors encounter and solve problems. The initial implementation of the 193 nm resist process did not meet the photolithography requirements of some IC manufacturers due to very high post exposure bake (PEB) temperature sensitivity and, consequently, high wafer-to-wafer CD variation. Characterization of these new resists needs to be carrier out prior to implementation in the R&D line. In addition to standard lithography parameters, resist characterization needs to include defect density studies. Cypress Semiconductor applied KLA-Tencor’s Micro Photocell Monitoring (µPCM) methodology for defect monitoring in the resist qualification process and was able to drive corrective actions earlier, resulting in faster ramp and elimination of potential yield loss.

Defect characterization has long been an integral part of process development work in R&D facilities, since ramping up a new technology and achieving high yields requires that processes have low defect densities. Defects introduced by etch, film deposition, and chemical mechanical planarization (CMP) processes are typically detected using inspection of short-loop, product, and/or monitor wafers. The defects are then characterized (size, shape, composition, spatial signature, etc.) and defect source analysis (DSA) is performed to identify the source of the defects. Process changes are then implemented in order to reduce or eliminate the various defect types, and the results are verified through further inspections.

photolithography engineers to develop and characterize new processes. Traditional photolithography metrics such as depth of focus (DOF), exposure latitude (EL), CD control, PEB temperature sensitivity, resist profile, and process window have been of primary concern.

These properties can vary greatly between different resists; therefore, new resists — even from the same vendor — need to be characterized prior to utilizing them on product wafers. Characterizing a new resist process based on photolithography metrics alone is not sufficient, since defect density is as important as CD, overlay, etc. Typical defects introduced in the photolithography process include bridging pattern, missing pattern, particles, residues, and collapsed pattern. These types of defects tend to impact yield, as the subsequent processing step (e.g. etch, implant) relies on the photoresist to define the pattern. Thus, developing and maintaining photo-lithography processes with low defect densities is critical for the yield and ramp of a new technology.

While this is common practice for most process modules, it is less prevalent in the photolithography module. The introduction of 193-nm scanners and photoresists for the 100-nm technology node has challenged

Detecting yield limiting defects and controlling excursions at the 100-nm technology node requires a high sensitivity defect inspection methodology that can be implemented in a production facility at minimum cost.

Introduction

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Non-patterned test wafers coated with resist and/or anti-reflective coating (ARC) materials have been used to assess defect density, as have inspections of patterned resist on product wafers. These methods have inherent shortcomings that reduce their effectiveness. In the case of non-patterned wafer inspections, typically only one component of the photocell is tested and, therefore, interactions between the various processes are not observed. Inspecting patterned resist on product wafers, often referred to as micro-after develop inspection (µADI), incorporates the entire photo process, however the “noise” introduced by the underlying layers tends to limit the sensitivity of the inspection.

KLA-Tencor’s Micro Photocell Monitoring (µPCM) methodology was developed to address the need for a high sensitivity inspection that can capture defects associated with the entire photolithography process. µPCM better utilizes available inspection tools and can be easily and cost-effectively implemented in production. µPCM uses patterned test wafers instead of blanket or product wafers, allowing the defect performance of the entire photolithography process (coat, expose, bake, develop, etc.) to be characterized using high sensitivity inspection. The implementation of µPCM in the characterization of 193-nm resists used for the gate and contact layers will be discussed in the remainder of this article.

The use of µPCM wafers for tool qualification and a cost analysis of two defect excursions are also included.

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utilizing resist-on-silicon patterned wafers. This monitoring methodology requires high resolution imaging technology and has been described in detail in references 1-4. These wafers are processed through all components of the photocell so that patterning defects, material interactions, and pattern density-specific defects can be characterized. µPCM wafers provide a higher signal-to-noise level than product wafers, critical for creating high sensitivity inspections. Further, SEM review of the defects is simplified (compared to non-patterned wafers) and the potential impact on yield can be assessed.

Successful implementation of the photocell monitoring methodology requires sufficient sensitivity to all microlithography defect types. The µPCM methodology utilizes KLA-Tencor’s 2351 high resolution imaging wafer inspection system and leverages its inherent strengths.

This inspection system has both ultraviolet (UV) and visible illumination modes, as well as high numerical aperture (NA). This system offers different optical inspection modes that provide high sensitivity to critical defects. These include brightfield (BF), Edge Contrast™ (EC), and Full Sky (FS) (see sidebar on 23xx inspection modes).

Resist characterization

In order to ensure that a photoresist will meet the needs of the target technology, the performance of the photoresist needs to be characterized. Parameters such

Photocell monitoring

The term “photocell” is used to describe the group of tools used in the photolithography process. This includes coat cups, developer cups, bake plates, and the exposure tool. Each component of the photocell is typically monitored individually using non-patterned test wafers, and defect density baselines are established for each component. Test wafers are used to optimize the individual processes in order to reach the entitlement defect density level and to then track the performance over time and identify defect excursions. While nonpatterned test wafers can be used to identify many defect issues, there are critical defect types that cannot be monitored using these test wafers. For example, defects related to the patterning process, interactions between materials (i.e. ARC and resist), and pattern density cannot be characterized using non-patterned test wafers.

The µPCM defect monitoring methodology addresses the shortcomings of non-patterned wafer inspection by

23xx inspection modes

During BF mode inspection, light is incident perpendicular to the wafer surface and reflected into the time delay integration (TDI) detector. The TDI detector creates a digitized gray scale image and imaging algorithms provide information on wafer defects.

EC mode is an optical mode that takes advantage of brightfield illumination. It suppresses reflected light from “low topography” surfaces — usually considered noise, such as color variation due to layer thickness variation while enhancing light intensity (signal) of the edges of high topography features.

FS mode is yet another optical mode that takes advantage of brightfield illumination. It suppresses previous grain layer noise by selectively filtering out light associated with this nuisance defect. FS mode is particularly effective on back-end metal layers.

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as CD control, resist profile, line edge roughness, PEB temperature sensitivity, and CD SEM shrinkage need to be quantified. Focus exposure matrix (FEM) wafers are used to evaluate the CD variation of isolated, gap, and semi-dense structures, in order to determine the overlapping process window. All of these factors can have a direct impact on yield; therefore, it is critical that this characterization work is done prior to introducing a photoresist into the manufacturing process.

Since photoresist vendors are continually improving the performance of their photoresists to meet the needs of IC manufacturers, the photoresist characterization process is an often-repeated task. The relative immaturity of the 193-nm lithography process and the stringent photolithography performance requirements needed for the 100-nm technology node add to the dynamic nature of process development.

The initial 193-nm photoresists utilized at Cypress Semiconductor were able to meet the process requirements, however they were not optimal. The PEB temperature sensitivity of the gate layer photoresist and the DOF of the contact layer photoresist were two critical parameters that needed improvement. PEB temperature sensitivity has a direct effect on CD variation, and DOF impacts CD control and photoresist profile. CD control is a vital factor for device performance and, consequently, the yield of the device. The photoresist profile is of critical importance for Table 1. Gate layer the etch process and can impact

device yield. Photoresist samples were obtained from different vendors, and two of these photoresists were selected for consideration.

Gate layer resist

The CD of the gate structure must be tightly controlled to meet the electrical performance specifications of the transistors. CD variation due to PEB sensitivity was identified as a problem at the gate layer for the 100-nm technology being developed in the R&D facility. A photoresist with a lower PEB sensitivity was obtained, and its performance was compared to the baseline photoresist. Table 1 lists the critical parameters for the baseline and the proposed new photoresist.

The process window of each photoresist was evaluated by measuring the CD variation on FEM wafers. This was done for isolated, gap, and semi-dense features and

photoresist characteriza tion parameters .

Process Window Overlap

F i g u re 1. Process window overl ap curves for p hotoresist A and B.

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Resist A (Baseline)

Resist B

F i g u r e 2. SEM cro ss-sections from FEM wafer f or photoresist A and B. Res ist A had slightly better DOF than Res ist B.

the data is plotted as a function of exposure dose and focus. The area contained within all three curves represents the process window overlap, as shown in Figure 1. SEM cross-section audits were performed to assess the DOF of the process. The SEM cross-section images for resists A and B are shown in Figure 2.

Photoresist B had improved PEB sensitivity and showed comparable performance for the other critical photolithography parameters.

The DOF for photoresist Z showed the desired improvement over photoresist Y, however the photoresist profile was barrel shaped (Figure 3). This photoresist profile was not sufficient for the subsequent etch process. The photoresist bake conditions were modified in order to improve the photoresist profile; however, this resulted in a DOF that was equivalent to that of photoresist Y. Further, the PEB sensitivity of photoresist Z was slightly higher. Photoresist Z failed to meet the photolithography requirements.

Contact layer resist

Along with shrinking linewidths, the CDs of contact holes are also decreasing. For the 100-nm node, the top CD of the contacts to the gate layer is on the order of 130-nm. This CD must be tightly controlled in order to meet the electrical specifications of the device. Further, the photoresist profile of the contacts needs to be as close to vertical as possible, since the profile can greatly affect the contact etch performance. The DOF of the baseline photoresist was marginal, and a photoresist with an improved DOF and comparable PEB and etch bias was desired. A new photoresist was obtained and characterized. Table 2 lists the critical parameters being compared for the baseline and the proposed new photoresist.

Table 2. Cont act la yer ph ot oresist character izati on parameters.

Photoresist Y

Photoresist Z

F i g u re 3. Contact hol e profi le comp arison for photores ists Y and Z .

Defect characterization: Gate

ÂľPCM wafers were prepared using the baseline and the proposed new photoresist in order to assess the defect density of the two photoresists. An inspection recipe for the gate layer was created on the 2351. Various spectral modes and pixel sizes were tested in order to arrive at a recipe that had high sensitivity with low false counts. The Edge Contrast (EC) mode gave the best performance for this layer and the 0.25 Summer 2003

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F i g u re 4. Waf er map for ph oto resist A.

F i g u r e 5. Wafer map for photo resist B.

µm pixel size was selected due to low false counts and good throughput. The inspection results revealed a large difference in defect density between the two photoresists, as can be seen in the wafer maps (Figures 4 and 5).

This was unexpected, as blanket photoresist coated wafers showed very low defect density levels for both photoresists (less than 30 defects in total) and in no way indicated that there would be such a large difference between the two photoresists. SEM review was performed in order to characterize the defect types present on the wafers, and sample images are shown in Figure 6.

F i g u re 7. Defect densi ty b y d efect t ype for photoresist A, B, an d

Two defect types accounted for the majority of the defects on the wafers: resist bridge and micro-bridge.

Both of these defects had a high likelihood of causing yield loss, so conversion to photoresist B was delayed.

The defect images were presented to the photoresist Micro-stringer

Resist Bridge

F i g u re 6. SEM images of typic al defects seen on gate layer µPCM wafer.

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i m p roved B.

vendor, who then modified the processing procedure based on the findings. An improved version of photoresist B was then obtained and characterized using the µPCM method. The improved photoresist B showed not only fewer Micro-bridge defects than the initial version, but also fewer defects than photoresist A (Figure 7).

Based on the results of the µPCM inspection and the photolithography characterization, the improved version of resist B was qualified for production use.

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F i g u re 8. Wafer map for photo resi st Y.

F i g u r e 9. Wafer map for photoresist Z.

Defect characterization: Contact

wafer having at least one defect. The defect images were shown to the photoresist vendor, and the photoresist was modified based on the µPCM inspection learning. µPCM wafers were processed using the improved version of photoresist Z and inspected for defects. The improved version of photoresist Z showed a much lower defect density than the initial version, but a higher defect density than the baseline photoresist Y (Figure 12).

µPCM wafers were prepared using the baseline photoresist Y and photoresist Z, and an inspection recipe was created on the 2351. The inspection parameters that gave the highest sensitivity and a low false rate for this layer were UV and brightfield illumination modes, and the 0.16 µm pixel size. The difference in defect density for the contact photoresist was even greater than that of the gate layer. The wafer processed with photoresist Z had approximately forty times the number of defects of the photoresist Y wafer, and the defects were randomly distributed on the wafer (Figures 8 and 9). Again, this difference in defectivity Distorted Contacts Missing Contacts Partially Open Contacts was not observed using the F i g u re 10. SEM images of distor ted, missing, an d p artially open cont acts. non-patterned test wafer method. SEM review was performed and the three primary defect types were identified to be distorted, missing, and partially open contacts (Figure 10). A focused ion beam (FIB) cut was made through one of the partially open contacts and the cross-section image is shown in Figure 11.

The defects reviewed on the wafer processed with photoresist Z appeared to be gross enough to impact the contact etch process. The high defect count and random distribution across the wafer resulted in every die on the

F i g u re 11. FIB cross-section of partia lly open co ntact.

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Tabl e 3. ROI an alysis f or gate a nd cont act layer defec t ex cursions.

Th e po tential dollars lost if thes e defect excursion s not been det ected via µPCM test waf ers wa s ca lcul ated based on an ASP of $13 per di e, 5,000 wa fer star ts per week, and 474 di e per waf er.

F i g u re 12. Defec t d ensi ties of res ist Y, Z, and improved Z.

The slightly higher defect density of the improved photoresist Z combined with the barrel-shaped profile and higher PEB temperature sensitivity led to this photoresist not being selected over the baseline photoresist for the contact layer.

ROI analysis

The µPCM characterization work identified several distinct defect types on both the gate and contact layers that could not have been captured using non-patterned wafer inspection. SEM review of the defects showed that these defects had a high likelihood of impacting yield. Table 3 illustrates an ROI analysis for gate and contact layer defect excursions.

was selected as the vehicle for the tool qualification, as the process was converted to the same photoresist as the gate layer and the LI layer had the smallest line width and pitch for this device. The defect inspection recipe parameters that yielded the best results for this layer were UV light, Edge Contrast, and the 0.20 µm pixel size. Since this layer would be scanned by production as part of the standard tool qualification procedure, an iADC (inline automatic defect classification feature on the 2351) classifier set was created to minimize the time spent on SEM defect review. The initial defect review identified five critical defect types that will be included in the iADC classifier set. These defects are shown in Figure 13.

The potential cost associated with each of these defect excursions is quite substantial, and far greater than the cost of processing and inspecting a µPCM test wafer.

Further, µPCM wafers can easily be processed and inspected on a daily basis in order to reduce the number of wafers at risk should a defect excursion occur. Based on this, Cypress Semiconductor has begun implementing the µPCM methodology as part of the standard tool qualification process for the photocell.

The µPCM wafer qualification is currently being performed on a daily basis in order to establish the baseline defect density level and to acquire defect patch images that will be used to populate the iADC classifier set.

Once the baseline defect density level is established and the iADC classifier set is created, the frequency of the tool qualification may be reduced if appropriate. µPCM wafers will be processed following all photoresist or ARC batch changes and after preventive maintenance work has been carried out on any component of the photocell.

Tool qualification using µPCM

Conclusion

The results obtained during the photoresist defect density characterization highlighted some of the shortcomings of the non-patterned wafer inspection method, and a decision was made to implement a µPCM waferbased tool qualification. The local interconnect (LI) layer

The development of new technologies and processes is a continual challenge for semiconductor manufacturers.

Shortening the development time while ensuring that the processes are robust is a critical aspect of R&D. The introduction of 193-nm photolithography has been one

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Type 2

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Type 5

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Type 3

iADC Class Codes 1) micro-bridging 2) full stack bridging 3) surface particle (small) 4) falling line 5) surface particle (large)

F i g u re 13. SEM images of defec t types incl uded in iA DC c lassifi cation set.

of the challenges for the 100-nm technology node.

Qualifying new materials and tools has required the implementation of a defect inspection methodology that has a high sensitivity to potential yield limiting defects. The utilization of µPCM to assess the defect performance of 193-nm photoresists was a critical part of the photoresist characterization effort at Cypress Semiconductor. High defect density levels were seen on both of the new 193-nm photoresists being evaluated using µPCM wafers and, therefore, the photoresists were not used on any product lots. The standard nonpatterned wafer inspection did not reveal significant differences between the baseline and proposed photoresists. The defect data collected from the µPCM wafers were shared with the photoresist vendors, and the vendors were able to improve their process, lowering the defect density to the baseline level. Had the defect performance not been characterized using µPCM and the photoresists used in production, the potential yield hit could have cost almost $3 million. Therefore, defect characterization using patterned resist on bare silicon

wafers is highly recommended for the 193-nm photolithography process. The µPCM inspection recipes created on the KLA-Tencor 2351 can also be used to qualify the track and scanner for production use, and the defect density can easily be tracked using iADC and SPC. This is currently being implemented at Cypress Semiconductor.

References 1. Ingrid B. Peterson, Defect Reduction Methodology in the Li t hog ra p hy M o d ul e , XI I I A nn u a l M e e t in g of SPI E M i c rolithography Conference, p. 520 (1999).

2. Kay Lederer, et al., Automated Micro Defect Monitoring for 300mm Lithography, Olin Interface 2002.

3. Eric H. Bokelberg, et al., Photocluster Defect Learning and Develop Process Optimization, Olin Interface 96, p.127 (1996).

4. Ingrid Peterson, et al., Lithography Defects: Reducing and Managing Yield Killers Through Photo Cell Monitoring, Yield Management Solutions 2-3 (Summer 2000).

A version of this article originally published in the 2003 SPIE Microlithography proceedings 5038, SPIE Micro l i t h ography Conference, February 2003, Santa Clara, California, USA.

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