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Get ready for slowdown in device shrinks, shift litho R&D to other issues, says NIST director

By J. Robert Lineback The Semiconductor Reporter www.semireporter.com Feb. 24, 2003

Karen H. Brown

SANTA CLARA, Calif. — The semiconductor industry must soon shift its emphasis from steadily shrinking device feature sizes on two-year technology cycles to much broader efforts in cost reduction and wafer-fab productivity if chip makers want to continue leveraging Moore's Law this decade, warned the deputy director of the U.S. National Institute of Standards and Technology (NIST) here in a speech before lithography experts.

Dubbing the upcoming period a "lithographer's vacation," Karen H. Brown cautioned that optical exposure tools — such as new 193-nm scanners — and photomask processes were simply unable to keep up with the accelerated device-shrink targets now contained in the industry's technology roadmap. Instead of forcing optical tools to print feature sizes much smaller than 60-to-50 nanometers, the chip industry must take a different tack and much-needed break from the aggressive shrinks of transistor gates and half-pitch design rules no widely associated with Moore's Law, Brown told a couple hundred experts at KLA-Tencor Corporation's Lithography Users Forum prior to the start of the SPIE Microlithography conference in Santa Clara.

"If the tool isn't going to make smaller feature sizes because you have reached the physical limits, then maybe those people [lithographers] can work on something else for a while," she told the group, which responded with nervous laughter. Later, while Brown fielded questions at the Sunday evening event, one lithography expert asked if it was going to be a "paid vacation."

Brown then admitted that the term "vacation" may not be the best way to describe the upcoming period for lithography development, but she urged attendees of the SPIE Microlithography conference this week to look beyond the technologies and processes that were most familiar to them.

"There are a lot of technologies out there that can be cost effective and save a lot of money for specific levels 36

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What happened to cheaper and not just smaller in Moore's Law? Somewhere along the way in the past three decades, Moore's Law — the industry's gauge for predicting transistor integration on ICs — turned into mostly a rule for device shrinks with heavy emphasis on aggressive lithography technologies, observed Karen H. Brown, deputy director of the U.S. National Institute of Standards and Technology (NIST).

It was not always that way, she noted during her speech before a group of lithography and metrology experts Sunday night in Santa Clara before the start of this week's SPIE Microlithography conference.

Ever since Intel Corp. co-founder Gordon Moore first proposed the his curve for doubling transistors on a chip every 18 to 24 months in the mid-60s, Moore's Law has become a golden rule to keep the chip industry on track with next-generation process technologies and integration on a die. But the emphasis today may be too much on costly lithography shrinks with not enough attention to Moore's law for lower costs, Brown told the group.

"In some ways it [Moore's law] is the same but in some ways it has changed. Originally, it was [focused on] transistors per chip or unit area, but that translated into cost per function because if you can stuff more transistors into the same area, you get more functions for the same amount of cost or less cost per function," she noted. However, the emphasis since the mid-1990s "became the lithography feature size."

used in photomasks and device structures," said Brown, who is also acting director of NIST and a former director of lithography at industry consortium International Sematech.

Sunday agreed with Brown, but the NIST deputy director predicted that existing optical lithography systems and processes would no longer support device shrinks after 2004 or 2005.

"You don't have to take cost out at the gate level. Cost can be taken out at other levels and you can take cost out by how you do the design," she told the group, suggesting that a variety of lithography technologies could help to solve the high cost of photomasks and other processes while 157-nm and extreme ultraviolet (EUV) lithography is given more time for development.

"Somewhere in here," she said, pointing to slide showing a plot for device shrinks in the industry's lithography roadmap, "things are going to slow down because 157-nm isn't going to be in manufacturing in 2005, and EUVL will probably not be in manufacturing in 2006. So the industry is going to have to figure out how to look at what we have [here] and deal with the reality of the situation — things are not going to shrink as fast as we show here." Brown added that the industry must also work harder to "figure out how to deal with the problem in an economical and cost-effective way."

The dilemma facing the semiconductor industry is whether or not to press harder to ready 157-nm wavelength lithography tools for production in just a couple years or to continue using complicated and expensive resolution enhancement techniques in reticles to print smaller feature sizes with 193-nm scanners. Not all of the experts attending the lithography meeting on

In her talk before the KLA-Tencor-hosted gathering, Brown proposed going back to the original emphasis of cost-per-function "or something else as defined

by Moore's Law" without "necessarily having the lithography line [for shrinks] going straight down."

Without some new approach — such as immersion lithography, which is now being studied as a potential optical lithography extender — Brown suggested that the photolithography curve for shrinks will flatten out or only go down slightly from 2004 until nearly the end of decade. "We need new technology now to continue the shrinks," she said, adding that 157-nm and EUV lithography are not even close to providing feasible solutions in the next couple of years.

"My prediction is the industry will find a new solution — a new paradigm for how to make Moore's Law stay on track in cost-per-function," she said, suggesting that designers work more closely with lithographers and process engineers to keep technology from stalling out. "Maybe slower cycles in feature size shrinks will allow more cost-effective tool development because you have more time and resources to focus on specific types of answers."

She urged better communications between lithography and design groups. Perhaps that means lithography engineers will have to impose strict limits and rules on IC designers, who cannot break the imposed design rules for the next four or five years — even with resolution enhancement techniques, Brown suggested. "Maybe lithographers should become designers," she added.

Brown suggested that the upcoming "lithographer's vacation" period could be used to help improve existing optical lithography systems and photomask technologies to put them back on track in terms of cost for many IC applications — such as lower volume ASICs. The time could also be used to help struggling lithography equipment makers, photomask shops and other infrastructure suppliers recoup investments while regaining financial health after the industry's worst downturn ever, she added.

According to Brown, it takes $200 to $300 million to develop a lithography tool, which today might have only a lifecycle of two years — "the 157-nm tools are projected to be in use [for critical dimensions] from 2005 to 2007," she said, referring to current roadmap targets of EUV lithography being introduced around the 2007 timeframe for the 45-nm process technology node.

"You cannot recover your investment. You can hardly make them work right," Brown warned. "So it is a chance for equipment companies — especially in this timeframe when money is not just pouring in the doors — to look at how they are spending the money, and do it more cost effectively ... It is a balancing scenario — how do we use this time to catch up and have more cost effective tools and more robust processes?"

"Affordability and cost are issues we need to think about.

We need to make smaller feature sizes — yes — and we need to do other things — yes — but we need to do them cost effectively," said Brown, a former IBM Corp. lithography researcher and developer for 22 years. "We need cost-effective resolution enhanced masks [such as optical proximity correction, or OPC, and phase-shifting]. That means masks will not cost $400,000 apiece," she added, referring to current projections of $1 million or more per photomask set in 90-nm processes.

"We need development of mask infrastructure because it is lagging behind, and it does not allow us to do many things cost effectively or at all. Perhaps we could [cut costs and implement shrinks] if we spent time, energy, and money on that," Brown said.

Copyright 2003, Intervalis LLC

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