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Improved Yield Learning Using CMP Equipment Monitors

by Scott Hiemke, Dean Spaugh, John Givens, Albert Liu, Miguel Delgado, VLSI San Antonio; Rebecca Howland Pinto, Ph.D., KLA-Tencor

When a new line monitoring point is introduced into a manufacturing line within a fab, it must be justified. This justification process involves careful experimentation to determine that process excursions are occurring at these points which have significant impact on yield. It involves verification that inspection and metrology tools are optimized to identify the relevant excursions, and it involves bringing together people from several different groups within the fab to cooperate on the solution. Finally, the solution must be implemented on the manufacturing line.

CMP defects by polarization

CMP defects by sensitivity

CMP defects

CMP defects

At VLSI San Antonio, new inspection points were introduced to monitor intermetallic oxide (IMO) chemical mechanical polish (CMP) layers, and tungsten CMP (WCMP) layers. A combination of defect monitoring using the AIT, defect review using the CRS and JEOL SEM stations, and analysis using Quest produced information that led VLSI to make changes to the way their CMP scrubbers and polishers are utilized. These changes provided significant benefit to the yield learning rate at the San Antonio facility.

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Figure 1. A combination of s input polarization and high sensitivity set-

Introducing a new inspection point

The process that VLSI used for determining whether a new inspection point should be introduced for post-CMP layers was comprised of several steps. First, the defect group characterized the proposed line monitor point. This involved setting up recipes on the AIT, and going through various combinations of polarizations and sensitivity settings to determine which setup provided the best capture of defects. In the case of CMP layers, success meant capturing the largest number of microscratches, shallow scratches, gouging and slurry residues while minimizing false counts. The defect group

tings on the AIT provided best capture of defects on CMP layers.

found that s-polarization and high sensitivity provided the best results, especially in open areas of low pattern density (figure 1).

The second step of the process involved collecting data from the manufacturing line at that inspection point, to establish a baseline and determine what impact these defects had on yield. Analysis of the data indicated that defects introduced at the CMP steps produce a high potential for die loss. Based on this information, a team was formed to address the CMP processes as a source of high yield impact.

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Defect detected at WCMP1 Defect from Old Scrub Recipe Figure 2. Introducing a new scrub process made an immediate, positive impact on defectivity.

The team and its charter

The team’s charter was to optimize the CMP processes: specifically, to minimize defects introduced at CMP steps, and maximize true up-time of the CMP polishers.

VLSI set goals and deliverables for the project, and set limitations on allowable methods for addressing the problems. For example, existing CMP consumables (pads and slurries) and equipment had to be utilized.

Defect inspection and film thickness measurements were the chief techniques employed to attack the problem.

The interdepartmental team, comprised of process engineers from the defect group, CMP engineering and CMP manufacturing, discovered that the first step towards solution of the problem was to establish a control action system. This system is represented by a flow chart that documents ownership for each step of the decision of what to do with out-of-control lots. The process of documenting responsibility through the control action system proved invaluable in making progress towards the goals of the project.

The culprits

Defect detected at IMO2CMP Figure 3. Examples of defects detected after WCMP and after IMOCMP.

nine lots through the process flow, measuring film thickness and defectivity after each CMP step. The AIT was particularly well suited to this application, because its high throughput meant that every wafer in the lot could be scanned to enable characterization of wafer-towafer variation. Examples of defects found after WCMP and after IMOCMP are given in figure 3. Note that several defect types were captured well in areas of dense pattern.

Following the defect inspection, the wafers were measured on the UV-1280SE to characterize the variation

The second area investigated was the nonuniformity of the oxide layer after CMP. The team followed a set of

Figure 4. Film thickness measurements (using the UV-1280SE) showed

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Film Thickness

Once the control action system was in place, the team began its investigation by examining the effectiveness of the post-CMP scrub. They discovered that changing the scrub process significantly reduced the number of defects left on the wafer. A comparison of the new and old scrub processes is given in figure 2, along with examples of defects found after scrubbing. Introducing the new scrub process made an immediate, positive impact on defectivity.

Site on the Wafer

a domed oxide profile, which negatively affected edge die yield.

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Figure 5. Introduction of a line monitoring point helped trace defect excursions to a faulty drum of slurry and wear and tear of a polishing pad.

in oxide thickness across the wafer (figure 4). The film thickness measurements showed that the oxide profile was domed, and as a result, edge die yield was negatively affected. This prompted the team to recommend tightening the specifications for post-CMP oxide uniformity.

Transfer to manufacturing

The last part of the team’s responsibility was to transfer the improved process to manufacturing. This meant that the AIT had to be interfaced to PROMIS, VLSI’s Work In Progress (WIP) tracking system. Fortunately, more than 90 percent of the GEM/SECS code written originally for the Surfscan 7700 was transferable to the AIT. This ensured that the correct lot numbers, process levels, recipes and data were being sent to Quest and transferred to VLSI’s SPC system.

The line monitor was set up to monitor WIP in the queue for a tool, and skip lots past the inspection steps if more than a certain number of lots are waiting, or if a recipe is missing. As a result of this setup, more than 60 percent of the total volume are currently inspected post-CMP by scanning lots across 10 to 12 part types.

In addition, over 50 percent of the other process layers are inspected on the AIT. At VLSI San Antonio, over 19 process layers throughout the line are inspected by the AIT. The final step in transferring the process to manufacturing involved training the CMP engineers and manufacturing personnel to use Quest and the various review stations at their disposal.

The learning continued

Once the improved process was successfully transferred to manufacturing, some other important discoveries were made. One defectivity excursion at oxide CMP was traced to a change in a drum of slurry, when the lines had been improperly flushed out (figure 5).

Figure 6. Examples of defects found at a shallow trench isolation (STI) CMP layer.

CMP Manufacturing decided to change the pads more frequently: three times more often to reduce the defect levels. Introducing this inspection point has resulted in a dramatic change in the way maintenance is done on the CMP polishers in this facility.

Faster yield learning now and in the future

Since implementing the line monitoring methodology described above, VLSI San Antonio has increased their yield learning rate. A better yield learning rate translates directly into higher profitability for the fab.

Because of this success on their current products, VLSI San Antonio also elected to add an inspection point to their below-0.25 µm development work, at shallowtrench isolation CMP (figure 6).

This paper is largely derived from a presentation first given in July 1998 at the Yield Management Solutions Seminar during SEMICON/West.

Another discovery was that just before a polishing pad was changed the defectivity level increased. As a result Spring 1999

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