Magazine spring99 coverstory

CMP TECHNOLOGY TRENDS: IMPLEMENTATION

by Anantha R. Sethuraman, Ph.D., CMP Solutions, KLA-Tencor

Mechanical Polishing C hemical (CMP) has become one of the

most widely-accepted and practiced planarization methods in IC fabrication in less than two decades. The explosive growth of this segment of semiconductor process technology has been remarkable in an industry that has been credited with rapid growth. In an industry that aspires to reach six sigma process control based on scientific first principles, CMP is still being used and developed by artisans. The rigor in the design of experiments held as gospel by the semiconductor industry has not been applied in the development of CMP consumables. After more than ten years of widespread assimilation of this technology, users need an integrated process control solution for their CMP needs. This article discusses some of the history of the maturation of the technology, notes current challenges facing the industry and presents some views on the timeliness of an integrated process control solution for CMP. Current status and emerging trends

When viewed as a process module within a fab, CMP is comprised of a number of elements from a number of different suppliers (see figure 1).1

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Each user assembles a selection of components from this list and integrates the process in manufacture. It is quite likely that each of these components are available from a relatively limited group of vendors who specialize in products unique to CMP which are guarded by high levels of secrecy and intellectual property protection. In contrast, for the more mature sectors such as plasma etch or thin film chemical vapor deposition (CVD), an equipment supplier can more than likely provide the user with the tool, best-known-methods (BKMs), endpoint detection, process consumables, delivery systems and even exhaust treatment systems.

With the broadening of knowledge and expertise in CMP, the technical community is driving towards achieving the maturity level that they have become accustomed to expect in widely accepted processes.

However, due to the consumablespecific nature of CMP itself, the fact remains that all slurries and pads will still be specialty materials, controlled by one or two vendors. By its very nature — its multiple vendors and specialty material requirements — CMP has developed into a niche market technology that demands generous amounts of “black magic” and folklore to achieve success!

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Post-CMP Cleaning

Planarization Equipment Conditioner Endpoint detect Process Slurry Pad Insert Template Slurry delivery Slurry replenishing Slurry recycling Slurry disposal

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Metrology

Equipment PVA Brush Tanks Spin/rinse/dry Hot DI water Cold DI water Process Chemistry Chemical delivery Chemical disposal

Equipment Thickness Uniformity Particles Scratches Defects Electrical quality Setup standards

Figure 1. Elements of a CMP process module. 1

# of Layers Polished

ILD polish Metal polish

1994 (0.8 - 0.5)

1998 (0.35 - 0.25 µm)

Figure 2. Growth of CMP utilization. 2

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The rapid growth in the use of CMP technology is shown in figure 2.

Between 1994 and 1998, CMP use more than doubled — use of CMP on interlayer dielectrics (ILD) grew from three to five layers, and polishing of metal contacts and the introduction of the damascene process created the need for CMP on metal. For example in a four metal layer process with shallow trench isolation (STI), ILD and tungsten CMP: 15-25 polishers would be needed at 60 percent utilization, with 20 wafers per hour, in a fab with 5000 wafer starts per week.

Furthermore, the extension of CMP to the front-end in order to enable STI integration has triggered the need for innovation. STI has become an architectural requirement for sub0.25 micron device rules, as localized oxidation of silicon (LOCOS) does not deliver the critical transistor properties. The challenge of STI is typically to planarize a high density plasma oxide over silicon nitride.

The objective is to remove the overburden without damaging the nitride excessively, while preserving the integrity of the circuit. Although this is a formidable requirement, it presents a great opportunity. The result has been development of exotically exciting technical solutions in CMP consumables, especially highselectivity slurries. In addition, process solutions using better endpointing have also enabled STI CMP. In the memory area (specifically DRAM), polysilicon polish has been in implementation for about a year.

The volume is expected to increase as more manufacturers adopt poly CMP. Figure 3 describes the evolution of CMP applications in chip manufacture. About two-thirds of the 93 semiconductor fabs producing devices with sub-0.5 micron geometries require some form of CMP. When considered in number of wafer

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starts per week that would need CMP, this number is in the thousands. This implies that the process has emerged as a critical part of the architecture of an integrated circuit and is therefore needed for integrated control of the process to achieve yield goals.

Emerging trends in equipment also support the need. A typical layout of a polishing area in the fab is shown in figure 4. As one can imagine, a wafer fab with more than 10,000 wafer starts per week would have several polishers. Currently each polish and clean tool is intrinsically connected with the input and output device. In the future, a robot will be used to allow two or more polishers to be attached to a single input/output source and a single cleaning station.

This arrangement will optimize tool use and increase processing speed.

The development of the infrastructure needed to support an efficient operation is drawn from all the vendors that supply into the area. Since CMP is a relatively new area for semiconductor manufacture, the expertise on the user side is sparse although growing. Larger organizations such as IBM, Intel, Micron Technology, Motorola and AMD have over the years developed a reasonable methodology to manage the technology. The development of such Application 1st Generation 0.8-0.5 µm

Oxide (ILD)

2nd Generation <0.5 µm

Above + ILD0 W CMP + STI

3rd Generation < 0.25 µm

Above + Cu, Al & low k CMP + new applications (both FE & BE, e.g.

Poly Si)

Figure 3. Current and future

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methodologies has been evolutionary.

The conventional control that a semiconductor engineer would like to have over the various aspects of the process has not been possible with CMP, primarily due to the continuing and rapid metamorphosis of the process itself.

A history of CMP development

Let us examine a little bit of history.

The chronology described in figure 5 shows the initial rollout of CMP3.

Conceived and developed at IBM under strictest secrecy during the early 1980’s, the process was not well publicized. Vendors who supplied equipment such as IPEC Westech, R. Howard Strasbaugh and process consumable suppliers with pads/carrier films from Rodel and slurry from Cabot were not told the end result of their involvement. This was a typical practice in early semiconductor process development, as intellectual property issues were not well worked out between vendors and chipmakers. The concept of joint development projects (JDPs) between vendors and chipmakers was alien in the era of big company research and development activities. The result was that early understanding of the intricacies of the process rested solely with the users and an infrastructure for development of an ideal solution

CMP

Post-CMP Cleaning

Single Platen/Single Head 1-step polish

Conventional wafer cleaning (wet stations) Wafer scrubbing/DI water

Multi-Platen/Multi-Head 2-step polish (buff step) End-point detection On-board metrology

Wafer scrubbing/DI water NH4OH

Integrated Dry-in/Dry-out Multi-Platen/Multi-Head Non-Rotary (e.g. Orbital, Linear CMP) multi-step polish, End-point detection On-board metrology

Integrated Dry-in/Dry-out Multi-Platen/DIW NH4OH, HF New cleaning methods & New chemistries

trends in CMP applications.

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integrating both equipment and materials was not developed. After all, the concept of polishing a wafer with expensive circuitry that had been developed and manufactured in a clean room environment using “dirty” particle-laden slurry was started as an “experiment”. Given the dramatic shift in thinking required to accept such an idea, there were a multitude of skeptics who did not expect CMP to survive, let alone be where it is today.

As with every breakthrough we have witnessed in the technology sector, what was once deemed improbable, or even impossible, has become a reality and is now accepted as an essential step. Until depth of focus requirements necessitated more stringent planarity as the shift to 0.35 micron devices occurred, CMP was never seriously viewed as a longrange solution. Due to the secrecy with which it was developed, understanding both the power and the challenges of CMP has taken longer to achieve than many other processes in our industry’s history.

Following on the heels of IBM, Intel launched CMP via technology transfer in the 1987-88 timeframe followed by Micron Technology in 1989. The SEMATECH program on CMP was conceived in 1989 and then began the pursuit of rigorous characterization of the process as adoption rose quickly. Member companies dispatched their best talent to collaborate in this “sand box” called SEMATECH. Technical advisory boards were formed and vendors were initiated into the “inner circle”, although again restrictions against disclosing the JDP progress to nonmember companies were imposed in an effort to ensure better return on investment for the member companies. Figure 6 presents the number of process areas that were involved in the CMP sector in 1992 and the increase to date. It depicts a 5-10 Spring 1999

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Robot Clean

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Figure 4. Trends in equipment layout in the CMP area. 2

East Fishkill Base Technology (83) East Fishkill Pilot Line (86) Logic (Oxide, Al) (89) Logic (Oxide, W) (89) Burlington Pilot Line (86) 4MB DRAM (89)

Figure 5. CMP development at IBM.

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Number of CMP Vendors

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times increase in the number of suppliers, each filling a specific need with a tailored solution. These suppliers now vie for nearly a billion dollars in total revenue available today.3 Considering the unusual complexity created by both the very nature of CMP and its idiosyncratic development, an integrated process control solution provider has not emerged.

Figure 6. Growth in the number of CMP vendors to date. 3

Number of CMP Patents Filed

Figure 7. Number of CMP patents filed.

What does the future hold?

With the advent of copper interconnect, the influence of CMP on final yield has increased even more. The success of copper dual damascene interconnect technology lies squarely on the film deposition, CMP and post-CMP clean steps. Along with the enabling characteristics of CMP for copper, there also is a hidden danger. Flaking of copper during or as a result of the CMP process creates defects that might be insignificant in other processes, but are considered “killers” in these highly sensitive applications. The thin layers and multiple levels used in copper interconnect structures will require increased CMP use, yet little is understood about the criticality of the defects seen there. The principal challenge in copper CMP is optimizing copper polish rate with respect to barrier layers (typically Ta or TaN).

Currently this is being achieved by a two or three stage process wherein a new slurry is employed for barrier polish. Although not fully optimized, the challenge has opened doors for technology development.

For this reason, the introduction of copper presents a huge inspection challenge and thereby a valuable opportunity for innovation.

We are currently approaching a point in time when there is a definite need to provide an integrated process control solution for CMP. Copper interconnect and a continuation of the challenges in areas such as shallow trench isolation and other interlayer

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dielectric applications makes control of CMP more critical in achieving appropriate device yield and performance.

What are the core competencies that will be needed in a supplier to win in the integrated process control solution game? To begin with, this highly complex technology will require an understanding of polymer chemistry, colloid chemistry, powder synthesis, electrochemistry, and surface chemistry, none of which are mainstream competencies in an industry that makes electrical devices. So who would be most successful in delivering an integrated process control solution for CMP? The most likely case would be a coalition of capital equipment vendors and consumable vendors who can service the market with all that is needed to run the process. Unlike many other semiconductor processes, CMP is unique in its requirement for both chemical and mechanical superiority, making the coordination of tools and materials considerably more important to a successful effort.

This industry is largely dominated by electrical engineers and, to a certain extent by mechanical engineers, due to equipment needs, so the few chemists or physical sciences engineers available have not been adequate to drive the creation of an integrated solution scenario. Furthermore, the newness of the technology has led to a “rat race” to file patents (figure 7). Propelled by the need to be the “first-to-file” company, most of the users have been unwilling to disclose or “share” the secrets with vendors who might then have been in a position to provide better solutions. This thinking is changing, but it has left a legacy of slow change in its wake.

Only now, as CMP has finally emerged as not just an accepted but an essential practice in the majority

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of fabs, is the industry turning from “implementing” to “improving” the use of this technology. An integrated solution utilizing the best tools, materials and techniques will be critical in achieving the high level of device performance and production yield required for the advanced products of the next millennium.

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1. M.A. Fury, Solid State Technology, April 1995 and July 1995.

2. M. Moinpour, Proc.NCCAVS CMPUG Annual Symposium., 1997.

3. K. A. Perry, VLSI Conference., June 1997.

4. A.R. Sethuraman, Future Fab International, Vol. 5, pp.261, 1998.

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Acknowledgments The author would like to acknowledge the helpful discussions with Mike Fury of Allied Signal, Mansour Moinpour of Intel Corporation and Kathleen Perry of Obsidian Inc. for the theme of this article.

5. A.R. Sethuraman, Proc. of CMP 98, NCCAVS, 1998.

About the Author Anantha Sethuraman has a Ph.D. in Materials Science with a metallization specialization. He is a Senior Director in Corporate Marketing focused on CMP strategy. He has held managerial positions in technology development at Cypress Semiconductor and Rodel Inc. He was involved in the development of CMP technology for several years at Rodel, primarily responsible for slurry and process development for advanced CMP processes. Anantha has published more than 70 papers and holds several patents in CMP technology.

Contact information KLA-Tencor • 160 Rio Robles • San Jose, CA. 95134 Tel 408.875.4374 • Fax 408.875.4144 Email: anantha.sethuraman@kla-tencor.com

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