D E F E C T M A N A G E M E N T Copper Interconnects
Cycling Your Way to Faster Development and Integration at the BEOL Accelerating Copper Interconnect Development
Judy Shaw, Richard L. Guldi, Tae Kim, Dan Corum, and Jeffrey Ritchison, Texas Instruments Steve Oestreich, Jason Lin, Kurt Weiner, Kara Davis, and Robert Fiordalice, KLA-Tencor Corporation
Development and integration learning cycles of a 130 nm advanced logic device were accelerated using area-accelerated e-beam inspection. The devices used in this study employed a low-κ dielectric (κ<3.0), a silicon carbide (SiC) etch-stop scheme, and several levels of copper interconnect.
Introduction
With the introduction of copper interconnects at 180 nm, and the subsequent blending of low-κ interlevel dielectrics (ILD) at 130 nm, interconnect modules continue to represent the biggest challenge for achieving fast ramps and high yields of the most advanced logic devices. Moreover, technology introduction cycles of 18 months, or less, require that technology ramps be efficient and that the limited number of cycles of learning be used effectively. Leading edge microprocessor technologies at the 100 nm node will utilize eight or more levels of back-end-of-line (BEOL) interconnect, making up over 70 percent of the device processing. So, rapid BEOL process development and integration are key to a timely ramp from the development to pilot production stages. Rapid development requires that problems be identified and isolated quickly. Once the issue is identified, process and integration splits that target the root cause can be identified. The key is providing the yield and integration teams with tools that can help them identify the source of the issue quickly. At the same time, it’s important to
quantify the impact in terms of both parametric performance and yield. If the root cause can be properly quantified, the process and integration engineering teams can be confident they are working on the best solution. In addition, proper quantification of the issue provides the basis for the identification of critical metrics. Through the monitoring of these metrics, progress toward the elimination of the issue can be tracked. Two-component strategy
The strategy is comprised of two components, electron beam inspection and advanced test chip design. The merging of these two components is called eDo.1 The fundamental concept of the eDo technology is the use of an automated e-beam defect inspection tool and data filtering techniques to isolate only electrical defects, while at the same time using smart test chip design to maximize wafer throughput. The isolation of the electrical defects from the many physical and nuisance defects is critical to accelerating yield learning. This is done using voltage contrast (VC) methodology. Contrast imaging is used to differentiate floating and grounded structures. In addition to using VC filtering, smart test chip designs are utilized to dramatically improve the relative throughput of the inspection allowing for what can be Spring 2003
Yield Management Solutions
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