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Q&A
TSMC’s T ransition to 300 mm
An Interview with Dr. Nun-Sian Tsai, Senior Director of TSMC’s 300 mm Pilot Line Project Dr. Nun-Sian (NS) Tsai is senior director of TSMC’s 300 mm pilot line project. Dr. Tsai joined TSMC in 1989 as an R&D manager. He then went on to hold various positions at TSMC, including Fab 1 fab director and Fab 4 fab director. From 1997 to 1999 he was vice president of operations at Vanguard International Semiconductor Corporation, a TSMC-affiliated company. Prior to joining TSMC, Dr. Tsai worked for AT&T Bell Laboratories from 1983 to 1989. He obtained a Ph.D. in materials science from M.I.T. in 1983.
Q
What are the primary reasons and main drivers behind your decision to move to the 300 mm wafer size?
A
There are three primary reasons that drive our decision. These include lower cost, higher capacity, and higher yield. With regards to cost, the expectation of the industry is that the unit IC cost will reduce by 30% within next two to three years. We have capacity installed with new technology and capabilities. If we continue to add capacity, 200 mm can take us to 0.13 µm, however, 300 mm can take us to 0.07 µm. The third reason is that we believe 300 mm yields will be significantly higher that 200 mm.
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Spring 2001
The slow down in 2001 will not impact or slow down our 300-mm activity. We plan to continue with the pilot line, install technology, improve yield, and reduce the cost. TSMC’s strategy is to be ready for ramp up as quickly as possible once the business recovers. The timing of advanced 300-mm production is related to the business aspect. If the business climate is good, we can even run more aggressive technolo gies; if it is bad, we will stick to 0.13 µm design rules.
Q
In your opinion, what are the key challenges to transitioning to 300 mm?
A
Our biggest challenge has been process integration defectivity. Currently, work is underway on
Yield Management Solutions
0.13 µm technology, and there is no experience with 0.13 µm yet that can be shared. We do not see a major issue in transferring processes from 200 mm, 0.18 µm Al interconnect technology to the larger, 300 mm wafer size. Other key issues include fab production and automation. In introducing new process technologies such as sub-wavelength lithography, potential issues include mask OPC, focus exposure, etc. Defects in copper and low-k have been points of concern in 200 mm, and will continue to remain of concern in 300 mm. However, more work has to be done in these areas before key challenges can be clearly identified.