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Intelligent Control of the Semiconductor Patterning Process: A NIST ATP Program Update

by Matt Hankinson, Ph.D., KLA-Tencor Corporation

This overview provides highlights from the first two years of the Intelligent Control of the Semiconductor Patterning Process NIST Advanced Technology Program (ATP). The three-year, $18 million program is focused on applying Advanced Process Control, including sensors and metrology, statistical analysis, and process control, to reduce variation in polysili con gate critical dimensions.

The patterning process (lithography and etch) is the most expensive process module in the semiconductor manufacturing process, accounting for almost half of the wafer processing equipment costs. The aggressive reduction in features sizes makes patterning one of the most difficult areas to control, and patterning is largely responsible for determining final device yield and product performance. At the same time, the ongoing reduction reduces the device tolerances and the process window, while demanding the patterning of more difficult features. If the process is not manufacturable at high yields, this will significantly increase cost per part.

However, if the process can be tightly controlled, then it is possible to manufacture higher-value parts at high yield.

with control algorithms and high-speed data analysis techniques to gain process control in the patterning module. These solutions are being developed and tested by the program team members and suppliers, enabling the semiconductor and related industries to purchase these integrated solutions as products for current or next-generation patterning equipment. Benefits that will be realized as a result of this project include: a) increased product yield as a result of improved repeatability of the patterning tool set; b) increased production efficiency as a result of reduced set-up time and reliance on test wafers; and c) increased productivity by replacing off-line metrology with new in-line metrology. The work in this program will be applica ble to future patterning generations and other potential breakthroughs in patterning technology.

The goal of the Intelligent Control of the Semiconductor Patterning Process project is to improve the gate linewidth uniformity in the wafer patterning process. Technological advances in semiconductor manufacturing are determined by the width, or critical dimension (CD), of the lines that are printed on a wafer. Limits on CD capability are set by the uniformity of the patterning process; a series of processing steps that includes photolithography and etch. It is proposed that a significant reduction in variance can be accomplished by developing and using measurements in the patterning flow, along

We have assembled a team of chip manufacturers, equipment manufacturers, sensor suppliers, software suppliers, and universities to implement a coordinated approach to improving CD uniformity.

Program Overview

This program is conducted by researchers in each of the partner organizations. KLA-Tencor Corporation provides overall technical coordination, with input and wafer processing by Motorola. Contributions from FSI International, a manufacturer of lithography equipment, Lam Research, a manufacturer of etch equipment, and KLA-Tencor, a process control and yield management company, assure that professional and commercially viable approaches will be taken to this work. The involvement Spring 2001

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algorithms for both lithography and etch, and the evaluation of sensors needed to measure control inputs in situ. The selected sensor technology covers the broad wavelength spectrum, DUV (248nm) to IR (25 (m).

These sensors will be evaluated for measuring attributes of resist chemistry during processing, wafer surface patterns, etch plasma chemistry, and etch exhaust chemistry, for use as possible control data sources.

Model-based feed-forward and feedback control algorithms will be developed to reduce variability in key processing steps for the patterning module.

F i g u re 1: Ga te CD C ontrol Team Part i c i p a n t s

of five universities, University of Michigan, Stanford University, University of California at Berkeley, University of California at Irvine, and University of Wisconsin completes the team (see Figure 1). A number of other companies are involved as subcontractors to the program.

The NIST Advanced Technology Program provides support through their funding and technical guidance.

Approach

Research in this program is folded into three principal focus areas: Focus Area 1: The first focus area is characterizing variability in the patterning process. This work is focused on a thorough analysis of sources of CD variability.

Process sensitivity and controllability of each source are determined for the lithography (resist coating and processing, exposure, reticle, metrology), etch, and etch metrology. Subsequent tasks consist of various modeling approaches relating CD variability to process conditions, and the evaluation of metrology techniques designed to observe these conditions. Metrology techniques including electrical linewidth, scatterometry, and spectral reflectometry, in addition to the existing CD-SEM technology, are used to study wafer variation. The work is being performed in the semiconductor manufacturer’s fab, the resist processing and etch labs, and the metrology lab, as well as technology development at the universities.

Focus Area 2: The second focus area is reducing variability in the patterning process. Tasks in this focus area are directed to the development of control 66

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Focus Area 3: The third focus area is system integration.

This focus area addresses integrating sensors, metrology tools and control algorithms into the process equipment and a commercially viable manufacturing control system.

The architecture is based on the APC Framework implemented in Catalyst.

Results

There are four basic categories to the results: 1) statistical analysis of time series and variance components; 2) sensor technology for monitoring process parameters; 3) metrology techniques for measuring wafer state and critical dimension; and 4) feed-forward and feedback control algorithms.

We are conducting an analysis of sources of CD variation.

A detailed CD error budget model is built using baseline process variation statistics and sensitivity studies to measure the impact on CD (see example in Figure 2).

A variety of process parameters are measured during the patterning process to establish the baseline variation. We collect this data in conjunction with wafer measurements to correlate process variation with CD variation. Statistical analysis includes assessing nested variance components with systematic and random effects, and spatial and temporal variation. For each nested level (lot-to-lot, wafer-to-wafer, across-wafer, across-field, and across-chip) we separate the systematic and random variation using spatial models and fixed effects. Sensitivity studies of key process parameters are then combined with the baseline statistical variation to construct a model of the impact of each parameter on CD variation.

We have also made progress in hidden Markov models for analyzing sensor data. This framework uses a stochastic state-based representation of the process to reduce false alarms and the detection latency by incorporating prior expectations about state changes. The technique can be automated for pattern-based change-point detection.

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for process control applications in lithography.

F i g u re 2: Sources of C D Variation Paret o Char t

The sensor technology progress includes a diode-laser absorption technique for monitoring the concentration and temperature of plasma chemical species. This method tracks the standard optical emission techniques, but has advantages in minimizing cost and window transmission. A broadband RF impedance sensor was also developed and analyzed under various process conditions. This sensor provides chamber condition information for fault detection and optimal maintenance cycles. The plasma etch process was characterized using both sensors. These sensors will be used for further process monitoring applications and possible inclusion in real-time control schemes.

CD metrology techniques in this program include scatterometry, electrical linewidth, and spectral reflectometry. Different CD scatterometry techniques have been evaluated and compared with CD-SEM for correlation studies. An in-situ reflectometry method was developed to measure resist CD during plasma etching. Integration methods have also been investigated

We have investigated various strategies for feed-forward and feedback control using CD measurements from the developed resist profile to adjust lithography and etch parameters (see Figure 3). The adjusted parameters initially included dose and etch time, but will be extended to additional parameters. We have also quantified the impact of metrology delay and measurement error on the controller performance. The benefit of wafer-to-wafer control strategies was simulated against lot-based controllers. Despite the low wafer-towafer variance in typical processes, significant benefit is observed from wafer-to-wafer control by quickly centering overall mean for the cassette. Process simulation tools such as PROLITH are used to test control strategies using realistic process parameters. We are also integrating lithography simulation tools for advanced model-based process control strategies.

Finally, we have investigated issues related to the collection, storage, and query of sensor, equipment and wafer data for applications in analysis and process control. This work has led to major improvements in the database performance. The program is expected to conclude in mid-2002 with the definition of a comprehensive gate CD control system.

We would like to acknowledge the time, resources, and expertise provided by the NIST Advanced Technology Program under project number 98-01-0167, as well as our partners, KLA-Tencor, Lam Research, FSI International, University Michigan, Stanford University, and finally our many participants including Motorola, U.C. Berkeley, U.C. Irvine, U. Wisconsin, On-line Technologies, Domain Logix, and Dynamic Intelligence.

F i g u re 3: Con trol Schematic

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