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M i c roeconomics of M e t ro l o g y, Yield, and P rofitability in 300 mm Manufacturing K. M. Monahan, Ph.D., A. Chatterjee, and G. Falessi, KLA-Tencor Corporation

Simple microeconomic models that directly link metrology, yield, and profitability are rare or non-existent. In this article, we introduce and validate such a model. Using a small number of input parameters, we explain current yield management practices in 200 mm factories. The model is then used to extrapolate requirements for 300 mm factories, including the impact of simultaneous technology transitions to 130 nm design rules, copper interconnect, and integrated metrology. We show that the dramatic increase in value per wafer at the 300 mm transition becomes a driver for increasing metrology capability, despite a concomitant increase in cost. As expected, the model results are strongly dependent on product type (memory, chipset, or microprocessor) and process maturity.

Introduction

In this work, we use a simplified microeconomic model for the profitability (i.e., profit per unit of time) generated by the semiconductor manufacturing process1. Let

PROFITABILITY = -R +

(Y y d b p ∑W T i

i i

i ij ij

- b i jC i)

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where R is the factory overhead rate, W is the number of wafer starts, T is the time interval, Y is the metrology-limited yield entitlement, y is the overall device yield expressed as the fraction of good dies per wafer out, d is the number of dies per wafer, b is the bin yield expressed the fraction of good dies in each performance bin, p is the average selling price per die, C is the manufacturing cost per wafer, i is the product index, and j is the binning index. This business model represents the gross rate of profit attributable to a factory. It does not include variable costs associated with packaging, marketing, or sales of the product. Some of the basic strategies for maximizing gross profit are discussed below.

The first term represents the fixed costs associated with capital investment, operation, and depreciation of the facility that are independent of capacity Spring 2001

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utilization. For 300 mm manufacturing, this investment might include 300 mm factory automation, 130 nm pattern transfer technology, copper/low-κ interconnect capability, and factory-wide metrology integration. In the above model, 300 mm factories would be losing significant amounts of money before processing a single wafer. The traditional strategy for minimizing the relative contribution of fixed costs is to reduce manufacturing cycle time and operate near maximum capacity. In a supplylimited environment, this means filling the factory with the highest margin products. In a demand-limited environment, this may require loading the factory with some lower margin products. The latter strategy reduces average margins, but may improve the ratio of profitability to capital investment.

The second term in the profitability equation above represents the rateof-profit, adjusted for manufacturing cost per wafer. This variable cost arises from materials, consumables, and other expenses that scale with the number of wafers processed.

Offsetting this cost is the factory revenue, which is calculated from the average selling price per die, scaled by dies per wafer, wafer-starts, metrology-limited yield, device yield, and bin yield. Using these input parameters, we develop a heuristic model for metrology and sampling that can help to define strategy for ramping yield in development and for continuously improving baseline yield in production. We have discussed the methodology for containing yield excursions in previous work 2.

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“top-line” revenue. Defect metrology tools, on the other hand, recover value by increasing yield without increasing costs (C), other than those associated with the metrology itself (c). In this sense, the benefits of metrology go directly to the “bottom-line” profitability of the semiconductor manufacturing enterprise. We have shown previously that metrology in the factory should be optimized using stochastic models2. However, the dynamics of metrology, yield, and profitability in the factory are best understood using heuristic response models that are chosen to fit the results of more rigorous stochastic models or, in some cases, actual factory data.

For the single-product response model, we make the simple assumption that, starting at 1-y0, killer defects decline by the same fraction with each cycle of learning n, so that the effectiveness of learning declines exponentially. The incremental cost c due to metrology is assumed to scale linearly with the number of cycles of learning, in accord with COO models. If the capability and cost of metrology scale with and , respectively, then substituting into the equation for profitability gives us an expression for the value recovered by metrology: ∆VALUE = (1–y0)(1–e-n )–

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n Ydp

In the limit where the metrologylimited yield entitlement approaches unity, the value recovered is just the improvement in the gross margin of the product. The number of cycles of learning required to reach peak profitability is given by

Metrology, yield, and profitability

Process tools add value by generating output (W/T) at a given level of yield, thereby contributing to the

Y

nmax =

1

{( ) dp(1–y ) }

ln Y

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We can make a number of qualitative observations with regard to metrology-driven yield improvement, some of which are highly intuitive: • In development, where starting yields are low, the need for metrology is high for all products. Within a single process generation, the optimal allocation of metrology resources is time-dependent.

• In production, high value per wafer and relatively low transfer yield increases the need for metrology (microprocessor).

Within a process generation, the optimal allocation of metrology resources is product-dependent.

• If metrology capability and cost are scaled proportionately (i.e., if is constant), the design of next-generation metrology tools (N+1 and N+2) will be dominated by the requirement for capability.

The negative impact of cost on value recovery is greatest when the expected revenue per wafer is low (memory).

• Value recovery is greatest when metrology tools are fast (low ), sensitive (high ), and responsive to all yield-limiting defect types (high Y). In virtually all cases, these are conflicting requirements that argue for multiple-tool metrology solutions. Development cycle time is reduced, yield ramps are steeper, and yield entitlements are higher.

Results and discussions

In Figures 1-3, the value-recovery model shows gross margin improvement (Y=1) for two virtual products: commodity memory and highend microprocessors. These products are assumed to have ASPs of $5 and $500 per die, respectively. The

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equipment. Capability and cost are assumed to double while going from generation N+0 to N+2. Capability is scaled with density, decreasing as chip size increases.

F i g u re 1. Commodity memory — 200 mm wafers.

F i g u r e 2. Commod ity memor y - 300 mm wafers.

F i g u re 3. $500 micro p roc essor - 300 mm wafers.

respective densities are 2000 and 500 dies per 300 mm wafer. Development yields are assumed to start at zero, while production yields at transfer are scaled to account for chip size and product complexity. Metrology capability and cost are estimated for both current (N+0) and future (N+2) generations of metrology

In the case of high-volume production, the model results are strongly differentiated by product type. For commodity memory on 200 mm wafers (Figure 1), the achievable yield is limited primarily by cost. In the case of commodity memory on 300 mm wafers (Figure 2), the additional value per wafer justifies a higher level of metrology (e.g., N+2), resulting in faster baseline yield improvement and a higher yield entitlement (nearly two percent higher in this case). Larger gains will occur as commodity memory manufacturers migrate to embedded logic, DSP manufacturers develop system-onchip products, and microprocessor companies compete for the highestASP market segments.

Due to higher average selling price, larger chip size, and lower transfer yield, the economic model for microprocessors is strikingly different.

Substantial investment in advanced metrology capability may be justified well into high-volume production.

Microprocessor margins are extremely sensitive to metrology capability and relatively insensitive to cost (Figure 3). Taken as a whole, this analysis brings up some significant economic issues: • Assuming optimized metrology capability, 300 mm factories should enjoy not only economies of scale but also higher yields and gross margins. This creates an opportunity for the larger silicon foundries and a threat for smaller semiconductor manufacturers that cannot afford to build 300 mm factories.

• In the case where multiple products are manufactured using a Spring 2001

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similar process, monitor reduction strategies intended for the lowest-value products can lead to unacceptable economic risk.

Ideally, sample plans should increase for high-value products manufactured on 300 mm wafers.

• In the case where multiple factories are equipped identically (copy exact), the benefits of metrology innovation may never be realized, severely limiting the ultimate yield entitlement.

Ideally, 300 mm factories should be designed to support seamless upgrades of existing metrology equipment and the introduction of newer metrology tools, with minimal disruption to the process and material flow (copy smart). Given a supply-limited labor market, these introductions may require remote e-diagnostics, e-applications, and e-training for both metrology and process tools3.

Multiple tool solutions

Our models generally support multiple-tool solutions for the optimization of yield and profitability. Most copper lines, for example, use a combination of darkfield, brightfield, and e-beam wafer inspection to accelerate yield ramps. With the further segmentation of metrology tools into stand-alone, clustered, integrated, and in-situ systems, the optimal metrology strategy seems less clear, until we consider the economic impact of these technologies.

Consider the case of integrated metrology. We assume that these systems will have lower sensitivity, respond to fewer defect types, but enjoy higher sampling rate in comparison with traditional stand-alone line monitors. The value-recovery calculations for production of microprocessors and commodity memory

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F i g u re 4. Integrated metro logy — mi crop ro c e s s o r.

F i g u re 7. Calibrated model — di verging yiel ds.

F i g u re 5. Integrated metro logy — co mmodity

cially for memory products during volume ramp, since these tools are “blind” to a large fraction of killer defects. As a result, factories would not achieve entitlement margins and would risk exposure to nonroot-causable yield excursions.

analysis. This “use-case” scenario illustrates a more general trend toward complete process-module control solutions that include multiple metrology tools 4, networked analysis software, and optimized yield strategies.

• In a supply-limited market, silicon foundries that currently enjoy a “wafers-out” business model, are likely adopters of integrated metrology. However, in a demandlimited market, foundries that do not acquire the most capable metrology tools, will lose customers to foundries with efficient “dies-out” business models or “wafers-out” business models with predictable yield boundaries.

Yield prediction is critical to meeting production requirements without creating excess inventory.

The normalized copper yield ramps of several leading-edge semiconductor companies are shown in Figure 6.

In Figure 7, we use some of this data to calibrate our microeconomic model, thereby enabling a root-cause analysis of the yield divergence between Companies A and F. By fit-

m e m o r y.

are shown in Figures 4 and 5. In this example, transfer yields start at 0.60 and 0.90, respectively. Based on results for integrated, line-monitor, and combined solutions, we can make qualitative observations about the use of integrated metrology for improvement of baseline yield: • In the case of microprocessors, integrated metrology appears to enhance the effectiveness of more sensitive, stand-alone line monitors by freeing them for more demanding applications. The wafer-to-wafer sampling capability of integrated tools reduces exposure to gross yield excursions.

• The use of integrated metrology as a “single-tool” solution creates unacceptable economic risk, espe14

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Copper pilot lines provide another example of success with multipletool solutions. Most copper lines use a combination of darkfield, brightfield, and e-beam wafer inspection for tool monitors, station monitors, line monitors, and engineering

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F i g u re 7. Calibrated model — diverging yields.

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• Finally, we have shown that success in copper yield ramps is critically dependent on both metrology capability ( high αY) and metrology capacity (high n) References 1 . K. Monahan, et al., “Accelerated yield learning in aggressive lithography”, Proc. SPIE 3998, p. 492 (2000).

2 . R. Williams, et al., “Optimized sample planning for wafer defect inspection”, Proc. ISSM’99, p. 43 (1999).

3 . M. Locy, “On-line diagnostics as a key part of process module contro l ” , P roc. ISSM 2000.

4 C. Hayzelden, et al., “Process module control for low-k interlevel dielectrics”, Proc. ISSM 2000.

F i g u re 8. Increasin g Cu c apability—e-bea m in spection.

ting the model first to Company-F data and then forcing it to achieve Company-A yield levels, we identified the likely causes of divergence.

The model parameters indicated that Company A had newer, more capable metrology tools and significantly greater capacity. An audit of the metrology tools in each company confirmed these results.

Adding metrology capability goes beyond upgrading or replacing older optical tools. One extension of metrology capability that is now common in copper pilot lines is e-beam wafer inspection. E-beam inspection technology is not only more sensitive to many physical defect types (Figure 8) but is also uniquely responsive to new classes of buried electrical defects (e.g., voids and incomplete vias) that are frequently observed in the copper damascene process. As a consequence, e-beam inspection increases the aggregate metrology capability (αY), enabling shorter development cycle-times, accelerated yield learning, and higher yield entitlements.

Conclusions

In this work, we have introduced a simple microeconomic model that links metrology, yield, and profitability in semiconductor manufacturing. These are our findings: • The dramatic increase in value per wafer at 300 mm justifies an increase in metrology capability, despite a concomitant increase in metrology cost • Value recovery by metrology depends strongly on process maturity, product type, metrology capacity, and metrology tool generation • Our model strongly supports optimized, multiple-tool solutions for improvement of yield and profitability • For example, integrated monitors can enhance the effectiveness of stand-alone monitors but are generally not viable as the sole metrology solution in a factory

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To be published in the Proceedings of ISSM 2000, September 26-28, 2000, Tokyo, Japan.

About the Author Dr. Kevin Monahan is VP of Parametric Solutions in the Customer Group of KLA-Tencor Corporation. He is currently working on factory-wide, high-volume engineering solutions for the control of photo and etch process modules. Kevin has held a variety of positions within KLA-Tencor, including VP of Technology in a Strategic Business Unit and Director of Strategic Marketing in the E-Beam Metrology Division.

Dr. Monahan is known as the founder of the SPIE Conference on Metrology, Inspection, and Process Control; former CTO of Metrologix, Incorporated; and editor of the Handbook of Critical Dimension Metrology and Process Control. He holds a BS in physics from the California Institute of Technology and a Ph.D. in physics from the University of California.

He has published more than 100 business and technical papers.

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