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From One Side to Another How Backside Defects Can Wreak Havoc on IC Features Laura Pressley, Ph.D., Shirley Hardin, Jeremy Bolf, Travis Kirsch, John Darilek, Mike Allen, Brian Dunham, Buster Klingemann, Teresa Mathews, Carolyn Cariss, Eric Apelgren, Dan Sutton, Kevin Harper, Laurence Kohler, Ph.D., Chris Lansford, Terri Couteau, Bryon Hance, Fab 25, Spansion LLC Rhonda Stanley, Joyce Witowski, Lisa Cheung, KLA-Tencor Corporation
This article examines the impact that backside defects can have on the frontside of wafers and, ultimately, on device performance. For example, in this study, a detailed front-end-of-line (FEOL) frontside and backside defect partition showed that several defect mechanisms were operating in the FEOL, and identified a previously unknown backside defect mechanism that was affecting every incoming silicon wafer from several silicon substrate suppliers. An evaluation of backside defect data enabled the silicon suppliers to identify the root cause.
Introduction
A key challenge for semiconductor devices patterned at 110, 90, 65 nm and below are backside defect transfer mechanisms that occur in batch processing equipment in which the frontside, device performance portion of the wafer is directly exposed to the backside of wafers during processing. Several studies of backside defectivity have been previously reported in the literature.1-10 The majority of processing equipment for IC devices utilizes single wafer processing for etch, photolithography, CVD, PECVD, and polish operations. Yet, diffusion and wet clean processes are typically performed in batches and are susceptible to defect transfer between wafers during processing. Several IC equipment suppliers have anticipated these defect transfer-related issues and have developed new methods to minimize these transfer mechanisms. For example, several IC wet clean equipment suppliers have developed immersion tools that orient wafers with the frontsides facing each other (face-to-face processing), which allows the
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Fall 2005
Yield Management Solutions
wafer backsides to not be directly exposed to the IC features. Going one step further, single wafer wet clean sinks have also been developed in recent years, and single wafer cleans are progressively being introduced in the FEOL cleans by various IC manufacturers. In FEOL diffusion furnace processes, wafers are typically positioned in parallel above each other with the frontsides of wafers underneath the less characterized and typically more defective backsides of wafers. This type of diffusion furnace batch processing is susceptible to backside defects and the incidence of film flaking onto the frontside of the wafers positioned below. These mechanisms may be the result of film stress, thermal expansion/contraction, and/or lattice mismatch issues that occur during diffusion processing. Therefore, it is important to understand and characterize the backside defectivity in the FEOL batch processes to determine if these processes contribute to die yield losses. In this paper, FEOL diffusion backside defectivity characterization methods are discussed, including the chemical identification of these defects, the correlation of various backside defect signatures to a root cause, the transfer to the frontside of wafers during FEOL diffusion processes, and the possible impact to device sort yields.