Magazine fall01 defect to yield

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A Defect-to-Yield Correlation Study for Marginally Printing Reticle Defects Jeff Erhardt, Khoi Phan, Eric Backe, Quang Tran, Beverley Fletcher, Advanced Micro Devices C. Bradford Hopper, Spotfire Systems Ingrid Peterson, Aaron Zuo, KLA-Tencor Corporation

This paper presents a defect-to-yield correlation for marginally printing defects in a gate and a contact 4X DUV reticle by describing their respective impact on the lithography manufacturing process window of a 16 MB Flash memory device.

The study includes site-dependent sort yield signature analysis within the exposure field, followed by electrical bitmap and wafer strip back for the lower yielding defective sites. These defects are verified using both reticle inspection techniques and review of printed resist test wafers. Focus/Exposure process windows for defect-free feature and defective feature are measured using both inline SEM CD data and defect printability simulation software. These process window models are then com pared against wafer sort yield data for correlation. A method for characterizing the lithography manufacturing process window is proposed which is robust to both marginally printing reticle defects and sources of process variability outside the lithography module.

Introduction

High yield for a leading edge, sub-0.25 µm technology depends greatly on the manufacturing process window at critical lithography layers. This process window can be strongly impacted by marginally printing, or “soft” reticle defects. Two hurdles must be overcome when evaluating a new product mask: the first is the ability to detect errors on the reticle, and the second is to understand the yield impact of any defects.

There are several ways in which lithography engineers attempt to characterize the impact of reticle errors on the manufacturing process window. As a first step, the manufacturer can use reticle inspection tools, such as the KLA-Tencor STARlight™ system, to detect the existence of reticle defects. After the reticles are received in the fab, the fab engineer can use automated defect inspection tools to review printed wafers. While these methods may be successful in identifying possible errors, the

yield impact of these defects can be difficult to quantify.

The printability of reticle CD errors depends not only on the defect size, but also on the shape and proximity to other features. Moreover, it is likely that the effect of these defects is influenced both by product-specific sensitivity and interaction with non-lithography process modules. It is important, then, to develop robust techniques for detecting and characterizing the true process window of marginally defective reticles.

Problem background

During the course of normal yield analysis, several lots were found to have a reticle site-dependent yield signature in which one of eight production die (site 7) had considerably depressed yield, as shown in Figure 1. It was immediately suspected that some sort of reticle defect was responsible for these repeated failures in site seven. Consequently, an effort was mounted to repeat the incoming Quality Check (QC) procedure for critical layer reticles of this particular product. The QC procedure consists of reviewing all critical reticles and test wafers printed from these masks for defects. This process did not reveal any obvious errors.

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F i g u re 1. Normalized distribution of functional die by reticle site for a typical lot. Si te 7 sho ws dramaticall y l ower y ield.

While the initial lithography investigation was ongoing, product engineering continued with end-of-line failure analysis. The analysis included using a custom test program that allowed the bit-level failures to be aggregated across multiple non-functional die. The output from this program indicated that, for site 7, two locations consistently failed more often than the rest, as illustrated in Figure 2. Taking note of these failing bit locations, chemical deprocessing of these wafers was carried out. Figure 3 shows the results of the strip-back process which revealed a single undersized contact that appeared likely to be the cause of the yield loss.

F i g u re 3. Wafer strip-bac k SEM revealed an undersized contact.

memory product reticles. The second goal was to understand the reasons for the shortcomings in quality control of incoming reticles. The final goal was to assess the impact of these defects on the process window in order to estimate the potential yield loss for the wafers already in progress.

The first repeater defect was found on a post-gate etch product wafer. Though the standard defect scan by KLA-Tencor’s 2132 inspection system at gate resist mask and after etch failed to detect the repeater defect, a technician was able to identify it during a manual SEM review. Following this operator feedback, a Photo Track Monitor (PTM) was run using the gate mask.

The Photo Track Monitor (PTM) or Photo Cell Monitor (PCM) is commonly used as a lithography

F i g u re 2. Orig inal electrical test r esults showing two columns fail dras tic ally mo re often tha n a ll others.

Lithography Analysis

Before the strip-back analysis was complete, the intra-field site-dependent yield information and bitmap coordinates were used to launch a lithography investigation. The first goal was to locate the repeater defect on the flash 26

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F i g u re 4. KLA-Tencor 2132 defect map for gate PTM (lef t) and K L A - Tencor 8100 SEM image of the ga te mask’s repeat er defect.

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F i g u re 5. Proc es s wind ow si mul atio n of non-defec tiv e and de fecti ve gate f ea tures u sing Av a n t i ’s Aeri al Image Ana lysis s oft ware on Sta rl i g h t S L 3 optica l i mages.

defect monitor and new reticle qualification check. The PTM sequence uses patterned photoresist on a flat silicon wafer followed by automated die-to-die defect inspection. Since this defect was caused by CD variation, the PTM wafer needed to be slightly underexposed to make the printing worse and, therefore, easier for the inspection tool to detect. In addition, the 2132’s sensitivity for the PTM recipe was increased to a setting much higher than that commonly used for product wafer inspection. This was possible because the printed resist-on-silicon wafer had a much better signalto-noise ratio than the topographically diverse product wafers. Figure 4 shows the resulting defect map and SEM image of the CD variation defect.

for non-defective and defective features, using this simulation software.

While the gate mask investigation was in progress, strip-back analysis determined that the electrical failure was in fact due to an undersized contact. Similar to the defective gate case, a contact reticle error was not detected either before or after etch on product wafers.

Further more, the standard contact PTM with resist pattern on silicon did not detect this defect. However, with the aid of bitmap coordinates and SEM images from the strip-back analysis, the 2132 recipe was re-optimized to the highest sensitivity to achieve successful detection. Again, this high-sensitivity recipe could not be used for product wafers due to excessive background

After this first repeater defect was identified, the gate reticle was re-inspected through the pellicle using the STARlight SL3 reticle defect inspection tool. The defect was much easier seen in reflection mode compared to transmission imaging. This is common for repairs, since they leave a stain easily apparent in the reflected image. The reticle was then sent back to the mask vendor and SEM measurements confirmed the defect to be a repair.

Once the defect image is captured by the STARlight inspection system, printability simulation can be used to predict how features and defects on the reticle will print on actual wafers. 1, 2 The reduced process window for the gate defect was simulated in this manner, using transmission data from the STARlight scan. Figure 5 shows the comparison of predicted process windows

F i g u re 6. KLA-Tencor 2132 defect map for contact PTM waf er showing und ers ized contact.

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F i g u r e 7. Proces s window simulation for non-defective a nd defective contact feat ures using Av a n t ! ’s Aerial Image Ana lys is software on KLA -Te n c o r ’s 353 optical ima ges.

noise. Figure 6 shows the defect map for a contact PTM wafer with the repeater defect successfully detected.

As demonstrated by the strip-back results, the defect in this case was a single undersized contact. Since this defect was not contamination, the STARlight SL3 contamination inspection tool did not detect this defect as would be expected. The reticle was subsequently sent to KLA-Tencor to be inspected using die-to-die mode on KLA-Tencor’s 353UV tool. This pattern inspection successfully detected the undersized contact. As in the gate case, the printed CD difference between nondefective and defective contacts was simulated using results from the STARlight scan. An example of the process window estimation by aerial image simulation is shown in Figure 7 using Avant! software in conjunction with the 353UV reticle transmitted image.

the actual functionality of the die, allowing an evaluation of the true process space when the lithography defect is combined with inline process variation outside of the lithography module.

Figure 8 shows the Focus/Exposure CD graph for the defective gate feature with overlaid process window for non-defective and defective features assuming ±10 percent CD control. This graph shows a significant reduction in the allowable process window for the defective feature compared to all others. Note, however, that a small process space exists which allows within-specification printability of non-defective and defective features on the same wafer. Inline SEM images were taken to compare non-defective and defective gate pattern features at opposite ends of the focus spectrum for worst case

Experiment

Once the presence and location of the reticle defects was confirmed on the printed Photo Track Monitors, a correlation study was run to compare the available detection methodologies. The study compared the predicted results from the lithography simulation software, inline defect inspection, and develop inspection CD measurements on printed FEM (Focus Exposure Matrix) wafers. To enable the yield comparison, an identical focus exposure matrix was run on the defective layers using full-flow production wafers. These electrically testable, product-based FEM wafers enable comparison between the empirically measured process window and 28

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F i g u re 8. Focus/exposure process window for CD defect on Poly mas k DUV resi st wa fer.

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F i g u re 9a. Electrically tested end-of-line process space for non-defective

F i g u re 9b. Electrical ly tested end-of-line process space for defective

die on gate-lay er pro duction FEM wafers.

die on gate-lay er pro duction FEM wafers.

exposure conditions. Though the printability of this defect was noticeably worse at positive relative focus, it did not appear to cause a silicon bridge at masking or after etch.

best opportunity for successful processing of both features occurs at a normalized dose of 1.12 and focus of 0.3.

After running the gate-layer focus exposure matrix, the product wafers received standard processing through the end of the line. The wafers were then electrically tested to determine the functionality of the product die. The results of this electrical testing are shown in Figure 9. In the figures, each pie icon represents the sort-bin distribution of all die processed at a given focus/exposure combination. Figure 9a includes all die with no repeater defects, and Figure 9b includes those with the known reticle error. Within each array, the approximate process window for functional die is highlighted in bold. From these maps, we can see that, although the functional process space for the defective die is reduced, a significant process window remains intact.

Next, a similar product wafer focus exposure matrix was run using the defective contact layer reticle. Figure 10 shows the Focus/Exposure CD graph for the defective contact with overlaid process window for non-defective and defective features assuming Âą10 percent CD control. In contrast to the gate defect case, this inline CD measurement suggests that there is no possible process that will allow in-spec printing of both the non-defective and the defective feature. According to this measurement, the

After completion of the inline analysis, the contact layer FEM wafers were finished with standard processing followed by electrical testing. Figure 11 shows the distribution of sort results for these wafers. The functional yield for all known non-defective die and the defective die is shown in Figures 11a and 11b, respectively. In contrast to the defective gate case, there is almost no allowable process window for this reticle error. The single functional point on the defective die occurs at a relative dose of 1 at nominal focus.

F i g u re 10. Focus/Exposure process window f or defective featur e on Contact mas k DU V r esis t wa fer.

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F i g u re 11a. Electrically tested en d-of -line process spa ce for non-

F i g u r e 11b. Electrica lly tested end-of -lin e process spa ce f or defec tive

defect ive di e on contact-layer productio n FEM wafer s.

di e on contact-layer productio n FEM wafer s.

Discussion

the simulation results, there should be no allowable process space for this reticle sizing error. The yield results agree, exhibiting only a single functional die at the center point of the contact masking process.

Recall that this investigation began with a single electrical failure and the subsequent detection of a single gate-layer repeater defect. It was not until after the precise location of the failure was determined electrically that the problem was confirmed to be due to a contact mask error. The known presence of two reticle errors, one subtle and the other slightly more obvious, along with one gross electrical failure, presented an ideal opportunity to study the process window of these defects and analyze why neither problem was initially caught.

For both the defective gate and contact cases, the inline process window measurement and the printability simulation correlate very well to the end-of-line yield.

Using the criteria that the lithography must allow simultaneous in-spec processing of both non-defective and defective features, the inline gate CD measurement predicted that successful printing was possible within a reduced window. Likewise, the simulation results predict the existence of an overlapping process window. In fact, the product wafer yield results agree with both of these estimates. As predicted by the inline product wafer CD measurement, the defective die yield is enhanced at higher exposure doses. As the lithography process moves toward the opposite end of the window, the defective die’s yield begins to fall off while the non-defective die continue to yield. The contact example tells a similar story. According to both the inline measurements and 30

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Reticle-quality verification faces two major hurdles.

The first is to determine the existence and location of the reticle defect; the second is to quantify its impact on the functionality of the device. This exercise has suggested that inline characterization techniques can do a reasonable job of predicting the yield impact of a known reticle defect. However, it says nothing about the ability to detect these subtle errors in the first place.

F i g u re 12. A t iered appr oach to reticl e-quality verification.

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As we have seen here, the currently installed tools for reticle and patterned-wafer inspection gave mixed results in the ability to reliably detect these defects. The newergeneration inspection tools, however, have been shown to detect this class of defects reliably. More importantly, the wafers inspected typically represent only one point in the allowable process space and exclude any variability outside of the lithography module.

To address these issues, the use of electrically tested product FEM wafers has proven very useful. The product based Focus Exposure Matrix provides valuable information at several levels. First, for reticles with more than one die per field, it provides process sensitivity information at the functionality level. Second, at the bit level, this technique can help to identify specific defect hot spots. Both of these outputs evaluate the full range of lithography process variation as well as interactions with other process modules.

Conclusion

Reticle defects can play a significant role in overall device yield. However, some “soft” mask errors may not actually result in yield loss. Detecting and quantifying the impact of these marginally printing reticle defects poses a significant challenge. This work has examined several of the methods available to identify and evaluate these types of defects. It has shown those early detection techniques such as printability simulation and inline CD measurement correlate well with end-of-line yield. However, these techniques are obviously useful only after defects are successfully detected.

Finally, the use of electrically tested product wafer FEMs at critical lithography layers has proven to be very valuable for in-depth product characterization.

To overcome the limitations and build on the strengths of each of these characterization techniques, we propose the implementation of a tiered approach to new productmask evaluation. Figure 12 illustrates how each of these methods might be implemented in different

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phases of the product development lifecycle, where each tier acts as a screening step for the next. At the mask shop, reticle scans coupled with printability simulation provide the first layer of defense. Once the masks are received in the fab, defect scans and criticaldimension measurements may eliminate additional errors. Finally, as the product development begins to mature, electrically tested FEM wafers can identify additional process interactions and product sensitivities.

Acknowledgments

The authors would like to thank Bernie Matt, Terrence Tong, Jack Thomas, Mark Ramsbey, and Dave Koon at AMD for their support of this work; Margo Gill and Amalia DelRosario for their excellent deprocessing and imaging of the subnominal contact; Mike Pochkowski at KLA-Tencor and Douglas Bernard at Avant! for the simulation work; Ed Hou and Bob Lane at KLA-Tencor for help with the KLA-Tencor 353UV and STARlight inspections, and Darren Taylor at Photronics (Allen, TX) for the KLA-Tencor 8100 Reticle SEM inspections.

References 1 . Donald Pettibone, Mohan Ananth, Maciej Rudzinski, Sterling Watson, Larry Zurbrick, Hua-Yu Liu, Linard Karklin, “Wafer Printability Simulation Accuracy Based on UV Optical Inspection Images of Reticle Defects”, Proc. SPIE Symp. Optical Microlithography XIII, Santa Clara, Calif o rnia, March 1999, Vol. 3677, pp. 711-720.

2 . Ingrid Peterson, Kaustuve Bhattacharyya, Enio Carpi, Darius Brown, Martin Verbeek, Douglas A. Bern a rd, “Investigation of Fast and Accurate Reticle Defect Assessment Methods using STARlight™ for Chrome-on-Glass (COG) Reticle Defects”, Proc. Of Photo Mask Japan, April 2000, Yokohama, Japan

A version of this article was originally published in the proceedings of the th 11 Annual SEMI/IEEE Advanced Semiconductor Manufacturing Conference and Workshop, September 12-14, 2000, Boston, Massachussetts, USA.

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