Magazine autumn99 improvedcopper

Improving Copper Process Integration Using E-Beam Inspection

by Patrick Dao, Staff Engineer, Motorola, APRDL This article is based on a transcription of a paper presented at the KLA-Tencor YMS seminar at SEMICON/WEST 1999.

It is generally well accepted in the industry that most of the large semiconductor houses currently use a 0.25 µm technology with aluminum metallization, perhaps one poly layer in the design, as well as up to about five layers of metal. Now, as the industry shifts into the 21st century, we’re seeing a big shift to higher layers of metal, and also designs that call for dual layer poly. But the biggest shift is from using aluminum interconnects to copper process technology.

This paradigm shift in the industry creates two different types of yield-limiting issues. The first issue has to do with the shift to dual inlaid copper technology. It is generally well known that copper technology introduces many unique copper defect types. From a yield enhancement standpoint, the number one question is whether we can discriminate the killer versus non-killer defect types that are scanned and detected in-line. As we increase the number of interconnect layers, one can clearly see that the device becomes a smaller portion of the overall process flow. So the emphasis then shifts from the front end to the interconnect yield in the back end. As Motorola exhibits leadership technology in copper processing, we realize that by improving our yield learning cycles, we can definitely bring more products to market in plain copper-based technology. Thus, we require an in-line failure analysis technique in order to accelerate our yield learning.

This article highlights how an automated e-beam inspection tool can catch both surface-related defects and embedded C-8

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defects within the via processing or the metal trench processing. For this example, we used a KLA-Tencor SEMSpec 2702 with random mode, which offers simultaneous physical and electrical in-line detection, with physical defect resolution down to 0.1 µm. Through voltage contrast imaging, we can catch electrical defects very readily. It has both a random and array mode capability. Random mode offers detect defection on a day-to-day basis, which serves many applications in our logic and DSP devices. The array mode offers defect detection on a cell-tocell basis, which we primarily use in our memory products.

It is fairly well known that copper introduces many unique defect types, which raises two questions. The first question is, how many can be electrically verified as yield limiters? The second question is, from these electrical verified yield limiters, how many of these can actually be consistently detected in-line? Currently, the traditional optical in-line inspections utilized at APRDL are inconsistent in the back end. This is because copper technology introduces what are called “cosmetic defects” — defects that are easily detected through optical inspections, and compromise the killer defect to signal-to-noise ratio. By utilizing an e-beam platform, we can take advantage of its built-in signal-to-noise advantage of current versus previous layer to catch only current layer physical defects. This naturally improves our killer defect detection. Also, because voltage contrast defects inherently have a high signal-to-noise ratio, we have a good methodology through sampling of voltage contrast defects. We are therefore confi-

dent that we can approximate the amount of voltage contrast defects that are still related.

sampling methodologies used to monitor our in-line defects, however, we reach a junction where this type of defect is poorly

Electrical Data

F a i l u r e Analysis

Yield Analysis

Electrical F a i l u re

In-lin e Defect

=

Hit!

F i g u re 1. Bitmap overl ay anal ysis verifi es cop per in-line defect “A” to be a yiel d l imiter.

Verifying a Yield-Limiting Defect This example actually reflects a real world problem seen at APRDL. We used a thin map overlay analysis technique to verify that an in-line copper defect was a yield limiter. However, it was difficult to quantify this defect, “A”, consistently using the current optical inspections, due to poor signal-to-noise ratio and resolution.

As a result, the other enhancements were delayed. Our solution was to utilize the SEMSpec to reliably detect this killer copper Defect A, and to verify the process solution to eliminate the root cause.

Figure 1 shows how bitmap overlay analysis was used to verify that the copper inline defect was a yield limiter. The image on the far right shows an electrical bit map signature (enlarged in the second image), where we correlate a physical inline defect to the electrical failure.

Through analysis we can determine that this is indeed a yield limiter.

This defect type is definitely caught inline through optical inspections. Due to

Normalized Defect Count: 1.00 Defect “A” Capture Rate: 100% Defect “A” Signal-to-Other Ratio: 7.2%

sampled in-line. Therefore, the amount of defect density for this type of yield killer is underestimated, and yield enhancement priority is focused elsewhere.

The inadequate sampling was traced back to the in-line optical inspection setup.

There were actually many previous defects flagged at the current inspection layer that were actually cosmetic. A top-down optical shot of a current metal layer with an underlying metal layer was evaluated, and many black dots were seen on the underlying metal layer. Most optical inspection tools will readily pick this up and thus confuse the number of defect counts in the overall sampling methodology. The previous defects were cosmetic and originated between consecutive inspection zones, and thus would not allow for defect source analysis to eliminate or filter them out in the sampling methodology.

As shown in figure 2, an extensive design of experiment was undertaken, using a wafer that generated a raw defect count on the SEMSpec scan using random mode,

Normalized Defect Count: 14.98 Defect “A” Capture Rate: 10% Defect “A” Signal-to-Other Ratio: 0.05%

F i g u re 2. Copper killer d efect d etection .

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indicating that it had the defect of interest.

This was the normalized defect count, and we made the assumption that, in this area of the SEMSpec scan, out of all the defects classified, the Defect A capture rate would be 100 percent. This gives a Defect A signal-to-other ratio of about 7.2 percent.

If you compare that to the baseline optical zone monitor, which is currently being used, you can clearly see that the normalized defect count is about 15 times greater.

However, the Defect A capture rate is only 10 percent, compared to 100 percent for the SEMSpec. Therefore, the signal-toother ratio is definitely less than 1 percent.

Normalized Defect Count: 67.68 Defect “A” Capture Rate: 43% Defect “A” Signal-to-Other Ratio: 0.05%

the same, in comparison to the baseline optimization.

On the other end of the extreme, the signal-to-other ratio can be maximized by suppressing the noise, as was done here.

The normalized defect count now approximates what the SEMSpec count generated.

However, the Defect A capture rate is definitely much less, at 8 percent. This showed that the SEMSpec can be utilized to accurately approximate and catch the number of yield limiting defects on the surface of copper layers.

Normalized Defect Count: 1.04 Defect “A” Capture Rate: 8% Defect “A” Signal-to-Other Ratio: 0.56%

F i g u re 3. Def ect count with c hanges to sensitivity.

The design of the experiment also tried to improve the signal and minimize the noise. In this case, you can maximize the sensitivity to try to improve the signal-tonoise ratio. Figure 3 shows that the sheer number of raw defect counts is overwhelming, and in the sampling methodology, it is more than likely that this type of defect would be missed. The normalized defect count increased dramatically to 67 times the number versus the SEMSpec. More of the defects were captured, although not even half of those that were detected by the SEMSpec. The defect signal-to-other ratio actually stayed

Better

As we shift to inlaid copper technology, the shift to interconnect yield accents the integrity of these inlaid features, and obtaining qualitative results using the current optical in-line inspections is challenging. One reason is that the resolution used to determine the good and marginal interconnects is insufficient. At APRDL, we utilize a specialized decoration etch technique to improve the resolution.

However, there are many drawbacks to this technique. The first drawback is that it introduces noise into the inspection results, and thus weakens confidence with the data conclusions. Another drawback is that the

Wo r s e

F i g u re 4. SEMSpec identi fies var ying degre es of via interconn ect i ntegrity.

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analysis wafer is sacrificed and cannot continue on with the process for further inspection at the end of line. With the e-beam inspection tool, we have proven its value for inlaid processing in copper. The resolution between modular and good

SEMSpec identifies marginal via processes on identical stru c t u re s

figure 5. The defects flagged here clearly indicate that they were much different from the neighboring structure and the reference image in the next available die.

In other areas of random logic, we identified missing vias, which were completely

SEMSpec identifies missing vias in random logic areas

F i g u re 5. Defect det ection of via i ssues.

interconnects is excellent, and there is no special process prep required. The scans can be done at either post via etch or the subsequent metal CMP layer. If warranted, the analysis wafers can continue with processing at the end of line for more learning.

Figure 4 shows the SEMSpec’s ability to identify varying degrees of via interconnect integrity. For example, the image on the left would normally suggest a good open via. Whereas, if you move down the scale, you can clearly see that the SEMSpec can differentiate between a marginal via, an incompletely etched via, and a closed via. This has been routinely used in APRDL to improve our via processing.

In other aspects, by leveraging the random mode capability, we’re able to identify marginal via processes on identical structures, as shown by the SEM micrograph in

SEMSpec scan showing missing vias on initial production tool perf o rm a n c e

undetected using an array mode scan or the conventional e-beam technique of just searching for missing vias.

We also used the SEMSpec to correlate electrical results with SEMSpec defects caught in-line. A plot was taken of a metal stat test structure which measures contact resistance and Ohms for contact.

For this example, the fallout was determined to be about 30 percent. The SEMSpec was then used to find certain errors within this logic circuit, and scanned. FIB cuts were also done. There were two problem areas with one via layer, and another problem with a second via layer. The FIB cut revealed two different root cause failure modes. In one case, the via was completely open, and in another, the via was marginally open. The SEMSpec was able to pick up both types of defects.

SEMSpec scan after production tool fix

F i g u re 6. Produc tion tool fix bas ed on SEMSpec re s u l t s .

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This should clearly show that by using an e-beam-based inspection tool, via processing can be significantly improved by utilizing the random mode capability, as well as the array mode capability of the SEMSpec.

F i g u re 7. SEMSpec

Validation of process tools

detects voltage contrast defects at

It is clear that copper process technology presents obstacles to a production rampup. This is because different tool sets may exist between a development fab and a production fab. More often than not, in a development fab, the process module may require a transit from a different tool set to a more improved tool to continue the process development. E-beam inspections have been used to assist in the validation of process transferability between production fabs, as well as when switching to another type of development tool. The inspection tool’s ability is leveraged to analyze large areas of the device. This technique is also used to supplement current physical and parametric analytical techniques, strengthening the confidence in the process transfer.

post Metal -CMP.

F i g u re 8. SEMSp ec in -lin e via tre n d .

Figure 6 shows a SEMSpec scan that revealed missing vias in the trenches on initial production tool performance. The tool had been deemed “transferable” and was ready to be transferred to the production fab. This was not acceptable. After the processing engineering group came up with a production tool fix, the SEMSpec scan validated that these vias were being printed correctly, so the process transfer could occur.

Another wafer was taken at post-metal CMP and scanned on the SEMSpec using a different production tool. Figure 7

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shows that the SEMSpec caught a voltage contrast defect to the metal structure in the areas that were scanned.

The initial FIB slice showed in the voltage contrast defect that there was some type of defect within this via layer. Upon magnification, it was shown to be a fill-related problem. An additional FIB slice showed that this fill-related problem wraps around the structure of the via, causing continuity problems. This type of defect increases the metal resistance and thereby causes the voltage contrast signal seen by the SEMSpec. In this way, a SEMSpec was used to identify partially open vias, which is very difficult in most conventional cross-section SEM analysis.

Using a process transferable method

An in-line via trend of the development tool is benchmarked, as shown in figure 8.

Using the SEMSpec, we were able to show that for the next five lots going through, we eliminated the voltage contrast defects, but kept it on par with the development tool. This was very crucial in our yield learning for copper.

The industry shift toward copper presents many types of issues with interconnect layers. Because the majority of the process flows resides in the back end, the back end process plays a much larger role in yield enhancement. Automated e-beam wafer inspection has been shown to be valuable in three cases. First, for improvements in copper killer defect detection in-line. Second, the identification of inlaid process issues identified weak points in the modules, and isolated the root cause through the process sections. Finally, for validation of process tool readiness by determining the transferability of the process to production fab. ❈ cir cle RS#029