Magazine autumn99 copperinterconnect

Cover COPPER INTERCONNECT — AN ENABLING TECHNOLOGY FOR FUTURE SCALING

Story

by Arun K. Chatterjee, Senior Director, Interconnect Solutions

t is widely known that the perforI mance of integrated circuits using

sub-0.25 µm technology will be highly influenced by device interconnects.1 Interconnect scaling is also a critical determinant for future increases in circuit density, especially for logic and microprocessor products. The interconnect solution for a given technology must address the performance, density and reliability requirements of a given product. In addition, as higher levels of interconnects for future logic and microprocessor products are needed (as shown in the figure 1), the interconnect strategy has to provide cost effective solutions for yield management and wafer manufacturing. In this paper we will review (1) material and process architecture considerations, (2) adoption and reliability of emerging interconnect technologies, and (3) the yield management considerations for sub-0.25 µm interconnect solutions.

Materials and device architectur e

What is the sub-0.25 µm interconnect solution? Is it copper, low-k, or copper and low-k? While it may be debatable whether a lower resistance material (like copper) or lower-k inter-layer dielectric (ILD) is the best approach for 0.18 µm technologies, it is apparent that both higher-conductive material and lower-k ILD will be

F i g u re 1. In fluence o f material on number of metal interc o n n e c t s .

required for sub-0.15 µm technologies. The path to implementing both lower-k and higher-conducting materials will depend on the product type and its design methodology. Table 1 provides an overview of this complex issue.

The columns reflect the technology generation, the rows represent various interconnect solutions. The k for low-k material is assumed to be 2.5.

The 0.35 µm technology with polycide gate, aluminum interconnect and standard SiO2 (k = 3.9) has been given a relative delay value of 1. Any combination whose value is greater than 1 will result in a slower product. Similarly, any combination that has a value lower than 1 will result in a faster product. Grouping the interAutumn 1999

Table 1 a. Relati ve dela y.

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Tab le 1b. Relative delay o f m ix e d d es ig n ru l e s (tran sistor is one generation ahead of inte rc o nnect).

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connect solutions with relative delay normalizes the effect of conductor thickness and length. While table 1a provides various alternatives, it is apparent that at 0.13 µm design rules both higher-conductive and lower-k materials are required.

One can delay the implementation of copper and low-k materials by using mixed design rules. Smaller feature size requires

F i g u re 2. Subtr active vs. dual -damasc ene p ro c e s s f l o w.

F i g u r e 3. SIA ro a d m a p a nd int erconnect adoption t re n d .

decreased metal pitch to effectively route signal lines by increasing available channels per cell. In contrast, increased metal pitch improves the performance.

Therefore, keeping the interconnect design rules a generation behind that of the transistor can greatly improve product performance at the cost of product density (transistor/logic per unit area), when a given product is not limited by its bonding pad design.

The concept of mixed design rules is not new — products whose die sizes are limited by the bonding pad density tend to benefit from this approach.

Mixed design rules also allow semiconductor manufacturers to effectively increase the life of existing process tools and technology.

However, table 1b suggests that for sub0.13 µm technology both copper and lowk material will be required.

In addition to changes in material for both conductor and inter/intra-level insulator materials, the architecture is also changing. Figure 2 shows the change in process architecture from subtractive aluminum to dual-damascene copper technology.

The dual damascene architecture not only reduces the processing steps by 20 percent, it also allows the manufacturing facility to use the current lithography tool set to scale the interconnect geometry. This is because printing and etching on an oxide insulator surface is easier than that on a reflective grainy metal surface. Therefore, the line width control and the continuity of smaller line-width for a damascene structure will be superior to that of a subtractive structure. As a result, the average product reliability for damascene metal will be higher than that for subtractive metal.

Copper and low-k ILD adoption trend

Figure 3 summarizes the present trend of interconnect solutions in general, especially for microprocessor and logic products. The X-axis represents the minimum feature size and the Y-axis represents the year of technology introduction to production per the latest SIA roadmap. It is interesting to note that both aluminum and copper will co-exist for 0.18 µm and 0.15 µm technologies. Hence, the industry will be in transition phase during these technology generations. For sub-0.15 µm technology,

Table 2. Activa tion en ergy of several interc o n n e c t material.

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F i g u re 4. Layout methodology vs. ele ctro m i g r a t i o n .

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carrying capability for different metal reservoirs.

Process control and yield management challenges

Table 3. Current carr yi ng capability for various re s e rv o i r s .

copper appears to be the dominant interconnect conducting material.

Reliability considerations

For a given operating temperature and current density the electromigration lifetime depends on both material and design factors. Copper, having a much higher activation energy, will significantly improve electromigration lifetime. Several studies2,3 suggest that for a given layout the current density required to prevent electromigration for copper could be as high as 5x106 A/cm2 compared to 2x105 A/cm2 for aluminum. However, one should keep in mind that electromigration can be increased by using refractory sandwich materials – such as, TiN/Ti/Al-Cu/Ti. However, refractory sandwich materials will increase the resistance of the conducting lines. Table 2 summarizes the current published activation energies for aluminum, copper, aluminum alloys and composite aluminum structures.

Electromigration lifetime is also a function of layout methodology for a given operation. Figure 4 shows that layout methodology can significantly increase the lifetime of a given conductor line. When the current flows towards the “A” direction, the electron will flow towards the “B” direction. Therefore, the metal reservoir will be either “small” or “medium” depending on the length of the narrower width metal line. However, if the direction of the current is reversed, the metal reservoir will be large, which will significantly increase the current carrying capability of the interconnect line. Table 3 summarizes the current

The major line monitoring and yield management challenges in the future are (1) high aspect ratio via and metal-trench with scaled geometry, (2) a new process architecture (dual damascene), (3) new materials (low-k for dielectric and copper for conductor), (4) contamination control (mainly from cobalt and copper) and (5) limited industry experience in copper dual damascene technology. In addition, technology transfer in the manufacturing ramp phase must be accomplished at higher yields for future technologies to remain ahead of the competitive curve.

Figure 5 provides the trend in electrical fault density, Do, with respect to technology migration for best practice manufacturing.

From figure 5, it is evident that, for best practice manufacturing, the fault density for 0.18 µm technology needs to be less than 0.18 per cm2. For 6- level metal technology, this translates into one defective via or contact per 3.6 billion contacts or vias.

To ensure proper line monitoring to meet this requirement, both physical and electrical on-line defect detection capabilities will be required. For on-line electrical defect detection, “non-contact” testing, e.g. voltage contrast techniques, will be needed.

Therefore, e-beam inspection technology will be very critical for future line monitoring of interconnect processing steps.

F i g u r e 5. Electrical fault dens ity (D o) tre n d .

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F i g u re 6a. Killer vs. nonkiller d efects.

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the defect detection methodology should focus on detecting primarily the “killer” defect types. Not all defects are killers. While it may be of some use to develop a correlation between killer and non-killer defect type and distribution, it is essential that the initial focus be on detecting killer defects. For example, the defects inside the via-metal trench are more critical than the defects on the spaces between via-metal trench lines for dual damascene structures, as shown in figure 6a, where “M” represents the metal lines and “V” stands for vias.

Similarly, embedded (or sub-surface) defects in ILD which were non-killer defects due to the advent of CMP technology will be killer defects as we etch metal trenches that account for 30-40 percent of the die area as shown in figure 6b.

F i g u re 6b. Kill er vs. nonkiller d efects.

While e-beam technology is superior for detecting defects inside high aspect ratio “stacked” via and metal trench structures, optical inspection technology provides the most cost effective solution for embedded film defects. Therefore, future inspection strategies will require both e-beam and optical inspection tools. This in turn requires establishing a correlation between the two types of inspection technologies, based on advanced statistical models and methodologies.

F i g u re 7. Defect lea rning rate vs. yiel d management meth odol ogy.

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Defect learning and process module control (PMC) solutions

The defect (electrical fault density) learning trend has been increasing steadily for the last 15 years4, as shown in figure 7.

Initially it was the adoption of SPC that helped the defect learning process. During the early 1990s, the learning process was significantly increased through the adoption of advanced defect detection technology and intelligent line monitoring methodologies. Further increases in defectivity learning have been accomplished by using advanced yield management technologies that effectively integrate defect and parametric measurement tools, analysis and review tools, and best practice yield management methodologies.

In recent years, however, it has been observed4 that both defect learning rate and defect learning cycles can be improved by controlling each process module and establishing a defect/parametric correlation between process modules — for example, CD variations with respect to film thickness variations, or void formation during copper electroplating with respect to “as deposited” barrier layer thickness for a given deposition condition. Comprehensive defect modeling with respect to process module parameters and defect source database, will enhance defect learning.

Process modules can be divided into four major categories: (1) Film (i.e, material formation phase that includes deposition, implant, diffusion, etc.), (2) Lithography (i.e., image formation phase that includes reticle, resist, and exposure technologies), (3) Etch (i.e., material removal using plasma chemistry) and (4) CMP (i.e., material removal through chemical-mechanical polishing).

For sub-0.25 µm technologies, the major source of particle type defectivity will be process induced5 as indicated in figure 8.

Therefore, defect learning from one process

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1. M.T. Bohr, IEDM Technical Digest, P241-244, 1995.

2. Y. Arita, Semiconductor World, P158, December 1993.

3. D.B. Knor r, Proc. MRS Spring Symp., P75, April 1995.

4. KLA-Tencor, Yield Management Consulting Database (unpublished), 1996-1999.

5. ICE, Midterm Status Report, 1996.

F i g u re 8. Trend of pa rti cle defect ivity sourc e .

module can be applied to another process module, shortening the learning cycle.

Summar

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The combination of copper and low-k dielectric materials with dual damascene device architectures is the preferred interconnect solution for sub-0.15 µm technology. However, several manufacturing and yield management issues have to be optimized before we can realize the yield and cost benefits. The present key manufacturing and yield management issues are: (1) an optimized CMP solution for copper and barrier material, (2) optimized CMP selectivity of low-k dielectrics, (3) optimized void free copper electro-plating technology, (4) effective inspection technologies for high aspect ratio trenches, embedded film particles and sub-surface voids in the conductor lines, (5) intelligent correlation software and on-line electrical fault detection technology for each level of interconnect and (6) sufficient availability of experienced resources.

Timely solutions for some of the above manufacturing issues will require a closer partnership between the device manufacturers and equipment vendors. Since the major source of particle defectivity will be process induced for sub-0.25 µm technologies, a closer working relationsip between process-module equipment vendors and process-control equipment vendors will be needed to accelerate both yield learning and process module technology developments. ❈

Acknowledgements The author would like to thank the corporate marketing and yield management consulting groups for providing numerous helpful informa tion. Special thanks to Tom Long for many insightful discussions and Kern Beare for assisting in editing the manuscript.

About the Author Arun K. Chatterjee has an MS in Materials Science.

He has over 23 years of semiconductor technology and operations experience. He has held several management positions in CMOS and BiCMOS device development and process integration at Fairchild, Signetics, AMD, Data General, Synergy Semiconductor and Cirrus Logic. At Cirrus Logic, he also managed the advanced CMOS technology alliance with IBM and MiCRUS. In 1996, he joined KLA-Tencor’s Yield Management Consulting group and is currently Senior Director in Corporate Marketing focused on the company’s Interconnect Solutions strategy.

Contact Information KLA-Tencor 160 Rio Robles San Jose, CA. 95134 Tel 408.875.2372 Fax 408.875.4144 Email: arun.chatterjee@kla-tencor.com Autumn 1999

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