VOLUME I ISSUE
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AUTUMN 1998
$5.00 US
Yield Management
S O L U T I O N S Yield Enhancement and Process Control Strategies for the Semiconductor Industry
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COVER STORY: LITHOGRAPHY DEFECTS — THE HIDDEN YIELD KILLERS
13 IDENTIFYING PROCESS DRIFT WITH CD SEMS 25 INSPECTION IMPLICATIONS A DESIGN RULE SHRINK
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Lithography 11 Stepper Focus Metrology and Analysis using a Phase Shift Mask Phase shift focus monitor reticle and analysis software enable a quantitative measure of the best focus position. 13 Identifying Process Drift with CD SEMs While critical dimension is the standard metric on which CD SEM monitoring is based, other and potentially more sensitive metrics are available from the same tool. 16 Analysis of ESD-Induced Reticle Defects ESD damage to reticles can result in critical yield losses, but there are methodologies that can minimize the potential for such damage. Analysis 20 Image Management: A New Approach for Yield Analysis Automated storage and retrieval of images generated by inspection, metrology and failure analysis tools can expedite root cause analysis of yield excursions. 22 Yield Enhancement with Bitmap Analysis Review of failing bit data is an essential tool for improving yields in memory arrays, and an analysis of failing bit patterns can help pinpoint the cause of bit failures. Inspection 25 Inspection Implications of a Design Rule Shrink Defect inspection systems and strategies are changing as a result of shrinking design rules, new technologies, materials and financial considerations. 29 Automatic Defect Classification: A Productivity Improvement Tool ADC minimizes cost of excursions by eliminating inaccuracies and inconsistencies associated with manual defect classification and review. 2
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Cover image by Luie Lopez, Stephen Marley Productions
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Lithography Defects — The Hidden Yield Killers In today’s environment of rapidly shrinking geometries and increasing device complexity, minimizing defect density has become increasingly critical to maintaining high yields. For the lithography engineer, this means that defect density is now as important a concern as critical dimension and overlay metrology in the development and implementation of lithography processes.
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Metrology 37 Monitoring of Low Dielectric Constant Parylene Films using Spectroscopic Ellipsometry New data collection and analysis algorithms are required to measure thickness and refraction on new low dielectric constant films. 41 Tungsten Plug Measurement for CMP Development and Production Automated high-resolution profiler provides an effective method to measure tungsten plugs post-CMP.
News
46 362 Reticle Inspection System AMRAY 4000 Series Defect Review SEM Systems 47 Windows NT for Thin Film Measurement Tools HRP-220 High-Resolution Profiler KLASS PSF Phase Shift Focus Monitor
Corporate 44 Bringing the Future into Focus Excerpts from KLA-Tencor’s SEMICON West ’98 video, which featured interviews with industry leaders Mark Melliar-Smith, President and CEO of SEMATECH; Dale Harbison, Vice President of Texas Instrument’s Semiconductor Group; and Sung W. Lee, President of Samsung Austin Semiconductor.
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Editorial: An Opportunity for Growth
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Business News
Yield Management Solutions is published by KLA-Tencor Corporation. To receive Yield Management Solutions contact Corporate Communications at:
To complement and expand its Intelligent Line Monitor (ILM) solution, KLA-Tencor recently acquired DeviceWare, a provider of leading bitmap analysis software, and VARS Inc., a leading supplier of image archival and retrieval systems. 19 Industry Viewpoint: Bridging the Gap to 300 mm Wafers The industry needs cost-effective strategies to facilitate the transition to 300 mm wafers. According to Dan Hutcheson, VLSI Research, one of the most promising strategies is the use of bridge tools.
KLA-Tencor Corporation 160 Rio Robles San Jose, CA 95134 Tel 408.875.4200 Fax 408.875.4144 www.kla-tencor.com For literature requests call: 800.450.5308
34 Yield Management Seminar Series YMS at a glance.
©1998 KLA-Tencor Corporation. All rights reserved. Material may not be reproduced without permission from KLA-Tencor Corporation. Products in this document are identified by trademarks of their respective companies or organizations.
35 Best of YMS Inspection of Advanced OPC Reticles. 36 KLA-Tencor Autumn ’98 Trade Show Calendar 43 Q & A KLA-Tencor’s Yield Management Consulting Group.
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Editorial
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EDITOR-IN-CHIEF Roberta Emerson
An Opportunity for Growth
MANAGING EDITOR Judy Dale CONTRIBUTING EDITORS Kern Beare Carol Johnson Kavitha Kannan Robert Mendoza A S S O C I AT E E D I T O R Kevin Clover E D I T O R I A L A S S I S TA N T S Lars Ahntholz Petra Donnelly Janet Ely Holly Nielsen
It is too easy to look at the current state of the industry and see only the economic impact of the Asian financial crisis, the slowing demand for semiconductor-based products, and the resulting closure or cancellation of fabs. But long-time industry watchers and experienced management teams know that this is also an opportunity for the industry. Just below the surface of this “doom and gloom” outlook lies tremendous momentum toward the exciting new technologies and developments required to meet the evolving demands of the semiconductor roadmap and the information age. Now and in the future, yield enhancement strategies and process control improvements significantly impact the success of every fab. Achieving profitability continues to drive fast ramp speeds, reduced costs and higher return on investment. At the same time, technology
developments, such as those discussed in this issue, will be critical to the implementation of new processes and circuit designs. Phase shift masks and other key lithography developments, automatic defect classification, comprehensive yield analysis, and the measurement of new films and materials, will all play an important role.
ART DIRECTOR AND PRODUCTION MANAGER Shirley Short D E S I G N C O N S U LTA N T Carlos Hueso C I R C U L AT I O N Cathy Correia
KLA-Tencor Worldwide C O R P O R AT E H E A D Q U A R T E R S
The most visionary companies will see this period as an opportune time to enhance their technologies, their products and processes. The most savvy individuals will see this as a time to learn new technical skills and gain expertise for when the cycle turns up again. This industry downturn is an opportunity to expand our technical horizons and establish a new platform from which to create again the kind of extraordinary changes that this industry has been responsible for throughout its history.
KLA-Tencor Corporation 160 Rio Robles San Jose, California 95134 408.875.4200 I N T E R N AT I O N A L O F F I C E S
KLA-Tencor France SARL Evry Cedex, France 011 33 16 936 6969 KLA-Tencor GmbH Munich, Germany 011 49 89 8902 170 KLA-Tencor (Israel) Corporation Migdal Ha’Emek, Israel 011 972 6 6449450 KLA-Tencor Japan Ltd. Yokohama, Japan 011 81 45 335 8200 KLA-Tencor Korea Inc. Seoul, Korea 011 822 41 50555 KLA-Tencor (Malaysia) Sdn. Bhd. Johor, Malaysia 011 607 557 1946
Roberta Emerson Vice President, Corporate Communications
KLA-Tencor (Singapore) Pte. Ltd. Singapore 011 65 782 6788 KLA-Tencor Taiwan Branch Hsinchu, Taiwan 011 886 35 335163 KLA-Tencor Limited Wokingham, United Kingdom 011 44 118 936 5700
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Focus on Yield New bitmap analysis and image management solutions offer accelerated yield learning
KLA-Tencor recently acquired two privately held companies to complement and expand its Intelligent Line Monitor (ILM) solution, which integrates automated inspection, classification and analysis capabilities for real-time excursion monitoring and accelerated yield learning. DeviceWare, a provider of leading bitmap analysis software, and VARS, Inc., a leading supplier of image archival and retrieval systems for semiconductor equipment, were acquired in June, 1998. Bitmap line monitor speeds failure analysis The DeviceWare acquisition will allow KLA-Tencor customers to systematically collect and analyze electrical bitmap data, and then automatically merge that data with inline defect data using the Klarity Defect Data Analysis System. By being able to automatically correlate bitmap failures to physical defects, fabs can more quickly identify true yield-killing defects for accelerated yield learning. “With this capability,” said Glyn Davies, senior director of marketing, Yield Management Software Group, “we are essentially integrating automated test equipment into our overall ILM solution, enabling rapid and ongoing feedback on the failure mechanisms of a device for faster resolution of yield problems.” The bitmap analysis system collects bitmap data from a range of automated test equipment — including memory testers, logic testers and
mixed signal testers — and then automatically translates the electrical addresses of the failed bits into the correct physical locations on the die. In addition to sending the translated bitmap data to Klarity for automatic correlation with inline defect data, the converted bitmap data can also be automatically analyzed for failed bit patterns using powerful yet intuitive visualization tools, including full wafer bitmap viewing, wafer stacking, bin data overlay, die stacking and more. KLA-Tencor’s new bitmap solution is designed for all manner of memory, including SRAM, DRAM and EEPROM. It can also be used in the growing embedded memory caches of DSP, MPU, MCU and ASIC devices. Image management adds synergy to inspection, metrology and analysis products Image management has become an increasingly important part of the diagnostic process, providing critical information about the nature and source of yield-limiting process problems. The acquisition of VARS, Inc. gives KLA-Tencor a comprehensive image management solution, adding synergy to the company’s portfolio of industry-leading inspection, metrology and analysis capabilities. KLA-Tencor has worked closely with VARS for several years, developing data retrieval and archival capabilities for products such as the CRS Review Station and AIT Inspection System.
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The VARS Image Management System.
The VARS Image Management System stores and retrieves images generated from a broad variety of on-line and off-line equipment, including defect review stations, scanning electron microscopes, metrology systems and focused ion beam systems. Images and data are stored automatically in a single database and made quickly available through powerful database search engines. More than 60 systems are installed in semiconductor facilities worldwide. Previously, fabrication plants used Polaroid, video prints and other slow means of photography to document chip defects and other anomalies. VARS revolutionized the imaging industry by providing semiconductor manufacturers with a high-speed, high-capacity tool to display defect problems on computer monitors instantly as they occur.
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LITHOGRAPHY DEFECTS — THE HIDDEN
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YIELD KILLERS
Importance of Defect Reduction in the Lithography Module by Ingrid B. Peterson, Ph.D.,KLA-Tencor Yield Management Consulting
of the most important chalO nelenges in the implementation
and development of DUV and advanced i-line lithography processes is maintaining low-defect density in order to minimize the impact on yield. As geometries shrink and chip size increases, defect reduction becomes increasingly critical. The lithography engineer is now responsible for more than creating resist patterns on wafers; defect density is now just as important as critical dimension and overlay metrology in the development and implementation of lithography processes. Today’s lithography processes are very complex, and most process flows have twenty or more lithography steps. Implementing these processes successfully requires attention to yield and device performance as well as to critical dimensions and overlay. Lithography defects, therefore, can have a great impact on wafer probe yields, preventing them from being 100 percent, and thus impacting the cost and reliability of semiconductor devices. Even in the cases where lithography defects (equipment or process integration) appear to be cosmetic, the defects can have a 15-20 percent impact on yield. These defects are also very difficult to detect on product because they: 1)
have low topography; 2) optically appear as only a subtle color variation; 3) are very small (<< 0.5 Âľm); and 4) in many cases, are not visible under optical review. Therefore, effective defect monitoring procedures need to be implemented(1,2) and the defect inspection tool carefully selected. Examples of some of these defects and their causes are presented here in order to illustrate the nature of lithography defects, emphasizing their impact on yield and the importance of using the appropriate pattern wafer inspection tool to detect them. Also, this article discusses the importance of test wafer monitors as a means of detecting these defects; however, this subject is covered in more detail in References 1 and 2. Low topography defects: developer spots
In many fabs, a common problem that frequently goes unnoticed is the presence of developer spots, shown in figure 1. This defect is easily detected on an unexposed, resist-coated wafer that has been developed with a standard production recipe. Developer spots, caused by splashback during the rinse cycle, are not visible on bare-silicon wafers. This is a consequence of surface tension differences between a resist-coated Autumn 1998
Figure 1. Example of a developer spot.
wafer and a bare-silicon wafer. Brightfield, narrow-band defect inspection tools are the best choice for detecting developer spots since they are a low-topography, colorvariation defect. The lack of scattering edges on these defects prevents them from being detected on darkfield laser light scattering inspection tools. They vary in shape and size, from 1 to 20 Âľm in diameter; and they occur on developer equipment from different vendors. Possible
Figure 2. Wafer map showing the developer spots on the perimeter of the wafer.
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causes are poor exhaust in the developer cup, developer cup design, and type of developer nozzle. These defects are commonly detected on the perimeter of the wafer (see figure 2). The light-colored spots are clustered defects and the dark-colored spots are unclustered defects.
Figure 3. Effect of a developer spot on product.
In-line monitoring of production lots often shows that this defect type can block non-aggressive etch steps, such as nitride and thin masking oxides. An example of a defect blocking an etch step is shown in figure 3. In this example, the developer spot was probably created after the wafer finished its develop drying cycle. This spot blocked the nitride etch and subsequently inhibited the growth of the field oxide. Color variation defects: spots
Figure 4. Spot defect type caused by EBR splashback.
This general category of defects includes those that are generated during the coat process. They depend on the contact angle between the resist and developer and are residues generated by resistdeveloper interactions. Since these defects appear as color variations or stains on wafers, they are best detected by brightfield, narrowband pattern wafer inspection tools. They are also best detected on resist on silicon test wafers, rather than on product wafers. The signal-to-noise ratio is very low on product wafers due to the color variation contribution from previous process levels and defects from previous layers, causing these defects to escape detection during after-develop inspect, ADI. Figure 4 shows an example of a very common coat defect, EBR (Edge Bead Removal) splashback, which leaves a stain on the wafer. The color variation represents resist thickness variations which cause CD variations and pattern deformations on product and, therefore, impact yield.
The next example shows how very cosmetic-looking stains or spots can have serious impact on yield by blocking contact or via openings. This defect type has been shown to cause yield losses up to 20 percent. The origin of the residue which causes the spots or stains varies. It can be caused by developer precipitates, resist-developer interaction or resist and developer surfactant bonding. In many cases the stain is so subtle it will not be observed during optical review; it is detected only on brightfield inspection tools due to the high sensitivity of TDI (Time Delay Integration) technology. Figures 5 and 6 show this defect type blocking a contact opening. Figure 6 shows a confocal microscope scan of the blocked contact in figure 5. As this scan clearly shows, the first two contacts (left to right in figure 5) are clearly open, the third contact is partially blocked, and the fourth is completely blocked. The spatial distribution of this defect type is very dense (as shown in
Figure 5. Optical image of stain defect blocking a contact (from 2100 series inspection system).
Figure 6. Results of a confocal microscope scan of the defect in figure 5.
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Figure 7. Spatial distribution of the stain or spot defect shown in figure 5.
figure 7), radially outward, and follows the pattern on the wafer. The spatial distribution also is very useful in identifying the defect sources because it gives clues to possible mechanisms responsible for a particular defect. In this case, it indicates how this residue affected the wafer during the develop-rinse cycle. E2 nozzle spatial distribution
The next defect examples fall into a very characteristic spatial distribution called the E2 nozzle spatial distribution (shown in figure 8). The E2 nozzle is a proprietary means of dis-
Figure 8. E 2 nozzle spatial distribution.
Figure 9. Color variation defect.
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pensing developer used on TEL tracks. This is a very clean type of dispense; however, when it has defects, they tend to fall along a straight line, making it very easy to detect and trace back to the source. It is important to point out that the defect types which fall along the straight line pattern occur on all developer track equipment and are not unique to the E2 nozzle means of dispense. Only the linear distribution is unique to the E2 nozzle.
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Figure 10. Residue defect.
The defect types seen with this kind of spatial distribution are: critical dimension, CD variation, pattern bridging, and extra pattern (shown in figures 9, 10 and 11). Figure 9 shows an optical image of a defect that has the spatial distribution of figure 8. The profile and CD of the contact features under the rose color are dramatically different than those under the green color. This is a color variation defect detected on product after ADI and on test wafer monitors with a KLA-Tencor 2135. The test wafer monitors, resist pattern on silicon, provide much higher sensitivity than the product inspection. In the defect type pareto analysis chart, this defect was number one for the test wafer monitor and number eight for the ADI inspection on product, emphasizing the importance of effective defect monitoring.
Figure 11. Developer bubble defect.
The residue causing the bridging of the pattern in figure 10 also has the spatial distribution of figure 8 and can be caused by contamination of the developer dispense nozzle. Figure 11 shows another common defect caused by the development process. This defect is a result of N2 bubbles during the develop part of wafer processing. These bubbles are a consequence of supersaturation of N2 in the developer liquid which prevents the underlying area from being developed. The size of this Autumn 1998
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defect varies from submicron diameter to as large as 10 µm. The photo defects illustrated in this article are ones that are usually thought to be cosmetic; however, as shown by these examples, they can block contacts, cause bridging, missing or extra pattern and CD variation. Because these defects are low topography, have low scattering cross sections, show color variations, or are a consequence of resist film thickness variations, they are best detected by brightfield, narrow-band pattern wafer inspection tools, combined with effective test wafer monitor procedures1, 2. Test wafer monitors consisting of resist pattern on silicon provide much higher sensitivities compared to ADI on product. The days are past when fab engineers could concentrate on specific module
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parameters without considering the total impact on yield and productivity3. In today’s highly competitive semiconductor marketplace, both fab engineers and fab managers must be aware that lithography defects, even seemingly cosmetic ones, can greatly impact a fab’s yield — and not only the right equipment, but also the right corrective actions must be in place to prevent the catastrophic impact on yield these defects can produce. 1 I. B. Ferreira, “Effective Defect Monitoring in
Photo and Etch.” KLA Yield Management Seminar, March 13, 1996. 2 I. B. Peterson, “Defect Reduction Methodology in
the Lithography Module.” KLA-Tencor Yield Management Seminar, July 14, 1998. 3 Moshe E. Preil, Harry J. Levinson, “Yield-limiting
Issues in Deep-UV Lithography.” Microlithography World, Spring 1998.
About the Author Dr. Ingrid B. Peterson joined KLA-Tencor’s Yield Management Consulting Group in September 1995. Since then, she has developed and implemented yield management services in her area of expertise at many customer fabs. Dr. Peterson previously was a staff process engineer in photolithography at Synergy Semiconductor and also at VLSI Technology where she helped drive defect reduction for all areas of the fab. From 1987 to 1990, Dr. Peterson was a staff research scientist at the Max Planck Institute for Solid State Physics in Stuttgart, Germany. Dr. Peterson earned a Ph.D. in Solid State Physics from the University of California at Santa Barbara in 1987 and has published internationally in several areas of Solid State Physics.
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EVALUATE NEW EQUIPMENT EXTEND THE CAPABILITIES OF EXISTING TOOLS
Available for all stepper / scanner lithography tools and wavelengths Automated characterization of focus errors (system, lens, autoleveling, chuck flatness, etc.) Demonstrated 3 sigma precision of 11 nm Over 120 measurement points per field
Benchmark
TECHNOLOGIES
Premier lithographic test reticles and related services for all your needs
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phone: 781-246-3303
world wide web: www.benchmarktech.com
for automated evaluation of focus errors quickly and accurately
Phase Shift Focus Monitor Reticle
FROM KLA-TENCOR
FOR USE WITH PSF SOFTWARE
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Stepper Focus Metrology and Analysis Using a Phase Shift Mask by Patrick J. Lord, Senior Product Marketing Manager and Michelle Zimmerman, Product Marketing Manager
Since the introduction of phase shifting masks, engineers studying this imaging technique have been aware that errors in the phase of the mask (non-180 degree shifters) would cause asymmetries of the printed image as the image was defocused. These asymmetries would create a translational offset in the printed image as a function of the focus offset. The Phase Shift Focus Monitor reticle is a tool which uses this effect for stepper diagnostic and calibration.1 The basic concept of the focus monitor reticle is simple and elegant. A bar-in-bar overlay target is written on a reticle. Both the inner and outer bars are printed at the same time, with part of the target phase shifted by 90 degrees and the other part unshifted (figure 1). If the stepper is perfectly focused, the overlay error will be exactly zero in both x and y. If, on the other hand, there is a focus error, the phase shifted half of the overlay target will move relative to the unshifted part; and the result is interpreted as an overlay error which is a direct measure of the focus error. Even though the method requires a one-time calibration between the actual focus and the overlay misregistration (figure 2), the linearity of the behavior as presented in figure 3 is a strong advantage of the method. As opposed to alternative solutions that are quadratic in nature, the PSF method can easily detect small focus changes about the optimal operating point. With the introduction of new analysis software, such as KLA-Tencor’s KLASS PSF, semiconductor manufacturers have been quick to utilize the speed and power of this new technique. Unlike other focus techniques, which require qualitative estimates of image quality to determine the “best”
focus position, the PSF method provides an operatorindependent, quantitative measure of the best focus position. In addition, the high throughput of overlay measurement tools compared to CD measurement systems such as SEMs makes it possible to measure the best focus at many positions within a lens field in a very short amount of time.
Figure 1. Typical phase shift mask focus target (courtesy of Benchmark Technologies, Inc.).
Figure 2. Meander focus setup.
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Figure 3. Calibration linearity. Figure 5. Field cur vature after removal of field tilt.
This new capability has allowed stepper engineers to apply the same mathematical rigor to focus analysis which has long been available for studying overlay. Focus variations within the field and from field-tofield across a wafer can now be mathematically modeled to determine lens tilt (figure 4), field curvature (figure 5), astigmatism (figure 6), wafer and chuck flatness (figure 7), the impact of lens heating and barometric pressure (figure 8), and other focus anomalies.
Figure 4. Field tilt analysis.
The speed of the overlay measurement tools also allow the engineer to measure several wafers to average out wafer flatness effects that would otherwise distort the data. The quantitative power of this technique is a breakthrough step in the analysis of stepper focus. Used as a daily focus monitor, it becomes an invaluable phase for any advanced process control implementation targeting dose control for improved critical dimension performance. 1 The Phase Shift Focus Monitor reticle is exclusive-
ly available from Benchmark Technologies, Inc.
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Figure 6. Lens astigmatism.
Figure 7. Wafer and chuck flatness.
Figure 8. Lens heating effects.
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Identifying Process Drift with CD SEMs Getting more than critical dimensions from SEM linescans and images with correlation scoring by David M. Goodstein, Applications Engineer
In situations where CD-only-based monitoring of process integrity proves inadequate, the CD SEM continues to provide essential monitoring capability through the use of linescan and image correlation metrics. This additional information is extracted from the same line scans and images acquired in the course of standard automated CD measurement. Consequently, there is almost no impact on throughput. The high sensitivity of these metrics to even small degrees of process variability suggests they will play an important role in all demanding CD SEM-based process monitoring and control applications. CD SEMs play an essential role in photolithography and etch process characterization and monitoring. Post-develop (DI) and post-etch (FI) monitoring of device critical dimensions (CD) as well as fast, thorough characterization of processes and process equipment are routinely handled by advanced high-throughput CD SEMs. Realtime process monitoring is especially important to catch yield-compromising process variations as soon as possible, before a significant and costly fraction of in-process wafers are affected. While CD is the standard metric on which CD SEM monitoring is based, additional and potentially more sensitive metrics are available from the very same tool. To see why more sensitive monitoring metrics might be necessary even at large design rules, consider the CD variation of an i-line resist isolated line on metal as a function of stepper defocus and exposure (figure 1). With a nominal CD of approximately 540 nm (at 0 Âľm defocus, 190 mJ exposure), a DI monitor that flagged resist-line CD deviations greater than five percent would still allow significant process variation (figure 2). Process drift of this magnitude might well impact post-etch metal line CD and overall line integrity, compromising device performance and total yield. This can be avoided
with tighter process monitoring at the post-develop stage, using non-CD-based metrics. Limitations of CD-only monitoring
It should not be surprising that not all process drift can be identified by changes in critical dimension. Interconnects, gates, contacts and vias are fundamentally three-dimensional structures, and characterizing them solely in terms of CD (which is itself a function of the measurement algorithm applied to the CD SEM image or linescan) is necessarily a simplification. If a device feature simply scales uniformly with process drift, then CD is an adequate metric. However, this is often not the case. The limitations of CD-only characterization and monitoring are evident in figure 3, where isolated end-of-line structures are imaged by a CD SEM at 75kX magnification. Measurement linescans, acquired near the middle of the line, are also shown. The resist line printed at 1.2 Âľm defocus and 200 mJ exposure (bottom image) measures at 535 nm, a CD deviation of less than two percent from nominal (543 nm). Such a line would pass most CD-only monitors, where process windows are typically 10 percent of nominal. However, when compared to the line printed at optimal focus and exposure (top image), the non-optimal line clearly suffers from reduced sidewall steepness (wider, but lower intensity edges) and variable resist thickness (bright fringes across the line). These changes can lead to an appreciably Autumn 1998
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feature under inspection to the optimal one I am trying to manufacture?” For CD SEMs, the most accessible metric of feature fidelity is linescan or image correlation, calculated against a reference or optimal template. It utilizes the same linescans and images that are acquired during the course of auto-
correlation, and CD correlation (defined as one minus the absolute fractional CD deviation from optimal) are plotted for varying defocus at optimal focus (figure 5a) and varying exposure at optimal focus (figure 5b). In both cases, correlation scoring provides a more sensitive measure of process drift than CD.
Figure 1. Bosung plots of isolated line CD vs. focus (in µm) for i-line resist on metal 1.
different etch transfer function, which may unfavorably impact the resultant metal line and, therefore, the etch process yield. The key to catching these types of process variations is to monitor not only feature CD, but a metric that reflects overall feature fidelity as well; such a metric should answer the question: “How similar is the
Optimal Field (0.0 µm, 190 mJ) CD = 543 nm
Inspection Field (-1.2 µm, 200 mJ) CD = 535 nm
Correlation
Figure 3. A comparison of end-of-line images and measurement linescans from the isolated resist lines of figures 1 and 2. Focus and exposure conditions are indicated in parentheses.
mated measurement and has the added advantage that, unlike CD measurement, it is an algorithmindependent metric of a feature’s faithfulness to a standard.
Figure 2. Wafer map showing deviation of i-line resist on metal 1 isolated line CD from optimal CD as focus and exposure var y. The yellow field corresponds to optimal focus and exposure, with a CD of 543 nm. The green fields define the range of process conditions that yield resist-line critical dimensions within five percent of 543 nm.
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The one-dimensional correlation between the non-optimal and optimal measurement linescans (bottom right), and the twodimensional correlation between the non-optimal and optimal end-of-line images (bottom left), are displayed in figure 3. These low correlations (compared to those in figure 4) should raise a red flag that significant process drift has occurred, even though the CDs at this process step remain in spec. Further evidence of the potential power of correlation-based monitoring is shown in figures 5a and 5b, where image correlation, linescan
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The effect of establishing an 80 percent threshold (20 percent deviation) on linescan correlation for this layer is shown in figure 6. Correlation scoring clearly facilitates more precise monitoring of process drift than CD measurement alone. Fully automated correlation monitoring
The power of correlation-based monitoring would be of little benefit if it could not be implemented with the same level of automation and speed as CD-based monitoring. In fact, linescan and image correlation monitoring on the KLA-Tencor 8100XP can be integrated seamlessly into normal automated CD measurement, and provides: • Real-time calculation, reporting and output to measurement data
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linescan- and image-based characterization methods,1 will be a critical part of every successful CD SEM-based yield monitoring system.
Optimal Field (0.0 µm, 190 mJ) CD = 543 nm
Inspection Field (-0.3 µm, 190 mJ) CD = 558 nm
Correlation
Figure 4. A comparison of image and measurement linescans between optimal and near-optimal resist lines. Note the significantly higher linescan and image correlations as compared to those in figure 3.
files of linescan and image correlations against user-defined optimal templates. • Automatic acquisition of sub-optimal linescans and images, based on user-defined thresholds, for subsequent review. This is accomplished with nearzero impact on throughput in automation. Correlation monitoring is, by no means, limited to the example discussed here. Dense lines, contacts, other layers, and the smallest design
rules are all accommodated in the current implementation on the 8100XP. Depending on the application, acceptable correlation thresholds can be determined and subsequently enforced in conjunction with standard CD monitoring. When fully integrated into CD SEM-based, closed-loop advanced process control, correlation provides an even more powerful tool for maintaining lithographic process integrity and achieving maximum yield. As device geometries continue to shrink and process windows continue to narrow, correlation monitoring, as well as other
Figure 6. Wafer map showing linescan correlation score grouping as a function of focus and exposure dose. The yellow field corresponds to optimal focus and exposure. Taken together, all colored fields define the range of process conditions that yield at least 80 percent linescan correlation.
1 J.M. McIntosh, et. al., “Approach to CD SEM Metrology Utilizing the Full Waveform Signal,” SPIE Proc., 1998.
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Figure 5. a) Variation of isolated-line CD correlation (one minus absolute fractional deviation from nominal), image and linescan correlation at optimal exposure (190 mJ) as a function of defocus. b) Variation of isolated-line CD, image and linescan correlation at optimal focus (0.0 µm) as a function of exposure dose.
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The author wishes to thank Bhanwar Singh and Bryan Choo of Advanced Micro Devices for providing the initial impetus for this investigation, as well as providing the focus-exposure wafers used to generate these results.
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Analysis of ESD-Induced Reticle Defects by Jim Reynolds, Reynolds Consulting
In semiconductor manufacturing, the effects of static charge are particularly critical in the photolithography area. The photo process involves step-and-repeat operations using reticles. A damaged reticle can result in thousands of defective products. Due to the small dimensions and non-conductive substrates on the reticle, electrostatic discharge (ESD) can occur, causing significant yield losses. The present study was made as the result of just such an occurrence. The observed production yield loss was eventually traced to multiple ESD events, which caused pattern damage on the reticles. Some recommendations to the problem of reticle ESD damage are proposed. Introduction
Reticle deterioration over time has long been a concern of the wafer lithographer. Since the advent of the wafer stepper in the early 1980â&#x20AC;&#x2122;s, events such as pellicle breakage, crystal growth under the pellicle, and electrostatic discharge (ESD) have created a low incidence of extremely expensive problems. The consequences of an undesired change on the image surface of a reticle can cause problems ranging from downgraded products to 100 percent yield loss. Isolating these losses to a damaged reticle can be very difficult and time consuming. Many semiconductor lithographers prefer periodic reinspection of reticles to the disastrous possibility, however remote, of undetected reticle damage. In 1997, a large European semiconductor manufacturer observed the yield on an established product drop to zero percent over a short period of time. This article is a discussion of that event and of ways to minimize the potential damage that can be caused by ESD. Reticles and ESD
Static charge is most commonly generated by triboelectric charging. Whenever two dissimilar materials are in contact and separated, a charge exchange occurs between the two surfaces, resulting in two oppositely 16
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charged objects. Once an object becomes charged, it may transfer its charge directly to another object. Induction charging can also occur when an isolated conductive object is brought near another charged object, without actually touching it. At any time when two objects, with a potential difference large enough to break down the insolating path that separates them, come close together, current will flow causing an ESD event. As a practical matter with reticles, the sources of charge are ubiquitous and the gaps over which discharge can occur are small now and getting smaller. Charges can build up on garments, work surfaces, packaging materials and air streams, just to name a few possibilities. Fab environments are normally dry with relative humidity at 40 percent or below and rapidly moving air. The quartz substrates used on most photomasks have a very low surface conductivity, allowing puddles of charge to build up on different areas of the reticle. Voltage differences of 5-8,000V are not uncommon on the surface of a reticle. The chrome which defines the pattern can conduct a high voltage to a region on the mask where the electrostatic potentials are lower. If chrome, run at a high potential, comes into close proximity of another at a lower potential, the resulting high electric field gradient will cause ESD. When this happens, extremely high temperatures are generated which melt both chrome and, in some cases, quartz, causing an undesired modification of the pattern. This reticle damage can occur over time (with small ESD events) and in varying degrees of severity.
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Figures 1-3. Progressive examples of ESD damage on advanced reticles.
Case study
Production yield losses at a major semiconductor manufacturer prompted the current investigation. The cause was arduously traced back to one of the reticles used in the photolithography process. We inspected the two-die reticle using a KLA-Tencor STARlight system and examined both the individual defects and the pattern of defects. Several levels of damage were discovered on this reticle. Figure 1 shows slight damage of the antireflective layer which lies on top of the chrome. This precursor to ESD was visible on the STARlight, even though this section of the reticle would probably go undetected on a pattern defect inspection system and would print normally. This level of damage can exist on a reticle that does not have additional damage, providing a means of early identification of a reticle that is prone to more catastrophic ESD.
When the potential of the distant region approaches or exceeds the breakdown voltage, the ESD shown in figures 1-3 occurs. Living with ESD
As long as photomasks are made of conductive chrome on non-conductive quartz substrates, the potential for ESD exists. It is up to the reticle maker and user to minimize exposure to this problem and the damage it can cause. The most direct method is to add conductivity to the air surrounding the reticle. This can be done with electronic air ionizers in front of the HEPA filters supplying air to the workstations where reticles are handled or used. Increasing the relative humidity as far as possible (50-55 percent) provides additional protection. Even with these measures, the only way to prevent yield loss due to ESD on reticles is to reinspect the reticles periodically using a STARlight or similar system. circle RS#033
Figures 2 and 3 show regions of the same reticle with increasing levels of ESD. Both show evidence of rapid current flow, coupled with deformation of the chrome image. This current has produced melting of both the chrome and quartz substrate. In figure 2, a small tail emerges from each side of the gap with a transmission of around 72 percent, as measured on the STARlight. In figure 3, a bridge with 53 percent transmission is found. Both of these cases would have produced bridging when printed on a wafer. Figure 4 is an atomic force microscope (AFM) rendering of the defect in figure 3, clearly showing the physical topology of the region. All three of these cases met the classic ESD requirements. Long conductors came from a distant part of the plate, bearing the potential of a charged region. A small gap separates them from a relatively short conductor which bears the potential of the local region.
Figure 4. AFM rendering of the bridge defect shown in figure 3.
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We can’t promise you’ll like what you see on your reticles. ( But we can promise you’ll see it.) Now that the world is moving below 0.18 µm, things are really going to get ugly. To survive, you’ll need to see just what you’re up against. That’s the idea behind our new 353UV, the industry’s Yield-killing OPC. first and only reticle inspection system for deep UV lithography. Thanks to a series of engineering breakthroughs, its shorter wavelength lets you see photomask patterns with the high resolution needed for critical UV inspections. In fact, with unprecedented 0.15 µm sensitivity, the 353UV can discern the finest details on the most
©1998 KLA-Tencor, Inc.
complex photomasks, and uncover subtle anomalies that otherwise couldn’t be found. At the same time, it can detect whole new classes of defects that are just now impacting yield. Plus, by combining all this with advanced new algorithms, the 353UV makes it easy to capture even the most subtle defects on OPC and PSM reticles. Now you can have the tools to view deep UV reticles with a startling degree of clarity — even though you might not always like what you see. For more information, please visit www.kla-tencor.com/353uv.
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Industry Viewpoint Bridging the Gap to 300 mm Wafers By Dan Hutcheson President, VLSI Research, Inc.
Is the transition to 300 mm wafers dead? Have the high cost of 300 mm tools and the current industry downturn ended wafer-size transitions? No, but these factors have caused the industry to look for more cost-effective transition strategies. One of the most promising strategies is the development of bridge tools. The transition to 300 mm wafers has been identified as a key step in maintaining profitability in an era of shrinking geometries and increasing device complexity. Unfortunately, higher costs paired with the current downturn have prevented the industry from simultaneously transitioning to both 300 mm wafers and the 0.25, 0.18 or 0.15 µm device generations as previously expected. The next window of opportunity will occur around 20012004, coincident with the adoption of the 193 nm lithography tools needed to manufacture 0.13 and 0.10 µm devices. If the industry misses that window, I believe it will be the end of wafer-size transitions. The shift to 300 mm may be even more difficult to accomplish in 2001 than it would have been now, if it requires extensive construction of new fabs. Although I expect the industry to be in a strong upturn by that time, it will still be financially strapped as it attempts to both increase capacity for existing generation products and finance the transition to 0.13 geometries for advanced devices. It is, therefore, critical that we find a low cost, low risk means of
facilitating this transition; and I believe bridge tools are the solution. To deliver on that promise, bridge tools must meet three key criteria. They must have the ability to handle either 200 mm or 300 mm wafers with easy upgrades. For any given process, the 200 mm version of the bridge tool must deliver a combination of footprint and throughput that results in a smaller floor space requirement than that of the previous generation of 200 mm tools. Finally, the cost of ownership for a 200 mm bridge tool at a particular process step must be less than that of the current generation of 200 mm tools. If the industry begins the shift to bridge tools now, it should be able to surmount the key challenges I expect it to face in 2001. It will be able to respond quickly to increased demand for capacity by transitioning from 200 to 300 mm wafers without incurring massive construction costs. In addition, it will have production-proven 300 mm platforms that will help speed the ramp to full yield for new 0.13 µm advanced devices — a critical factor both in meeting demand and increasing profitability. G. Dan Hutcheson is president of VLSI Research, Inc., a company specializing in market research and economic analysis of the semiconductor manufacturing industry.
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Image Management: A New Approach for Yield Analysis by Bert Plambeck, Program Manager
As volumes of defect data are generated in the semiconductor manufacturing process, manufacturers look to sophisticated systems that can help extract meaningful information needed for rapid analysis and resolution of yield problems. Being able to quickly determine the root cause of a yield excursion or a process problem is the essence of yield engineering. While SPC or pareto charts help yield analysis, review of images generated by the inspection, metrology or failure analysis tools during the fabrication process can help expedite the process of determining of the root cause of a yield excursion. With the addition of the VARS image management system to its suite of yield enhancement solutions, KLA-Tencor enhances the capability of its inspection and metrology systems and increases the overall value of its solutions to customers. Image management is becoming an increasingly important part of the diagnostic process, providing critical information about the nature and source of yield-limiting process problems. Defect images are valuable in process analysis. For instance, a CD SEM edge profile image illuminates information derived from Bosung curves, and overlay images taken across the wafer can visually quantify CMP process uniformity. Collecting images one at a time on polaroids and storing them in binders in the lab were helpful to yield engineers in the past. However, as timeto-information becomes ever more critical to resolve yield problems quickly, going through binders of polaroids and unorganized data files to identify images associated with the defect under review has become a laborious and time-consuming exercise. Manual image storage methods do not facilitate easy information access, information sharing or transfer within or between fabs necessary for 20
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rapid resolution of yield problems. For images to be meaningful, it is important that they are captured from the inspection and metrology tools, saved along with the associated defect data and made available instantaneously to engineers or the yield management system. The VARS system
The VARS image management system stores and retrieves images generated from a wide variety of on-line and off-line equipment including defect review stations, scanning electron microscopes (SEM), metrology equipment and focused ion beam (FIB) systems. With a large online capacity expandable to hold millions of images, it links all the image gathering tools in the fab to a single database allowing economical storage and fast access and retrieval of images along with the relevant inspection data. User stations at each image-generating tool are utilized for image acquisition and transfer to VARSâ&#x20AC;&#x2122; central host for storage and distribution. Once stored, images can be reviewed one-at-a-time with a one-second retrieval time or as a gallery of images created using user-defined search criteria. Images can be easily imported into reports and printed in full color or black-and-white with printer options that allow the user to include image related data on the image printout.
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Imaging the future
Images will play an important role in fabs in the future. Multiple tools across the fab are generating greater and greater volumes of images — images, that when stored and managed efficiently, can provide solutions to current problems and opportunities for optimizing yield in the future. As inspection, metrology and yield enhancement systems become fully integrated, images will add a new dimension to yield management — when available in real time, images will support, clarify and expedite the analysis of yield limiting problems. VARS is the springboard for creating a complete image management system for the fab of the future — a system that will enable better process visualization, whether the process is in a fab across the hall or an operation half the world away.
Figure 1. VARS connectivity in a fab.
Whether within a single fab or between fabs located half a world apart, VARS enables and enhances communication. Web access can be added to the VARS host that allows users to access/download data and images stored on the host using an Internet browser. Within seconds of addition of images to the VARS database, they become available to any authorized person in the company via the Intranet or the Internet. Users can format the image browser screen to display images and the associated defect data. Access is controlled through password protection. A key advantage which an image management system provides is the transfer of yield and process examples from an established fab to a remote fab. A yield engineer can search a remote database for defects that are similar to those appearing in the local line. When a match is found, the cause and corrective action can be determined from engineering analysis done previously, saving time and effort.
Image Window displays images selected by user for record or playback. Control Panel allows users to record or playback in one second, perform multiple parameter searches, display selected images in gallery format, image tag list, view another station’s live video, enable automatic data interface from other vendor’s inspection tools.
Data Window shows user-definable data structure which allows users to save data associated with the defect image under review.
Figure 2. VARS user interface.
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Yield Enhancement with Bitmap Analysis by Ken Bernstein, Program Manager
Review of failing bit data collected by automated test equipment (ATE) is an essential tool used by engineers to improve the yield of memory arrays. While visual inspection of this data provides the engineer with the locations of failing bits, analysis of the failing bit patterns can help pinpoint the cause of bit failures.
With the introduction of KLA-Tencor’s BitPower™ Analysis System, bitmap analysis has transitioned from an offline engineering function into an ongoing manufacturing process for yield improvement. With this system, bitmap data is collected during production test, failing bit patterns are automatically extracted, and the data is passed to Klarity™, KLA-Tencor’s automated analytical software module, where it is analyzed in conjunction with the physical defect data collected at in-line inspection points. Such analysis helps correlate defects detected earlier in the manufacturing process to an electrical failure identified at the end of the process. This bitmap line monitor is illustrated in figure 1. When off-line engineering analysis is required, KLA-Tencor’s BitPower System provides powerful bitmap review software for full reproduction and visualization of failing bit data and their exact topological locations, thus preserving the ability to view original and absolute bit coordinates.
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Figure 1. (a) KLA-Tencor’s BitPower system collects data from ATE. (b) Bitmap data is converted from electrical to physical coordinates and bit patterns are extracted. (c) Physical bit pattern data is transmitted to Klarity. (d) Klarity can analyze the bitmap data in conjunction with other data sources.
Bitmap line monitor step 1: Data collection
As the first step in implementing the bitmap line monitor, the KLA-Tencor BitPower system collects raw electrical bitmap data from the ATE. Memory testers are the traditional source of bitmap data; but with the memory content rising in non-memory devices, it has become increasingly common for logic and mixed signal testers to have the ability to produce bitmap data. KLA-Tencor’s BitPower system can accept data from any of these sources.
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Bitmap line monitor step 2: Electrical-tophysical conversion
In order to understand the cause of an electrical failure of a die, it is important to pinpoint the exact location of the failure point on that die. Converting electrically failed bit data into meaningful, physically correct coordinates has traditionally been a time-consuming and errorprone process due to complex internal address scrambling of the memory arrays. The BitPower system provides revolutionary new utilities that allow the user to easily create die models that perform the map-
ping between electrical addressing and physical coordinates. Any die type can be modeled, including those with multiple on-board memory arrays such as DSPs and microprocessors. As the physical data is created, the original electrical data is not discarded. Instead, it is compressed and saved to allow off-line manual analysis of the bitmap data with BitPower’s Bitmap Review Software. Such analysis is often required to review optically invisible defects that have resulted in the electrical failure of a die. The soft-
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ware allows the user to view failures at the wafer level or the die level. The wafer-level bitmap viewer (figure 2b top image) is capable of displaying the bitmap data across the wafer. The die-level bitmap viewer (figure 2b lower image) provides the more traditional die and sub-die-level bitmap representation. Bitmap line monitor step 3: Bit-pattern extraction
After the bitmap data is converted into physically correct coordinates, it can be searched for patterns such
Figure 2. Conversion of physical defect data to topological location of a bit failure.
Figure 2a. Top: Physical wafer map from inspection sys-
Figure 2b. Top: BitPower’s wafer level bitmap viewer shows the location
tem. Bottom: Exploded view showing die level defects.
of the electrical failures. Bottom: BitPower’s die/sub-die level bitmap viewer lets the user precisely locate the positions of failing bits and to view failing patterns at the bit level.
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Failing bit patterns vary by product. Circuit design, circuit layout, and process technology all play a part in determining the likely patterns that occur in a memory array. The BitPower system allows the user to create custom pattern descriptions for each device type. The final step: Automated analysis
Once extracted, the failed bit patterns are transmitted to the Klarity automated yield analysis system for further analysis and correlation to defect data obtained from inspection points. Klarity accepts the bitmap data from the BitPower Analysis System as it would from other data sources within a fab. The bitmap data can be incorporated into Klarityâ&#x20AC;&#x2122;s unique Decision Flow Analysis recipes for automated monitoring and analysis (figure 3). For example, recipes can be generated according to userdefined criteria to automatically trend failed bit classifications, identify repeating failure patterns, identify bit
failure excursions and send notification of such excursions to interested parties in the fab automatically.
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The combination of BitPower data and in-line inspection Figure 3. Regular monitoring of failed bit patresults provides terns extracted with BitPower can identify outKlarity with of-control conditions. powerful information required to determine the relationship between in-line defectivity determined earlier in the process/line, and bit failure patterns extracted by BitPower from electrical tests at the end of the process. Based on correlation results, Klarityâ&#x20AC;&#x2122;s built-in use of conditionals and filters allows selected wafers from a lot to be sent for further SEM review or failure analysis. This helps faster identification of the process zones contributing to yield loss, improves failure analysis efficiency and accelerates resolution of the yield problem. Full die
as single-bit failures, word-line failures, bit-line failures, etc. Each of these patterns provide clues to the potential cause of the failure at specific process steps. For example, a paired bit failure may be indicative of a missing field oxide or a failing word-line could be indicative of missing contacts.
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Inspection Implications of a Design-Rule Shrink by Mark Keefer, Technical Marketing Manager
The current semiconductor business environment has caused most semiconductor manufacturers to postpone new fab construction or expansion of existing fabs. However, competitive pressures require improved, more cost-effective manufacturing processes. One way to achieve higher revenue is to produce more die per wafer. As the transition to 300 mm wafers is delayed, alternative approaches to increase the number of die per wafer are occurring: decreasing the design rule of the circuits (linewidth “shrinks”) and product redesign (compaction). Two benefits can be realized — the increased circuit density results in increased capacity (number of die per wafer start), and shrinks can also improve device performance, which allows higher average selling prices. Shrinks are cost-effective since they do not require an entirely new processing equipment set (except photolithography). As minimum feature sizes shrink, IC manufacturers face an increasing challenge to maintain and increase wafer yields and chip performance. New process technologies may have implications for the existing metrology and inspection equipment. Since smaller feature sizes are susceptible to electrical faults induced by smaller defects, defect inspectors must become more sensitive. Cost-effectiveness can be achieved in part by extending existing capabilities, rather than investing in a completely new equipment set. Defect inspection systems and strategies are changing to support shrinking design rules, and to accommodate new technologies or materials, as well as increased financial considerations. In-process wafers have more die per wafer and, therefore, higher value, requiring optimal defect inspection and sampling plans to decrease the amount of product at risk due to an undetected yield excursion. Processing and defect inspection trends of linewidth shrinks
The 0.5 to 0.35 µm process shift is characterized by adoption of oxide CMP processing and use of i-line lithography on critical layers. Global planarization by CMP is an enabling technology for the transition to 0.35 µm and below linewidths. The flatter wafer surface enables finer resolution of device features by reducing the stepper
depth of focus requirement. However, new yield-limiting defect types introduced by the oxide CMP process include residual slurry, microscratches, and surface voids. The 0.35 to 0.25 µm process shift is characterized by adoption of tungsten CMP steps, use of DUV lithography, new inter-layer dielectric (with low dielectric constant k) and interconnect materials, and shallow trench isolation replacing LOCOS for tighter packing density. Additional defect types introduced by the metal CMP process include residual tungsten (puddles or stringers), recessed or cored plugs, and metal dishing and oxide erosion. The use of anti-reflective layers results in other new defect types such as pinholes. Inspection trends include the initial use of patterned wafer tool monitoring (reduced use of unpatterned monitor wafers), and initial use of automatic defect classification (ADC) in production. The 0.25 to 0.18 µm process shift will probably incorporate an unprecedented number of material and processing changes. It will likely see some combination of Cu interconnects and low k dielectric materials in a dual damascene architecture that replaces metal etch Autumn 1998
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and oxide CMP with oxide patterning and metal CMP low energy implants for ultra-shallow junctions, and step-and-scan DUV lithography coupled with resolution enhancement techniques. The increased value of wafers in process may alter inspection strategies. More fabs will adopt patterned wafer tool monitoring and, also, introduce photolithography cell monitoring to provide high sensitivity inspection and rapid feedback.
illumination rather than monochromatic reduces the effects of color variation resulting from thickness variation. Not only does this result in increased defect capture rate with lower nuisance defect counts, but it also results in more robust wafer alignment. In some cases, the reduction in color variation results in sufficiently increased defect capture rate that a larger pixel size can be used for inspection, increasing system throughput and lowering cost of ownership1.
mented by integrated classification and analysis tools that quickly convert defect data into corrective actions. IMPACT/ Online™ ADC, in production use, aids in process characterization and rapid identification of process excursions. Defects are classified quickly and accurately, and the results are sent to defect data management systems such as Quest/ Klarity for defect clustering, layer analysis, defect type trending, and SEM review sample selection. ADC greatly surpasses the speed
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Inspection technology enhancements
Many of the new processes in use today, such as CMP, result in new defect types. Killer defects must be detected with high confidence, which requires a clear distinction between defect signals and “noise” induced by process variations, such as film thickness variation and grain structure. Brightfield imaging inspection systems compare grayscale intensity levels from cell-tocell or die-to-die and interpret differences as possible defects. Color variations that result from film thickness variation result in a change in gray-scale levels. This noise reduces the sensitivity of the inspection system by raising the minimum threshold level required to interpret a difference as a defect. Metal grain structures have the same effect: creation of additional noise, potentially resulting in nuisance defects. Laser scattering systems also rely on detecting differences between die-to-die comparisons. Process variations that are unaccounted for result in having to set the detection thresholds higher, reducing inspection sensitivity. Inspection system technology has been developed to reduce the effects of process noise on the inspection process. Two key improvements are ultra-broadband brightfield illumination and Segmented AutoThreshold (SAT). Using broadband 26
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Figure 1. The SAT algorithm segments the different images used in die-to-die processing based on the mean and range value of each pixel. In the above example, two segments are used.
SAT is an image processing technique for die-to-die (random mode) inspections that increases sensitivity on wafers with grainy metal and color variations typically seen in CMP processes. SAT algorithms partition the wafer image into multiple segments based on mean and range pixel values for each pixel (figure 1). Then, a different threshold value is applied to each segment, and the threshold value is dynamically adjusted during the inspection. Lower thresholds are applied to areas with lower noise, maximizing defect capture while reducing nuisance defect counts. In a metal etch inspection on grainy metal, the use of SAT to suppress nuisance defects resulted in several times higher defect capture as compared to non-SAT inspection2. High capture of all yield-relevant defect types alone is not enough. Defect detection must be comple-
Yield Management Solutions
and accuracy of manual classification, and defect trending by defect type reveals excursions missed when trending by total random defect count alone3. As linewidths shrink, smaller inspection pixels are used (since yield-limiting defects are smaller), and trending by defect type (rather than total defect count) reduces the number of lots at risk4. The ADC system uses brightfield image processing algorithms similar to the inspection equipment, so the defects can be re-detected in spite of image differences introduced by CMP color variations. Patterned wafer tool monitoring
Defect inspection can be broadly divided into three categories: process line monitoring, process equipment monitoring, and engineering analysis applications. Process line monitoring typically
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uses high-resolution brightfield imaging systems on product or short-loop patterned test wafers. Equipment or tool monitoring typically uses darkfield laser scattering inspection of unpatterned monitor wafers. An opportunity exists for cost reduction in the equipment monitoring area by inspecting product wafers. The National Technology Roadmap for Semiconductors (NTRS) calls for a reduction in test wafers from 33 to 28 percent for the 0.25 µm to 0.18 µm technology generation5. Benefits of patterned wafer equipment monitoring are a more accurate representation of the true process (shows process integration failures), cost savings by reduction of monitor wafers, and the ability to use the same inspections for device monitoring, which aids in defect source analysis and yield prediction6. Patterned wafer tool monitoring also reduces process excursion detection time, reducing the amount of product at risk — an important consideration for highvalue wafers. Tool monitoring can also improve process equipment overall equipment effectiveness (OEE), by optimizing the time between preventive maintenance.
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The majority of capital investment in a linewidth shrink is in photolithography. Benchmarking the defectivity of new lithography technology is essential for fast yield ramps. The critical defects scale with the design rule, requiring high sensitivity inspection. Defect evaluation for a new lithography process on product wafers is difficult due to pattern complexity, previous layer defects and process noise; and it becomes more difficult with each successive mask layer. Back-end layers with multi-level metallization and CMP thickness variations exacerbate the problem. Use of a shortloop photo cell monitor (PCM) wafer avoids these issues. Silicon wafers are fully processed through the photo cluster — coat/expose/ develop — using the same process conditions (resist and design rules), except that stepper focus and exposure settings are optimized for baresilicon wafers. Photo cell monitors can be inspected with high sensitivity, due to low process and substrate noise, allowing higher defect capture than is possible on after-develop inspection (ADI) production wafers. High-resolution brightfield
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inspection (small pixel size) is able to detect photo defects such as developer spots that are low topography and/or have subtle color variations. The advantage of a photo cell monitor, compared to individual photo tool monitors, is that inspection time is significantly reduced and fewer wafers are required. Sampling frequency can be determined statistically, based on the number of excursions detected. Application of this technique has recently been described7. Impact of product mix on inspection systems
With the decline in DRAM prices due to overcapacity, many semiconductor memory manufacturers are diversifying their product mix to include logic devices to achieve higher profitability. Given the costsensitive nature of DRAM manufacturing, inspection systems dedicated to inspection of memory arrays were developed that offer cell-to-cell (array mode) inspection only, with a reduced selection of pixel sizes. Logic products have large areas of the die that are not repetitive cells, requiring the use of die-to-die (random mode) inspections for complete die coverage. Logic product design has been driven by interconnect complexity, leading to multiple levels of metal and the use of CMP as the global planarization technique. Inspection of logic devices and/or devices processed using CMP benefits from die-to-die mode and suppression of process noise using techniques such as broadband illumination and SAT algorithms. Importance of fast yield ramping
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Controlling and reducing defect levels becomes more important as linewidths decrease, for both development and production. Delays in finding and solving defect problems during development can delay the
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product transfer to manufacturing. Figure 2 shows the importance of yield ramping as a competitive advantage. As the industry moves to the next linewidth generation, both the initial production yield and the yield ramping rate are critical, especially as DRAM profitability has fallen severely8. Yield modeling illuminates the significant dollar savings that can be achieved with a fast, successful yield ramp (figure 3). Key to rapid yield improvement is the rapid identification of yieldlimiting systematic and random defects, so that engineering resources can focus on fixing problems.
die per wafer, and to increase product performance. With each technology generation, it becomes more important to achieve high yields quickly and sustain yield in manufacturing to ensure profitability. Processing changes associated with linewidth shrinks may require inspection system enhancements such as broadband illumination, SAT, and ADC to extend the life of inspection solutions. The increased value of each in-process wafer may force rethinking inspection strategies, such as adopting patterned wafer tool monitors or implementing photo cell monitors. 1 Metteer, B. et al, “TI MSTC/DP1 Evaluation of
Summary
Semiconductor manufacturers are decreasing design rules to reduce fabrication costs by producing more
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the KLA-Tencor 2138”, proceedings of KLA-Tencor Yield Management Seminar, Austin, TX, 1997. 2 Garver, J., Keefauver, K., Tinker, M., Improved
Defect Detection Performance at Metal and Contact Etch Levels Using a New, Optical
Yield Management Solutions
Comparison, Segmented Auto-Threshold Technology, SPIE Vol. 3050, pp. 452-463, 1997. 3 Breaux, L., Kolar, D., “Automatic Defect
Classification for Effective Yield Management”, Solid State Technology, Vol. 39 No. 12, pp. 89-96, 1996. 4 Shanthikumar, G., “Sequential and Bypass ADC
Sampling Models”, KLA-Tencor SEMICON/ West ADC Workshop, San Francisco, CA, 1998. 5 The National Technology Roadmap for
Semiconductors, Semiconductor Industry Association, San Jose, CA, pp. 117, 1997. 6 Jackson, J. and Usry, W., “Inspection of Etch
Layers and Patterned Wafer Tool Monitoring With the AIT”, proceedings of KLA-Tencor Yield Management Solutions Seminar, San Francisco, CA, 1998. 7 Phan, K. et al, A Methodology for the
Optimization of an I-line Lithographic Process for Defect Reduction, SPIE Vol. 3332, pp. 309-320, 1998. 8 Peters, L., “Speeding the Transition to 0.18 µm”,
Semiconductor International, Vol. 21 No. 1, pp. 61-70, 1998.
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Automatic Defect Classification: A Productivity Improvement Tool by Tony Esposito, IBM Corporation; Mark Burns, Scott Morell, KLA-Tencor; Eric Wang, Stanford University
Why should a semiconductor fab invest the time to review and classify defects on a wafer after the wafer has been inspected? To add the additional step of classification in an already lengthy fabrication process is contradictory to manufacturing fundamentals unless it can be proven that the additional step can positively influence final yield. The extra information about the source of defects is an obvious benefit that defect review and classification provide. However, a method for quantifying the benefit of classification is required. Traditionally, classification is done manually by a human operator after the wafer is inspected. Manual review and classification of defects offers defect source information but carries with it several less-then-ideal side effects. From a manufacturing standpoint, the extra processing step increases the total time it takes for a lot to work through the process flow. Classification requires additional employees and review tools on which to do the review and classification. From an engineering standpoint, the information fed back by classification is only useful if it is accurate and consistent. In practice, a multitude of factors impact the accuracy of classification including operator experience, state of operator consciousness, consistencies from operator to operator, cost of operator labor, the cost of review stations, and the excessive queue time lots spend waiting for review after in-line inspection. The ideal solution is to place the task of classification with an automated system that reduces or eliminates the majority of these negative side effects.
cluster tool daily monitor wafers using 64 Mb pitch). For each level, a minimum of 10 lots were used to measure the performance of ADC against a pre-defined set of metrics. ADC performance
The overall ADC performance of the five process levels (figure 1) was measured and recorded. Each of the ADC classifiers performed at or above the expected levels for the beta evaluation. Process/Level Defect Standard Wafer ADI Excursion Monitor 4 Mb Metal 1 16 Mb Metal 1 64 Mb POLY
Accuracy
Purity
Redetection
97% 80% 72% 77% 80%
100% 89% 80% 87% 80%
100% 91%* 100% 99% 98%
Figure 1. Beta performance of IMPACT/Online ADC. *The lower-than-normal redetection for the ADI monitor is due to nuisance defects. Subsequent to follow-on beta testing, the inspection recipe was modified using Segmented Auto Threshold (SAT), which reduced the nuisance defects and improved rede-
Beta evaluation of IMPACT/Onlineâ&#x201E;˘
tection to greater than 95 percent.
In a scientific approach to this task online, IBM installed a beta version of IMPACT/Online ADC on a KLA-Tencor 2132 defect inspector at IBM Burlington in order to collect data and analyze costs. The system was trained to classify five different production levels as part of the beta tool evaluation. The levels included: Trench Isolation, two metal levels, POLY on 64 Mb DRAM, and After-Develop Inspection or ADI (single layer
Case study: ADI excursion monitor
At the time of this study, the production classification strategy for the ADI Excursion Monitor was in transition from manual review and classification, to online automated defect classification using IMPACT. Therefore, the data collected for this study includes classification data from both the operators and ADC.
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Data collection procedure
For the purposes of this study, data and images from ADI wafers were chosen randomly across a two-week time period. The accuracy and purity performance (figure 2) was calculated for the operators and ADC with the expert classifications as the basis for comparison. The ADC classifications are more in line with those of the expert than the classifications generated by the five operators. This difference is indicated by the 20+percent difference in accuracy and purity.
ADC
0.73
Operator
Purity Accuracy
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0.62
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impact of physical defects on die yield. The ADI defect types were consolidated into two groups (figure 4): a killer group which consists of defect types with a kill potential equal to 100 percent, and a non-killer group which consists of all defect types with a kill potential less than 100 percent. The highest kill potential in the non-killer group was 35 percent with an average of less than 10 percent. 80% 70%
Percent of Defects Classified
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0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%
0% Figure 2. Accuracy and purity numbers for ADC and manual classifications.
Operator
ADC
Figure 4. Killer and non-killer defect statistics for the ADI excursion
The pareto (figure 3) of defect classifications is ordered by expert classification and includes the classification data from all three sources: Expert, ADC and Manual. 50%
Percent of Defects Classified
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While the ADC classifications produce a similar split of non-killer versus killer defects, the operator classifications favor the non-killer defect types. The more inaccurate operator classifications result in a systematic under-estimation of the impact that the defects are having on electrical yield. This defeats the purpose of the in-line inspection in that elevated yield loss is not discovered until end-of-line electrical testing. By this time, the manufacturing line may be full of substandard yielding material.
OT
Time-to-results Figure 3. Pareto of ADI excursion monitor classifications.
The relative magnitude of the ADC classifications match those of the expert classifier while the operator calls differ greatly in the SX (small defects) and the SF (Foreign Material on the Surface) class categories. This difference was found to be consistent across the five operators involved in the study. Other sources of manual classification errors were systematic. A single operator consistently classified SF defects as RR (Residual Resist) which suggests a need for additional training.
The total time-to-results is defined as the time it takes to acquire data that an engineer can use to start appropriate defect reduction actions1. For manual or automatic defect classification, the total time includes: • the inspection time; • the queue time between inspection and the review station; • the time required to load and align the wafers on a review station; and
Correlation to yield
IBM’s PLY (Photo Limited Yield) methodology for line monitor uses defect kill potentials to monitor the
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• the time required to perform manual or automatic classification3.
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The average total time-to-classification (figure 5) favors the ADC system by a factor of 50. With IMPACT/ Online ADC, the classification immediately follows the inspection step which eliminates the queue time associated with the manual classification. Classification Image capture Set up Queuing
Operator 0
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0 0.01 0.0001 0.0136 0.0237
Figure 5. Average time-to-classification results of ADC versus the operators.
Quantifying the benefits of defect review
The most obvious benefit of defect review is that it supplies information about the types of defects on a semiconductor wafer. The defect type information assists the yield engineers in identifying the sources of those defects. However, to choose the optimal in-line inspection and review sampling strategy, a method is needed for quantifying the benefits of all available strategies. A cost-based inspection and review sampling model for mean-shift random defect excursions has been developed by the Competitive Semiconductor Manufacturing (CSM) Automated Inspection Focus Study Research Group6 and is the subject of reference3. This economic model may be applied in this case study to quantify and minimize the total defect excursion cost, which consists of the out-of-control cost, the incontrol cost, investigation cost, fixing cost and false alarm cost3, 4, 5. A simple view of the process control dynamics is used (figure 6) to describe the basic premise of the economic model2, 3, 4:
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The time-to-classification is a subset of the total time-to-results that ignores the inspection time.
ADC
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Out-of-Control Cost Investigation Cost
Fixing Cost
Figure 6. Diagram of cost-based sampling model.
• The in-control cost is the product of the cost of baseline yield loss and the duration of time a process is in-control. • The out-of-control cost is the product of the cost of yield loss during an excursion and the duration of time the process is out-of-control. The time a process is out-ofcontrol is the sum of the detection delay, the investigation time and the fixing time. Accurate and timely defect review information will reduce this cost by reducing the detection delay and the time spent investigating the source. • The cost of finding the root cause for an excursion is the investigation or source identification cost. Again, accurate and timely defect review information will reduce this cost by reducing the time spent investigating the source. • The cost of implementing changes to return the process to an in-control state is the fixing cost. • False alarm cost is the cost of reacting to an excursion when the process is actually in-control. The false alarm cost is usually a combination of investigation and fixing costs. The dominant cost in the total cost equation is typically the out-of control cost. The electrical die yield of wafers processed while out-of-control is typically less than the die yield of wafers processed while in-control. This loss of product means loss of revenue that the product would normally generate. To minimize this revenue loss, the amount of time a process runs in an out-of-control state must be minimized. Excursion cost drivers — sensitivity analysis of the economic model
Information from in-line inspection sampling is used to determine whether an excursion has occurred or not1.
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SPC Limit
ond two bars in the series compare manual defect classification and ADC as measured in the case study. Note the overwhelming contribution of the beta risk, which accounts for 90 percent of the total detection delay for all four scenarios.
Out-of-Control Distribution
In-Control Distribution
Figure 7. Model of defect distributions — graphical representation
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Comparing the benefits of various ADI excursion monitor strategies
The data collected for the ADI excursion monitor was used to model the economic benefits of defect review and classification. The total detection delays including the review and inspection times are displayed for various ADI excursion monitor scenarios in figure 8. The inspection portion of the ADC bars include the review time associated with automated defect classification on an average ADI wafer. The first two bars describe a theoretical scenario where the accuracy of classification for manual and automated defect classification is perfect at 100 percent. The sec-
Detection Delay (hours)
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60 50 40 30 20 10 0 100%
90%
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Accuracy % Figure 9. Beta risk driven detection delay versus classification accuracy.
As a key driver of beta risk and, therefore, detection delay (figure 9), the accuracy of defect classification greatly affects the cost of an excursion. Looking at the excursion cost in terms of revenue lost per hour (figure 10) determines which in-line monitor strategy is optimal for the ADI process. In the total cost equation (figure 6), source identification time and fixing time play a close second and third to the costs associated with beta risk-driven detection delay. Note that ADC, based on performance measured during the case study, is the most cost-effective classification strategy. By adopting ADC on the ADI excursion monitor, IBM can expect to save over $250 per hour in revenue versus the manual defect classification strategy. This equates to more than $42,000 per week of revenue saved by implementing ADC at one in-line monitor location. Revenue Loss ($/hours)
The uncertainty in making this determination is measured using two risk factors — alpha and beta — both of which are based on the overlap between the in-control and out-of-control defect distributions (figure 7). The beta risk is of primary concern since it determines the length of the detection delay (figure 6), which is the duration of time the process runs in an out-of-control state before it is detected by the in-line control system. The beta risk is represented by the percentage of the out-of-control distribution to the left of the statistical process control (SPC) limit. By increasing the frequency of in-line inspection, the accuracy of the defect classifications, and the size of the review sample, the defect distributions become more distinct and the overlap between the two is minimized. Minimal overlap translates into reduced beta risk driven detection delay which reduces the cost of an excursion.
Detection Delay (hours)
of beta risk.
500
Fixing Source ID Review Inspection Beta Risk
400 300 200 100
MDC (100% accuracy)
ADC (100% accuracy)
MDC (49% accuracy)
0
ADC (73% accuracy)
MDC (100% accuracy)
ADC (100% accuracy)
MDC (49% accuracy)
ADC (73% accuracy)
Figure 8. Total detection delay for various ADI excursion monitor
Figure 10. Revenue loss rate for various ADI excursion monitor strate-
strategies.
gies.
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Conclusions
Using the excursion cost model enabled IBM to quantify the benefits of classification. The exercise revealed that classification, in general, is a vital part of a cost-efficient, in-line monitor strategy. In addition, classification metrics, such as the accuracy and review time associated with classification, determine the cost of an excursion. The key advantages in classification accuracy and time-to-results substantiate the need for on-line ADC as a replacement for manual defect classification on the ADI in-line defect monitor. The revenue losses associated with excursions are reduced by an estimated $42,000 per week by implementing IMPACT/Online ADC at the ADI in-line monitor location. The success at this process monitor, along with that of the entire beta evaluation, has motivated IBM to pursue the implementation of more production monitors using IMPACT/ Online ADC. Future IBM interests include SEMbased ADC and ADC on laser-scattering defect inspection tools. The optical limitations of identifying defects < 0.35 um in size combined with the constant reduction in critical dimensions that come with new process technologies favor an SEM-based ADC solution.
1 Louis Breaux and Dave Kolar, “Automatic Defect
Classification for Effective Yield Management”, Solid State Technology, December 1996, pp. 89 96. 2 Nurani, R. K., R. Akella, A.J. Strojwas,
R.Wallace, M.G. McIntyre, J.Shield, I.Emami, “Development of an Optimal Sampling Strategy for Wafer Inspection”, International Symposium on Semiconductor Manufacturing Proceedings, Tokyo, Japan, June 1994. 3 Wang, E.H., “An Integrated Framework for
Yield Learning in Semiconductor Manufacturing”, Stanford University Ph.D. Dissertation, May 1997, Chapter 3.
4 Wang, E.H. and D. Fletcher, “Optimal Wafer
Inspection Strategy with Learning Effects”, ASMC, October 1996.
6 The Competitive Semiconductor Manufacturing
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5 Nurani, R.K., R. Akella and A. J. Strojwas, “In-
line Defect Sampling Methodology in Yield Management: An Integrated Framework”, IEEE Transcript On Semiconductor Mfg. 1996.
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(CSM) Automated Inspection Focus Study
4 out of 5 Perfectionists Insist On VLSI’s Thin Film Metrology Standards.
NOW: ny”
n New “Ski s for d Standar 5nm 4.5 & 7. ss! Thickne If you’re responsible for thin film thickness measurements, you want them to be right. And you definitely don’t want to be embarrassed by a metrology tool that decides to drift at a critical time. That’s why perfectionists insist on VLSI’s suite of thin-film metrology standards. For silicon dioxide and silicon nitride. The broadest selection in the industry.
And now, oxide standards are available for 4.5nm and 7.5nm! It’s a VLSI exclusive. So if you’re a metrology perfectionist, flaunt it! Call now for your free “Good Enough ISN’T” button along with your free VLSI catalog... VLSI Standards: (800) 228-8574. Or on the Internet: www.vlsistd.com
The Measurement Standards for the Industry.
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Yield Management Seminar Series
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Since 1994, KLA-Tencor seminar series has provided customers with a valuable venue in which to share innovative ideas on how our products help solve manufacturing challenges. The new Yield Management Solutions Seminars, YMS2, will focus on value-added, integrated solutions for yield management, and process control. Key topics to be covered include CMP, Lithography, In-Line Monitoring and Yield Strategies. This section of the magazine will highlight a paper from a recent seminar and preview the upcoming session. We encourage you to attend and participate in our new seminar series. Your comments and feedback are welcome at any time.
YIELD
Call for papers
MANAGEMENT SOLUTIONS
YMS2 is always interested in proven application ideas, solutions to technical problems, new methodologies, and advanced techniques. The papers should focus on using KLA-Tencor tools and solutions to enhance yield through increased productivity and performance. The presentation does not have to be a formal published paper, just a synopsis of your testing and the results. Topics of interest
Defect Inspection, Lithography, CMP, Film Measurement, and Yield Management Strategies. If you are interested, please contact Janet Ely via email at janet.ely@kla-tencor.com.
SEMINAR â&#x2013;
For additional information contact Janet Ely via e-mail at janet.ely@kla-tencor.com
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YMS2 at a Glance October 21
Austin, Hyatt Regency (during SEMICON Southwest)
December 3
Makuhari, Japan, New Otani Hotel (during SEMICON Japan)
February 23
Seoul, Korea, Inter-Continental Hotel (during SEMICON Korea)
March 17
Santa Clara, Westin Hotel (during SPIE)
April 14 July 13
Munich, Germany (during SEMICON Europa) San Francisco, ANA Hotel (during SEMICON West)
Yield Management Solutions
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Inspection of Advanced OPC Reticles During the July 1998 YMS2, DuPont Photomask (DPI) presented its evaluation of OPC techniques and the inspection capabilities of KLA-Tencor’s new 353UV reticle inspection system. In the results, DPI emphasized the importance of OPC technology and the 353UV’s superior ability to inspect these features
Simply defined, optical proximity correction (OPC) techniques consist of incorporating features in the production of photomasks that neutralize optical distortion when a semiconductor design pattern is transferred to silicon. The value and use of OPC technology is growing because of the ongoing progression to increasingly smaller semiconductor design features. Semiconductor manufacturers are recognizing that OPC technology can extend the life of lithography steppers by extracting the maximum resolution performance possible from their equipment.
OPC addresses many issues OPC features range in complexity from simple edge jogs and line size adjustments to more complex, isolated mixed-tone features that are embedded in both the clear and chrome areas of the photomask. Serifs and hammerheads — squares and rectangles — are the most common OPC features on the photomask and are added to the end of a design line to prevent corner rounding and line-end shortening. Another technique involves adding assist features that change the way design features behave during the lithogra-
Figure 1. An oversized OPC feature can result in bridging on the wafer pattern.
phy process. For example, some OPC software packages automatically add scatter bars to isolated design features, causing those structures to print in the same manner as more dense design areas to produce a uniform result during the semiconductor manufacturing process. The features are too small to print during the lithography process, but preserve design integrity by increasing the resolution achieved by the stepper.
Monitoring the effects of OPC OPC features generated on a photomask are usually between 20 and 50 percent of the size of design features, requiring advanced production equipment to complete the manufacturing process successfully. Just as
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properly implemented OPC features improve the pattern accuracy, improper OPCs can create pattern complications. For instance, a missing or under-sized serif can cause significant drawback, while oversized serifs can result in bridging on the wafer (figure 1). Inspection technology is being pushed to new levels of functionality by the use of OPC. Although these features are sub-resolution, they still must be inspected and verified. As part of a strategic alliance, DPI and KLA-Tencor are working closely together to test advanced photomask inspection technology and new software algorithms that enable pattern recognition of advanced OPC fea-
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Figure 2. The 353UV significantly improves defect sensitivity over previous inspection systems.
tures, as well as identify OPC defects. Recently, DPI evaluated and characterized KLA-Tencor’s new Ultraviolet UV inspection system, the 353UV. During the evaluation, DPI engineers used both standard test plates and specially designed OPC reticles to characterize the new 0.18 nm pixel inspection, AOP algorithm, and defect highlighting tools.
System evaluation The 353UV demonstrated improved defect sensitivity on OPC features as a result of: 1) shorter wavelength, 2)
smaller pixel size, and 3) improved detection algorithms. Defects among serifs, hammerheads and assist lines were detected in isolated and dense geometries. Additionally, the 353UV system also showed improved sensitivity on UV-opaque defects and better resolution on DUV EA phase shift masks (figure 2). DPI engineers also realized that improved review tools are required to accurately classify the smaller defects. New review features such as edge sharpening and pixel displacement helped to classify 50 nm localized gate CD errors and process defects.
Inspection issues are closely linked to a photomask producer’s ability to generate features with sufficient clarity. The better a feature image is resolved on a photomask, the easier it becomes to do pattern inspections, saving valuable cycle time. The interdependent nature of production and inspection technology ensures that the development process will be ongoing, with advancements in production capabilities necessitating new developments in inspection technology.
KLA-Tencor Fall-Winter ’98 Trade Show Calendar
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October 19-21
ITC – International Test Conference, Washington, DC, USA
November 4-6
SEMICON Taiwan, Taipei, Taiwan
November 16-17
VDE/VDI Conference, Munich, Germany
December 1-3
Fall MRS, Boston, MA, USA
December 2-4
SEMICON Japan, Makuhari, Japan
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Monitoring of Low Dielectric Constant Parylene Films using Spectroscopic Ellipsometry by Carlos L. Ygartua, Process Module Manager; Duncan W. Mills, Staff Software Engineer; Clive Hayzelden, Senior Technical Marketing Manager
Parylene-F is one of the most promising materials for use as an intermetal dielectric at the 0.18 µm technology node. Due to its anisotropic refractive index, however, parylene-F cannot be examined using conventional spectroscopic ellipsometric techniques. In this article, the results of developing sophisticated data collection and analysis algorithms to determine the differences between in-plane and out-of-plane refractive indices are presented. The development of new intermetal low dielectric constant materials is a critical requirement for reducing parasitic capacitance and cross-talk in the increasingly finescale fabrication of semiconductor devices. Parylene-F (AF-4) offers a low dielectric constant (<2.3), high thermal stability (>450oC) and ease of deposition1. Ideally, measurement techniques for parylene AF-4 should be rapid, non-invasive, and similar to methods already in use for dielectric film monitoring. Spectroscopic ellipsometry (SE) has already achieved considerable acceptance as a monitoring tool. To achieve widespread acceptance of AF-4 in high volume manufacturing, however, it will be necessary to have methods and equipment for production monitoring of film thickness, uniformity, and refractive index. In this article, a method is presented for simultaneously measuring thickness, in-plane, and out-of-plane refractive indices of parylene. The UV-12X0SE and ASET-F5 film thickness measurement tools use two technologies: broadband (visible plus ultra-violet) Dual Beam Spectrometry (DBS), and Spectroscopic Ellipsometry (SE). KLA-Tencor measurement tools characterize films by providing reflectivity spectra and calculating the values of film parameters — the thicknesses, t, refractive indices, n, and extinction coefficients, k — from the best fit between theoretical and measured spectra. The DBS tool subsystem obtains the measured spectrum, Rm(λ), that represents the reflected light intensity as a function of the wavelength, λ. In the case of SE, the
reflected light is elliptically polarized. It can be represented by two components: a p-component, Rp, with polarization parallel to the plane of the incident and reflected beams, and an s-component, Rs, with polarization perpendicular to that plane (figure 1). Rp and Rs are complex quantities, defined by their intensities, |Rp| and |Rs|, respectively, and their phase difference, ∆. TanΨ and cos∆ are the standard ellipsometry parameters that describe the polarization state of the reflected light. They are defined by: Rp Rp = .exp (i∆) = tan Ψ.exp(i∆) Rs Rs TanΨ is the ratio of the p- and s-component intensities, and cos∆ is the real part of the complex quantity exp(i∆). To properly analyze the uniaxial birefringent nature of these films, KLA-Tencor has developed and implemented an algorithm designed to model the effects of the ordinary and extraordinary refractive next
p
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nord Figure 1. Showing the s and p polarization states of the reflected light together with the ordinar y (in-plane) and extraordinar y (out-of-plane) refractive indices of the par ylene.
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xylylene polymerizes instantly on the wafer giving parylene AF-4 films. The vapor phase polymerization method at Novellus provides parylene AF-4 films with excellent uniformity and conformity on 200 mm wafers. The deposited parylene AF-4 films are semi-crystalline and the polymer chains are composed of -[C6H4-CF2-CF2]- structure. We have measured both as-deposited samples and samples that have received a 400ºC anneal in a nitrogen atmosphere.
Model – DBS
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Ellipsometric analysis of several parylene films, including PPX-N, PPX-C, and PPX-D has indicated that they are uniaxial, with an extraordinary refractive index normal to the film surface, leaving two degenerate ordinary refractive indices lying in the plane of the film2. The nature of the birefringence differs between the types of parylenes; as an example, PPX-D is positive uniaxial (nextraordinary > nordinary), whereas most parylenes are negative
700
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0.5 0.0 -0.5 300
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Figure 2. SE and reflectivity spectra for as-deposited AF-4. Thickness = 1075 nm.
N vs nm
indices (RI) upon the amplitude and phase of the reflected signal. Fortunately, uniaxial films of the parylene type contain no in-plane anisotropy, so they cause no mixing of the two independent p and s polarization states. Consequently, the “traditional” tanΨ and cos∆ parameters defined for isotropic films also apply to the present analysis. Film deposition
In a typical parylene AF-4 deposition process, the AF-4 dimer, octafluoro-[2,2]-paracyclophane, is sublimed in a vaporizer and the sublimed gaseous dimer is passed through a pyrolyzer maintained at 600ºC - 700ºC. The generated monomer, a,a,a’,a’-tetrafluoro-p-
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0.10 0.08 0.06 0.04 0.02 0.00
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Table 1 shows a summary of measurement results for the as-deposited and annealed samples. The in-plane (nordinary) and outof-plane (nextraordinary) refractive indices of the as-deposited material were determined to be 1.5137 and 1.4135, respectively. Following annealing, the in-plane (nordinary) and out-of-plane (nextraordinary) refractive indices of the material were determined to be 1.5879 and 1.4170, respectively.
0.5 0.0 -0.5 300
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with an offset of ~0.1. The unified SE plus DBS measurement results for this sample match prism coupler index measurements at 633 nm (nordinary = 1.53 and nextraordinary = 1.42) and profilometer measurements (thickness ∼ 1030 nm). Figure 4 shows SE and reflectivity spectra for an annealed AF-4 sample with a thickness of 915 nm. The dispersion curves are shown in figure 5.
0.6 0.5 0.4 0.3 0.2 0.1 300
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Figure 4. SE and reflectivity spectra for annealed AF-4. Thickness = 915 nm.
uniaxial. Our analysis has indicated that AF-4, both as-deposited and after-annealing, is negative uniaxial, with fairly pronounced birefringence compared to other parylenes. Results
Figure 2 shows SE and DBS spectra for as-deposited parylene AF-4 on silicon, the reflectivity rapidly drops to less than 10 percent at a wavelength of 272 nm and the SE spectra oscillations are damped out in the 260-275 nm range. The variation of n and k with wavelength are shown in figure 3. A strong absorption peak at 272 nm is seen in agreement with the observed minimum in reflectivity. In the 300-750 nm range, where k=0, nordinary and nextraordinary are essentially parallel,
N vs nm 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3
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Wavelength (nm) Figure 5. Dispersions of the real (n) and imaginar y (k) parts of the refractive index for ordinar y and extraordinar y modes for the annealed sample. n ord (633 nm) = 1.5879 and n ext (633 nm) = 1.4170.
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As deposited Ordinary Extraordinary Delta 1075 n/a n/a 1.5137 1.4135 0.1002 0.0349 0.0509 -0.0160 0.0157 0.0696 -0.0539
Summary
KLA-Tencor found that the refractive index (RI) dispersion for the two optical axes and the film thickness can be determined from coupling spectroscopic ellipsometry (SE) and normal incidence reflectance spectroscopy (DBS). The negative uniaxial optical anisotropy (nordinary - nextraordinary) is shown to increase from 0.1002 to 0.1709 following annealing at 400ยบC. The measurement technique is suitable
Ordinary 915 1.5879 0.0370 0.0488
Annealed Extraordinary n/a 1.4170 0.0505 0.0671
Table 1. Summar y of
Delta n/a 0.1709 -0.0135 -0.0183
for routine measurement of film thickness and refractive indices of parylene-F films deposited during integrated circuit processing. Acknowledgments
We gratefully acknowledge our collaboration with James Stimmell and Devendra Kumar of Novellus Systems, Inc., San Jose, CA. We would also like to acknowledge the contributions of the Specialty
measurement results.
Coatings Systems Division of Alpha Metals, Inc. for providing the high quality cyclic dimer AF-4 starting material used in this study. 1 M.A. Plano, D. Kumar and T.J. Cleary, The
Effect of Deposition Conditions on the Properties of Vapor-Deposited AF-4 Films. Mat. Res. Soc. Proc. Vol 476, 1997. 2 J.G. Gaynor and S. B. Desu, Optical Properties
of Polymeric Thin Films Grown by Chemical Vapor Deposition, J. Mater. Res., vol. 11, No. 1, Jan. 1996.
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New Off-Tool Software Products for Increased Film Measurement Productivity THIN FILM SOFTWARE 2.x WORKSTATION
RECIPE GENERATOR
Off-tool data analysis and recipe management
Automatic waferless recipe creation using basic stepper and reticle database information
GEM/SECS software development and training tool
Recipe generation on a local tool or workstation database
OLSA 1.x Off-line spectral analysis software for recipe development, measurement simulation, and analysis
For more information, circle RS#032 located on the business reply card or call (408) 875-7996.
LAPLINKโ ข FOR NT Remote control for diagnostics and troubleshooting
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Tungsten Plug Measurement for CMP Development and Production by Anna Mathai, Technical Marketing Engineer; Paul Sullivan, Software Manager; and Jason Schneir, Product Marketing Manager
Chemical Mechanical Planarization (CMP) processes are widely used in the semiconductor industry to enable multilevel device processing and smaller device features. Process variations in CMP can lead to many failure modes. For example, most metal polishing processes lead to recessed metal features because of the differential polishing at the dielectric/liner/metal interface. In addition, changes in the process, such as the pH level of the slurry, polishing speed or conditioning of the pads will change the plug recess. Plug recess needs to be carefully monitored since if it is too large, it will degrade the electrical connections between the vias and metal interconnects. This can lead to increased electrical resistance and limit the performance of the integrated circuit. CMP process sectors have commonly used profilers to measure the post-CMP planarization of the wafer. As the feature size of ultra large-scale integration technology decreases, this introduces stringent requirements on the spatial resolution of the CMP metrology tools. KLA-Tencor’s High-Resolution Profiler (HRP) is designed to monitor metal CMP processes in the fab, as is demonstrated here on measurements of tungsten plugs. Measuring plug recess
In a production environment, it is critical for the plug recess measurements to be made automatically on an entire cassette of wafers without operator intervention. The HRP loads each wafer automatically with a pre-assigned orientation and uses optical pattern recognition to locate an isolated plug to within a 10 x 10 µm area. Since CMP provides low optical contrast, edge enhanced pattern recognition models are used. Next, the feature-find algorithm scans the stylus in the x-direction with a preassigned scan length (see schematic in figure 1). If no plug is found that meets preset depth and width criteria, the stylus steps over a pre-assigned distance in the
y-direction and takes another x-scan (scans 1-3). In this way, the stylus quickly locates the plug and then takes a scan in the y-direction (scan 4) to determine the center of the plug. Then, a high-resolution image is acquired, positioning the isolated plug to within 0.5 µm of the center of the scan (shown by dotted lines). Figure 2 shows an HRP high-resolution image of an isolated tungsten plug. Scan 1
Next, the data is analyzed by the Scan 2 HRP advanced cusScan 3 tomizable measurement software, Answer!™ (see figFinal highure 3). Answer! resolution scan centered seamlessly integrates Scan 4 on feature sophisticated macros written in a highlevel programming Figure 1. The HRP feature-find algorithm. language with the HRP software. This architecture enables KLA-Tencor to quickly develop custom macros for specific process measurement needs. The Answer! plug recess algorithm thresholds the data to automatically find the plug and separate it from the background. Then, the algorithm extracts a representative line profile through the plug. Finally, it segments the data vertically, based on user-selectable parameters, in order to compute the plug recess and width.
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excellent long-term repeatability and to be insensitive to the stylus shape.
Figure 4 summarizes ten dynamic measurements on a single isolated tungsten plug, with the wafer unloaded and re-loaded between measurements. We found the plug recess measurement to have excellent repeatability of 0.9 nm (1σ).
Figure 2. HRP high-resolution image of 0.25 µm geometr y isolated tungsten plug.
In process development, the HRP has proven to be an invaluable characterization tool for CMP applications, including post-CMP Shallow Trench Isolation (STI), tungsten and copper CMP, and inter-level dielectric CMP. The HRP is used by both semiconductor manufacturers and CMP equipment manufacturers routinely to qualify and monitor the performance of CMP polishers.
The measurement was repeated after 12 hours and again after 48 hours, using the same stylus. The measurement was also repeated using two other styli. Overall, we found the plug recess measurement to have
198 Angstroms
Figure 3. The HRP Answer! plug recess macro
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automatically measures tungsten plug recess and width.
The First Production-Ready 300 mm Resistivity Measurement System The new OMNIMAP® RS-100 delivers the features customers have been asking for. • Accurate edge measurement to 1 mm from the conductive film • Powerful and easy to use Windows NT® platform • Full GEM/SECS HSMS compatibility and more • Expanded sensitivity for highly conductive interconnects such as copper and thick aluminum • Automated probe conditioner • 3D uniformity maps • 200 mm and 300 mm configurations • Meets SEMI safety and ergonomic requirements
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Q&A
Answers to your questions from KLA-Tencor’s Yield Management Consulting Group (YMC).
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I already have yield engineering experts on staff in my fab; what value can a Yield Management Consulting team bring me?
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The KLA-Tencor Yield Management Consulting group adds value to your yield improvement efforts in two ways. First, we maintain a unique bank of proprietary information captured from benchmarking more than 100 of the world’s top semiconductor manufacturers. This information bank includes a highly confidential database of yield learning rates and maximum achievable yields, as well as “best practices” identified throughout the semiconductor industry. Using this database, Yield Management Consulting can help determine your fab’s yield potential and which “best practices” can help you quickly achieve your yield goals. Second, when time-critical situations occur in your fab, our team of seasoned yield management professionals can supplement the skill sets of your fab yield engineers to jointly address your yield problems.
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What expertise do your yield management consultants offer?
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Our Fab Yield Benchmark Study and Statistical Probe Yield Analysis use Yield Management Consulting’s specialized consulting software and our proprietary databases. However, customers obtain the greatest benefit and value when KLA-Tencor inspection tools, analysis software, and yield management consulting expertise are integrated to provide a complete solution to yield-limiting issues.
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Are your services effective in new fab start ups, as well as existing fabs?
Our Yield Management Consulting team is comprised of specialists with an exceptionally broad-based set of yield management skills. They represent over 400 collective years of wafer fab yield engineering experience and state-ofthe-art knowledge in interconnect and equipment technology. What kinds of results have been seen from YMC work?
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Accelerated yield learning rates can translate into millions of dollars in additional revenue. Results vary by customer situation; however, many customers have stated that they have realized tens of millions of dollars in savings or revenue as a direct result of yield improvements achieved with Yield Management Consulting assistance.
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Would Yield Management Consulting services benefit me even if I do not have KLA-Tencor equipment or software in my fab?
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Yes, Yield Management Consulting offers a set of services that are not KLA-Tencor tool dependent.
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These services are very important to the ROI for a new fab since the longer it takes to ramp a new fab, the more revenue is lost. Because today’s typical new fab investment is $1.5 billion, it is critical to maximize the ROI by quickly ramping to entitled yields. Yield Management Consulting uses their suite of proven yield management methodologies and services to help you achieve industry-leading fab yield ramp rates to assure maximum yield and ROI in the minimum amount of time. For more information, contact your local YMC group 408.875.2696 circle RS#026
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Bringing the Future into Focus Interviews with Industry Leaders A video shown at KLA-Tencorâ&#x20AC;&#x2122;s exhibit during SEMICON West 1998 featured interviews with industry leaders Mark MelliarSmith, President and CEO of SEMATECH, Dale Harbison, Vice President of the Semiconductor Group at Texas Instruments, and Sung W. Lee, President of Samsung Austin Semiconductor, on the challenges and issues the industry faces today. Below are excerpts from this video:
Mark Melliar-Smith, President and CEO of SEMATECH
KLA-Tencor: What do you see as the most critical challenges the industry will face in the next few years?
Sung W. Lee, President of Samsung Austin Semiconductor
Harbison: Today, feature sizes are shrinking and demands on speed and density of the circuits are increasing. Post-optical lithography is a big challenge, because EUV, Scalpel and other X-ray techniques are very expensive; at the same time, we've got copper, we've got low-k, we've got all these things that are costing the industry large amounts of money.
Dale Harbison, Vice President of the Semiconductor Group at Texas Instruments
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Melliar-Smith: I think managing complexity is probably the biggest challenge this industry faces over the next decade. . . . Very often it will be harder to design a 100 million gate integrated circuit than it will be to make it. And very often, in a factory, the process control technology is more difficult than the process itself.
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Lee: Nowadays, prices are decreasing so fast we have to introduce our new products as quickly as possible. Ramp-up speed is the most critical thing for us. KLA-Tencor: What about the impact of fast yield ramps on profitability? How is that driven by today’s economic environment? Melliar-Smith: Fast yield ramps are crucial for a couple of reasons. The first tends to be very close to home. It's when you've built a $2-billion fab and your shareholders want a return on it. The only way to get a return on such a large investment is to ramp it very quickly. But equally important, your customers need a fast yield ramp as well. Typically they're looking for the highest technology and they want it quickly, to help their products come to market. Lee: We‘ve already invested $1.5-billion here in this fab, so if we delay the product, interest and depreciation will cost us almost $10-million a month. How to build our fab fast, how to quickly ramp our production, and how to enhance our yield are the most important things. Speed means everything in this business. KLA-Tencor: What does “yield management” really mean? Why is it so important? Melliar-Smith: The most important thing to understand about yield management is no surprises. It's not just a matter of data, it's a matter of reality. It's a matter of turning the data into what actually is going
on, inside the process or inside your fab. What we really need to do in yield management is to look at the future, and where the process is at any point in time, to try to prevent the defects in the first place. Lee: We have to heavily rely on the automated inspection equipment and the automated data collection systems to make our decisions more correct. Harbison: Predicting results is very important, and that's what we want the yield management tools to do. . . . That's why it's so critical for us to have more automated and more advanced yield management tools, so that they can gather that raw data, massage it, digest it, and give it back to the fab people in a form that they can very quickly take action on and very quickly generate results. KLA-Tencor: So what role will the industry play in the future? Melliar-Smith: I think you're always ultimately limited by the human imagination in almost anything that you do. We've been able to facilitate whole new markets, like cellular telephony, the Internet, the PC — all of those technologies essentially have been made possible, and certainly cost effective, by integrated circuits. If you are interested in seeing this video in its entirety, please circle reader service #29 on the BRC.
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Product News 362 Reticle Inspection System
An extension of the 300 Series platform, the 362 Automated Reticle Inspection System now compares optical proximity correction (OPC) technology enhanced geometries on the photomask to a matching database. The 362 is optimized for increased sensitivity on production OPC photomasks through the new AOP algorithm and improved database modeling, ensuring a closer match between the optical and database images. In addition, data preparation and rendering speed improvements can reduce both cycle and inspection times of advanced databases. The 362 also features defect review enhancements resulting in improved defect classification of subtle mask pattern errors. Previous 300 Series systems can be field upgraded to the 362. circle RS#017
AMRAY 4000 Series Defect Review SEM Systems
KLA-Tencor AMRAY Division’s 4000 Series Defect Review SEM systems offer the latest in SEM-based defect review and automatic defect classification capability for 0.18 µm process technologies and beyond. The 4000 series — offered in both 200 mm and 300 mm configurations — works in unison with KLA-Tencor’s Intelligent Line Monitor (ILM) System, automatically filtering optically inspected and classified data, performing one-touch ADC, and updating Quest™/Klarity™/VARS with both images and data. By using information available from inspection and optical high-resolution defect capture (HRDC), only critical defects are reviewed on the SEM. Moreover, automated defect localization (ADL) provides hands-off automation for rapidly collecting high-magnification SEM images, improving SEM utilization and operator productivity. All AMRAY 4000 series SEMs are fully compatible with IMPACT/Offline™ SEM ADC for hands-off automatic classification of SEM circle RS#031 defects.
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Windows NT® for Thin Film Measurement Tools
KLA-Tencor is the first to offer thin film measurement software which uses the Windows NT true multi-tasking and multi-thread operating system, resulting in increased throughput and the lowest cost of ownership of any advanced thin film measurement system available. In addition to the film measurement system software, KLA-Tencor offers off-line software products that increase overall system productivity. These off-line products include: off-line spectral analysis for recipe development and simulation, laplink for remote control and diagnostics, and recipe generator for fast waferless recipe creation. The combination of the new software, operating system and off-line software products meets the advanced productivity requirements of thin film process control. circle RS#032
HRP-220 High-Resolution Profiler
The HRP-220 offers in-line surface measurement capabilities for meeting 0.18 µm requirements and challenging applications such as metal and inlaid metal CMP, and shallow trench isolation (STI), post-CMP. The HRP-220 can measure total wafer flatness with better than 1 nm vertical resolution. This unique capability builds on the HRP-200 platform which offers both the long-scan capability, production-proven repeatability and ease-of-use of a stylus profiler, and the fine-area, high-resolution analysis and imaging capabilities of an atomic force microscope (AFM). The HRP-220 provides increased productivity and extended ease-of-use through its new customizable analysis software, Answer!, which automates monitoring of critical parameters. In addition, the HRP-220 capitalizes on the robustness and multi-tasking power of Windows NT® architecture. circle RS#028
KLASS Phase Shift Focus Monitor
The KLASS Phase Shift Focus (PSF) Monitor™ software is an analysis package designed to be used as part of a focus determination technique that takes advantage of the correlation between image translation of a phase shifted overlay target and stepper focus. Using a patented Phase Shift Focus Monitor test reticle available exclusively from Benchmark Technologies Incorporated, users can quantify and consequently automate stepper focus determination in the fab. This software can be seamlessly integrated with the KLA-Tencor 5000 series overlay measurement tools. circle RS#027
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Some might think it means to move slowly. But in the world of silicon, we see it as a license to speed.
On the tortuous road of yield management, we’re writing a new set of rules. One that moves well beyond die-per-wafer to define yield as a significant way to speed time-to-market. Optimize silicon performance. Enhance productivity. And ultimately, have a profound impact on both profitability and competitive advantage. Admittedly, it’s a broader perspective than other companies take. And a critical one for the fabs of today and tomorrow. But it’s just what you’d expect from our singular focus on yield enhancement, backed by over two decades of industry experience. To put our integrated yield management technology to work for your company, please call 1-408-875-4200, or visit www.kla-tencor.com. You’ll see that we’ve got a better roadmap. And a faster way to get you there.
© 1998 KLA-Tencor, Inc.