CMOS Digital Integrated Circuits Analysis
Kang
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Exercise Problems
5.1 Design a resistive-load inverter with R = 2 kΩ, such that VOL = 0.05 V. The enhancement-type nMOS driver transistor has the following parameters:
VDD = 1.1 V
VT0 = 0.52 V
γ = 0 V1/2
λ = 0
µnCox = 216 µA/V2
(a) Determine the required aspect ratio, W/L.
(b) Determine VIL and VIH.
(c) Determine noise margins NML and NMH.
SOLUTION :
(a)When Vout = VOL, Vin = VDD = 1.2V, the driver transistor operates in linear region. Using Eq.(5.12)
Since VOL is small, VOL/EcLn can be ignored. Using (5.17)
' 2 0 1 2() 22 1 DDOLn RinToutout out Cn VVk W IVVVV KL V EL ==−− +
6 21.10.05216102(1.10.52)0.050.05 22 W KL −=−− Solve for W/L,
(b)When Vin = VIL, driver transistor operates in saturation region.
Since Vin is slightly higher than VT0, Vin-VTO can be ignored. Also vsat= EC/2. Using Eq.(5.21)
When Vin = VIH, driver transistor operates in linear region. Using Eq.(5.27) repeated here :
87.6 W L =
2 0 0 () () DDoutinT satox LinTC VVVV WvC RVVEL = −+
2 0 () 2 DDoutn inT L VVk VV R −
derivative with respect to Vin and set 1 inIL out in VV dV dV = =− ( ) ' 0 11 inIL out ILT in VV dV W kVV RdVLR = −=−= Thus, 0 6 ' 11 0.520.546 20002161087.6 ILT L VVV W Rk L =+=+=
Taking
2 0 2() 2 DDoutn inToutout L VVk VVVV R −−
to Vin and set 1 inIL out in VV dV dV = =− , ( ) ' 0 1 222 2 inILinILinIL outoutout inToutout Lininin VVVVVV dVdVdV kW VVVV RdVLdVdV === −=−+− ( )( ) ' 0 1 12 IHTout L W kVVV RL =−−+
Differentiating both sides with respect
5.2 Layout of resistive-load inverter:
(a)Draw the layout of the resistive-load inverter designed in Problem 5.1 using a polysilicon resistor with sheet resistivity of 150 Ω/square and the minimum feature size of 400nm. It should be noted that L stands for the effective channel length which is related to the mask channel length as L = LM + d - 2 LD. where we assume d (process error) = 0 and LD = 15nm. To save chip area, use minimum sizes for W and L. Also, the circuit area can be reduced by using the folded layout (snake pattern) of the resistor.
(b)Perform circuit extraction to obtain SPICE input list from the layout.
(c) Run SPICE simulation of the circuit to obtain the DC voltage transfer characteristic (VTC) curve. Plot the VTC and check whether the calculated values in Problem 5.1 match the SPICE simulation results.
SOLUTION :
(a)The layout is shown in following.
0 ' 1 2 IHTout L VVV W Rk L =+−
2 00 ' 1 22 2 DDoutn ToutToutout L L VVk VVVVV W R Rk L +−−− ' 2 3 inIH DD out VV L V V W Rk L = = 0 '' 21 2 3 DD IHT LL V VV RkRkWW LL =+− 66 21.11 0.5220.772 320002161087.620002161087.6 V =+−= (c)NML = VIL – VOL = 0.546 – 0.05 = 0.496V NMH = VOH – VIH = 1.1 – 0.772 = 0.328V
Plug in back to Eq. (5.27) repeated above to solve for Vout
With the simulation result, we get 0.44
VV = and 0.79
VV = . From the problem 5.1, we calculated 0.55 IL VV = and 0.77 IH VV = . Therefore both calculation and simulation results are similar.
5.3 Refer to the CMOS fabrication process described in Chapter 2. Draw cross-sections of the following device along the lines A - A' and B - B'.
SOLUTION :
0 0 0 2 0 4 0 6 0 8 1 0 1 2 0 0 0 2 0 4 0 6 0 8 1 0 O u t p u t V o l t a g e ( V ) Input Voltage (V) VIL V H
(c) The VTC curve is shown in following.
IL
IH
The cross section is not drawn to scale. For A – A’ ,
5.4 Consider the following nMOS inverter circuit which consists of two enhancement-type nMOS transistors, with the parameters: VT0 = 0.48 V µnCox = 102 µA/V2
(W/L)load = 3 (W/L)driver = 9 γ = 0 V1/2
F| = 1.011 V λ = 0 VDD = 1.2 V EcLn = 0.45V
(a) Calculate VOH and VOL values.
(b) Interpret the results in terms of noise margins and static (DC) power dissipation.
(c) Calculate the steady-state current which is drawn from the DC power supply when the input is a logic "1", i.e., when Vin = VOH.
SOLUTION :
Gate oxide Halo Substrate(p-Si) N+ LDD N+ LDD STI STI CVD oxide Metal CVD oxide Metal silicide silicide silicide Poly-Si s p a c e r o f f s e t s p a c e r o f f s e t s p a c e r s p a c e r CVD oxide
Substrate(p-Si) N+ CVD oxide STI STI Poly-Si Oxide
The Cross section for B – B’ :
|2Ф
(a)The value of VOH must be found first to calculated VOL.
V
: load transistor in saturation,
Therefore, VOH = 0.72V
V
: load transistor in saturation, driver transistor in linear region, input
(b) VIL : load and driver transistors in saturation
= . Thus plug these relationships back into (1)
: load transistors in saturation and driver transistors in triode.
OH
( )2 0 0 2 load DDOHT k VVV−−= 0 0.72 OHDDT VVV=−=
OL
VOH ( ) ( ) ( ) 2 2 00 2 22 loaddriver DDOLTOHTOLOL kk VVVVVVV −−=−− ( ) ( ) ( ) 2 2 1.20.48320.720.48OLOLOL VVV −−=−− 2 42.880.51840 OLOLVV−+= VOL = 0.36V
is
( ) ( ) 22 0022 loaddriver DDoutTinT kk VVVVV −−=− ( ) ( ) 22 1.20.4830.48 outin VV −−=− (1)
derivative with respect to Vin on both sides
1 IL out in V dV dV =− ( ) ( )20.7260.48 IL out outIL in V dV VV dV −=−
Take
and use
inILVV
( ) ( ) 22 0.7230.7230.48 ILin VV −+=− 2 65.761.38240 ILILVV−+= 0.48 IL VV =
IH
( ) ( ) ( ) 2 2 00 2 22 loaddriver DDoutTDDToutout kk VVVVVVV −−=−− ( ) ( ) ( ) 2 2 1.20.48320.48outinoutout VVVV −−=−− (2)
in on
30.72outILVV=− when
V
Take derivative with respect to V
both sides and use
30.72outILVV=− when inILVV = . Thus plug these relationships back into (1)
Using 5.51, we can calculate static (DC) power dissipation
Assuming that the input voltage level is low during 50% of the operation time and high during the other 50%, the overall average DC power consumption is,
(c)You can check the steady-state current from the problem (b) 5.5
1 IL out in V dV dV =− ( ) ( ) 20.723(20.482) IHIHIH outoutout outinout ininin VVV dVdVdV VVV dVdVdV −=−−
0.480.360.12 LILOL NMVVV =−=−=
( ) ( ) 2 0, , 1 2 2 1 n DCinDDOHTnOLOL OL Cnn k IVVVVVV V EL ==−− + ( ) 6 2 102101 920.720.480.360.3611 0.36 2 1 0.45 A =−−= +
( ) 2 0, , 1 2 22 1 n DD DCOHTnOLOL OL Cnn k V PVVVV V EL =−− + = 6.6µW
µnCox = 102 µA/V2 µpCox = 51.6 µA/V2 VT0,p = -0.46 V VT0, n = 0 48 V γ = 0 V1/2 |2ФF|,n = 1.011 V |2ФF|,p = 0.972 V EC,nLn = 0.45V EC,pLp = 1.8V VDD = 1.2 V
Design of a pseudo-nMOS inverter:
(a)Determine the (W/L) ratios of both transistors such that:
(i) The static (DC) power dissipation for Vin = VOH is 1 µW, and
(ii) VOL = 0.1 V.
(b)Calculate VIL and VIH values, and determine the noise margins.
(c)Plot the VTC of the inverter circuit.
νsat,p = 70000
SOLUTION : (a) (i) ( ) ( ) 2 0, 0,, 2 DDTp DD DCpsatox DDTpCpp VV V PWvC VVEL = −+ ( ) ( ) 2 2 1.20.46 1.2 0.001700001.9510 21.20.461.8 p W = −+ Wp =5.66µm, Lp = 40nm 142 p W L = ( ) 2 0, , 1 2 22 1 n DD DCOHTnOLOL OL Cnn k V PVVVV V EL =−− + Let’s assume that VOL is 0.1V, ( ) 4 2 1.21.02101 0.00121.20.480.10.1 0.1 22 1 0.45 n W L =−−→ + 298 n W L = (ii) ( ) ( ) ( ) 2 2 0, 0,0,, 0,, DDTp p OLOHTnOHTnCpp n DDTpCpp VV k VVVVVEL k VVEL =−−−− −+
(i)
input low voltage VIL can be calculated using (5.42) and (5.44),
expression can be rearranged as 4.161.54
Note that VIL must be larger than the threshold voltage VT0 of the driver transistor, hence, VIL = 0.601 V is the physically correct solution. The output voltage level at this point can also be found as
( ) ( ) ( ) 2 2 1.20.46 0.11.20.481.20.481.8 1.20.461.8 p n k k =−−−− −+ ' ' 0.191 p pp n n n W k k L W k k L == , 0.378 p n W L W L = 0.378 pn WW LL = 10,0.378103.78 np WW LL === (b)
The
( ) ( ) 0,0, 0.480.240.46 p ILTnoutTp n out k VVVV k V =+− =+−
outILVV=− Using (5.42), ( ) ( ) ( ) ( ) 2 2 0, ,0, , 2 2 inTn p nsatnoxDDTpDDoutDDout Cnn VV k WvCVVVVVV EL −−−− ( ) ( ) ( ) ( ) 2 2 2 3 7.25100.48 3.651021.20.461.24.161.541.24.161.54 in ILIL V VV =−−+−−+ The
two possible
for VIL. 0.601 0.359 IL V V V =
This
solution of this second-order equation yields
values
To calculate V
This expression is rearranged as:
Next, substitute Vout in the KCL equation (5.42), to obtain
The solution of this simple quadratic equation yields two values for VIH
where VIH = 0.952 V is the physically correct solution. The output voltage level at this point is calculated as
In conclusion, the noise margins for high signal levels and for low signal levels can be found as follows:
The input low voltage VIL can be calculated using (5.42) and (5.44),
4.160.6011.540.965 out VV =−=
0, 2 IHTnout VVV =+
IH,
0, 0.50.50.50.24outIHTnIH VVVV=−=−
( ) ( ) ( ) ( ) ( ) ( ) 2 0, 2 0,, 0,, , 2 23 1 2 2 1 1 1.521020.480.50.240.50.241.6710 0.50.24 1 0.45 DDTp n inTnoutoutpsatpox DDTpcpp out cnn IHIHIH IH VV k VVVVWvC VVEL V EL VVV V −−= −+ + −−−−= +
0.952 0.17 IH V V V =
0.50.9520.240.236
V =−=
out
1.20.9520.248 0.6010.10.501 HOHIH LILOL NMVVV NMVVV =−=−= =−=−=
(ii)
This expression can be rearranged as
The solution of this second-order equation yields two possible values for
Note that VIL must be larger than the threshold voltage VT0 of the driver transistor, hence, VIL = 0.582 V is the physically correct solution. The output voltage level at this point can also be found as
This expression is rearranged as:
Next, substitute Vout in the KCL equation (5.45), to obtain
( ) ( ) 0,0, 0.480.1910.46 p ILTnoutTp n out k VVVV k V =+− =+−
5.232.05outILVV=− Using (5.42), ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 2 2 0, ,0, , 2 3 2 5 2 2 2.43100.48 9.761021.20.461.25.232.051.25.232.05 inTn p nsatnoxDDTpDDoutDDout Cnn in ILIL VV k WvCVVVVVV EL V VV −−−− − =−−+−−+
IL 0.582 0.378 IL V V V =
V
5.230.5822.050.994 out VV =−= To
VIH, 0, 2 IHTnout VVV =+
calculate
0, 0.50.50.50.24outIHTnIH VVVV=−=−
The solution of this simple quadratic equation yields two values for VIH
where VIH = 0.706 V is the physically correct solution. The output voltage level at this point is calculated as
In conclusion, the noise margins for high signal levels and for low signal levels can be found as follows:
( ) ( ) ( ) ( ) ( ) ( ) 2 0, 2 0,, 0,, , 2 45 1 2 2 1 1 5.11020.480.50.240.50.241.5610 0.50.24 1 0.45 DDTp n inTnoutoutpsatpox DDTpcpp out cnn IHIHIH IH VV k VVVVWvC VVEL V EL VVV V −−= −+ + −−−−= +
0.706 0.299 IH V V V =
0.57060.240.113 outV =−=
1.20.7060.494 0.5820.10.482 HOHIH LILOL NMVVV NMVVV =−=−= =−=−= (c) <i> 0 0 0 2 0 4 0 6 0 8 1 0 1 2 0 0 0 2 0 4 0 6 0 8 1 0 1 2 O u t p u t v o l t a g e ( V ) Input voltage (V) <ii>
5.6 Consider a CMOS inverter with the following parameters:
Calculate the noise margins and the switching threshold (Vth) of this circuit. The power supply voltage is VDD = 1.2 V.
SOLUTION :
First, the output low voltage VOL and the output high voltage VOH are found, using (5.56) and (5.57), as VOL = 0 and VOH = 1.2 V. To calculate VIL in terms of the output voltage, we use
Since, with low input voltage, VIL, we can assume that Vin-VT0,n << EC,nLn, VDD-Vout/E
p << 1. Thus, we obtain,
0 0 0 2 0 4 0 6 0 8 1 0 1 2 0 0 0 2 0 4 0 6 0 8 1 0 1 2 O u t p u t v o l t a g e ( V ) Input voltage (V)
nMOS VT0,n = 0.48 V µnCox = 102µA/V2 (W/L)n = 10 pMOS VT0,p = - 0.46 V µpCox = 51.6µA/V2 (W/L)p = 19
(5.61) ( ) ( ) ( ) ( ) ( ) 2 0, 0,, 2 0, , 1 2 2 1 inTn nsatox inTnCnn p DDinTpDDoutDDout DDout Cpp VV WvC VVEL k VVVVVVV VV EL −+ =−−−−− +
C,pL
( ) ( ) ( ) ( ) 2 0, 2 0, 2 2 2 n inTn p DDinTpoutDDoutDD k VV k VVVVVVV − −−−−−
To calculate the VIL , we differentiate both sides of above equation with respect to Vin.
Substituting Vin = VIL and (dVout/dVin)=-1, we can get this expression.
Now substitute this expression into the KCL equation.
This expression yields a second-order polynomial in Vout, as follows:
Only one root of this quadratic equation corresponds to a physically correct solution for Vout (i.e., Vout > 0).
From this value, we can calculate the critical voltage VIL as:
To calculate VIH in terms of the output voltage, use (5.71):
Next, substitute this expression into the KCL equation (5.68) to obtain a second-order polynomial in Vout
0,0, 2 1 20.461.21.040.48 0.980.569 11.04 outTpDDRTn IL R out out VVVkV V k V V +−+ = + −−+ ==− +
( ) ( ) ( ) ( ) 4 2 4 2 10.210 0.980.5690.48 2 9.810 21.20.980.5690.461.21.2 2 out outoutout V VVV −− −+−−−−
2 3.9243.155.670 outoutVV−−=
1.168 out VV =
0.980.5690.576ILout VVV =−=
( ) ( ) 0,0, 2 1 1.20.461.0420.48 1.020.61 11.04 DDTpRoutTn IH R out out VVkVV V k V V +++ = + −++ ==+ +
( ) ( )2 2 2 1.0421.020.610.481.21.020.610.46 4.1653.61.760 outoutoutout outout VVVV VV +−−=−−− +−=
Again, only one root of this quadratic equation corresponds to the physically correct solution for Vout at this operating point, i.e., when Vin = V
.
From this value, we can calculate the critical voltage V
as:
Finally, we find the noise margins for low voltage levels and for high voltage levels using (5.3) and (5.4).
5.7 Design of a CMOS inverter circuit:
Use the same device parameters as in Problem 5.6. The power supply voltage is VDD = 1.2 V. The channel length of both transistors is Ln = Lp = 60 nm.
(a)Determine the (Wn/Wp) ratio so that the switching (inversion) threshold voltage of the circuit is Vth = 0.5 V.
IH
0.033 out VV =
1.020.0330.610.64 IH VV =+=
IH
0.576 0.56 LILOL HOHIH NMVVV NMVVV =−= =−= Switching Threshold voltage is, ( ) ( ) ( ) 0,0, 0.480.3451.20.46 0.576 10.345 1 TnDDTp th VVV VV +− +− === + +
nMOS VT0,n = 0.48 V, µnCox = 102µA/V2 , EC,nLn = 0.4V pMOS VT0,p = - 0.46 V, µpCox = 51.6µA/V2 , EC,pLp = 1.8V SOLUTION : ( ) ( ) ( ) ( ) 0,, ,, 0,, 0.50.480.4 19mV 0.50.480.4 thTnCnn DSsatn thTnCnn VVEL V VVEL − === −+ −+ ( ) ( ) ( ) ( ) 0,, ,, 0,, 1.20.50.461.8 212mV 1.20.50.461.8 DDthTpCpp SDsatp DDthTpCpp VVVEL V VVVEL −− −− === −−+ −−+
(b) The CMOS fabrication process used to manufacture this inverter allows a variation of the VT0,n value by ±15% around its nominal value, and a variation of the VT0,p value by ±20% around its nominal value. Assuming that all other parameters (such as μn, μp, Cox, Wn, Wp) always retain their nominal values, find the upper and lower limits of the switching threshold voltage (Vth) of this circuit.
SOLUTION :
0,,, , 0,,,, 1.20.460.2120.51.8 126 0.50.480.0190.4 DDTpSDsatpth Cp n R pthTnDSsatnCn VVVV E k k kVVVE == == (/) 102 126,/64 (/)51.6 nnoxnn Rnp ppoxpp kCWLW kWW kCWLW ===== < Verification by Simulation >
nMOS VT0,n = 0.48 V, µnCox = 102µA/V2 , (W/L)n = 10 pMOS VT0,p = - 0.46 V, µpCox = 51.6µA/V2 , (W/L)p = 19
5.8 Consider the CMOS inverter designed in Problem 5.7, with the following circuit configuration:
(a)Calculate the output voltage level Vout
0,0, 0,0, 0.552V (15%),0.552V(20%),1.04 11()0.552(1.20.552)1.040.600V 1111 1.04 TnTpR TnDDTp R th R VVk VVV k V k ==−= ++ +− === + + 0,0, 0,0, 0.408V(-15%),0.552V(20%),1.04 11()0.408(1.20.552)1.040.527V(Lowerlimit) 1111 1.04 TnTpR TnDDTp R th R VVk VVV k V k ==−= ++ +− === + + 0,0, 0,0, 0.552V(15%),0.368V(-20%),1.04 11()0.552(1.20.368)1.040.691V(UpperLimit) 1111 1.04 TnTpR TnDDTp R th R VVk VVV k V k ==−= ++ +− === + + 0,0, 0,0, 0.408V(-15%),0.368V(-20%),1.04 11()0.408(1.20.368)1.040.618V 1111 1.04 TnTpR TnDDTp R th R VVk VVV k V k ==−= ++ +− === + +
1.2 V M3 (0.15 / 0.06) Vout
SOLUTION :
Note that the nMOS transistor M3 operates in linear region, and that its drain current must be zero. Consequently, the drain-to-source voltage drop across M3 is also zero. Thus, the CMOS inverter operates at inversion threshold(by definition), and its output voltage is equal to Vth
< Verification by Simulation >
(b)Determine if the process-related variation of VT0,n of M3 has any influence upon the output voltage Vout
SOLUTION :
There is no current of M3. So the process-related variation of VT0,n of M3 cannot have any influence upon the output voltage Vout.
(c)Calculate the total current being drawn from the power supply source, and determine its variation due to process-related threshold-voltage variations.
5.9 Consider a
inverter, with the following device parameters:
SOLUTION : nMOS VT0,n = 0.48 V, µnCox = 102µA/V2 , EC,nLn = 0.4V, vsat,n = 124340 m/s Cox,n = 22mF/m2 pMOS VT0,p = - 0.46 V, µpCox = 51.6µA/V2 , EC,pLp = 1.8V, vsat,p = 70000 m/s Cox,p = 19.5mF/m2 Also: VDD = 1.2 V λ= 0.1 V-1 < Short Channel Solution > ( ) ( ) ( ) ( ) ( ) ( ) 2 ,, ,,,, ,,, 2 6 1 0.50.48 0.12101243400.02210.10.5 0.50.480.4 0.344μA GSnTn DnnsatnoxnDSn GSnTncnn VV IWvCV VVEL =+ −+ =+ −+ = ( ) ( ) ( ) ( ) 2 ,,,,,,,,,, 2 0,,,,,,, 121 () 32.04uA/V-32.04nA/mV oxnDSnsatnGSnTnnoxnDSnsatnGSnTnn TnGSnTnTcnnGSnTncnn CVvVVWCVvVVW I VVVELVVEL +−+− =− −+−+ =−= < Long Channel Solution > ( ) 2 ,,,0,, 62 1 (/)()1 2 1 102102(0.50.48)(10.10.5)42.84nA 2 DnnoxnnGSnTnDSn ICWLVVV =−+ =−+= ( ) ,0, 0, 6 (/)()1 1021010(0.50.48)(10.10.5)21.42uA/V-21.42nA/mV noxnGSnTnDS Tn I CWLVVV V =−−+ =−−+=−=
CMOS
(a)Determine the (W/L) ratios of the nMOS and the pMOS transistor such that the switching threshold is
(b)Plot the VTC of the CMOS inverter using SPICE.
SOLUTION :
nMOS VT0,n = 0.53 V, μnCox = 98.2 μA/V2, EC,nLn = 0.4V pMOS VT0,p = -0.51 V, μpCox = 46.0 μA/V2, EC,pLp = 1.8V
DD = 1.2 V λ= 0
Also: V
Vth = 0.6 V. SOLUTION : ( ) ( ) ( ) ( ) 0,, ,, 0,, 0.60.530.4 60mV 0.60.530.4 thTnCnn DSsatn thTnCnn VVEL V VVEL − === −+ −+ ( ) ( ) ( ) ( ) 0,, ,, 0,, 1.20.60.511.8 86mV 1.20.60.511.8 DDthTpCpp SDsatp DDthTpCpp VVVEL V VVVEL −− −− === −−+ −−+ 0,,, , 0,,,, 0.5 0.5 0.51.20.510.0861.8 1.8 0.51.20.530.060.4 (/) 98.2 1.8,/ (/)46.0 DDTpSDsatp Cp n pDDTnDSsatnCn ideal nnoxnn Rn ppoxpp VVV E k kVVVE kCWLW kW kCWLW = −− == −− ==== 0.843 p W =
(d)Discuss how the noise margins are influenced by non-zero λ value. Note that
transistors with very short channel lengths (manufactured with submicron design rules) tend to have larger λ values than long-channel transistors.
0 0 0 2 0 4 0 6 0 8 1 0 1 2 0 0 0 2 0 4 0 6 0 8 1 0 1 2 Input Voltage (V) O u t p u t V o l t a g e ( V )
Determine the VTC of the inverter for λ = 0.05 V -1 and λ = 0.1 V-1 . SOLUTION : 0 590 0 595 0 600 0 605 0 610 0 0 0 2 0 4 0 6 0 8 1 0 1 2 O u t p u t V o l t a g e ( V ) Input Voltage (V) λ = 0 V-1 λ = 0.05 V -1 λ = 0 1 V-1
(c)
SOLUTION :
A sharp VTC transition and larger noise margins can be obtained with smaller λ values. Thus, CMOS inverters built with long-channel transistors can be expected to have steeper transfer characteristics, and hence, a higher gain in the transition region.
5.10 Consider the CMOS inverter designed in Problem 5.9 above, with λ = 0.1 V-1
Now consider a cascade connection of four identical inverters, as shown below.
(a) If the input voltage is Vin = 0.598 V, find Vout1, Vout2, Vout3 and Vout4. (Note that this requires solving KCL equations for each subsequent stage, using the nonzero λ value).
Vin Vout1 Vout2 Vout3 Vout4
SOLUTION : nMOS VT0,n = 0.53 V, μnCox = 98.2 μA/V2, EC,nLn = 0.4V, vsat,n = 124340 m/s Cox,n = 22mF/m2 pMOS VT0,p = -0.51 V, μpCox = 46.0 μA/V2, EC,pLp = 1.8V, vsat,p = 70000 m/s Cox,p = 19.5mF/m2 VDD = 1.2 V < Short Channel Solution > 22 ,0,,,0,, 22 0,0, 2 0, 1 11(/)()(1)(/)()(1) 22 11(/)()(1)(/)()(1()) 22 0.5(/)()0.5 noxnGSnTnnDSnpoxpGSpTppDSp noxninTnnoutpoxpinDDTppoutDD noxninTnpox out CWLVVVCWLVVV CWLVVVCWLVVVVV CWLVVC V −+=−+ −+=−−+− −−+ = 2 0, 22 0,0, 6262 6 (/)()(1) 0.5(/)()0.5(/)() 0.598.2108(0.5980.53)0.546108/0.843(0.5981.20.51)(10.11.2) 0.50.198.2108(0.5980 pinDDTppDD nnoxninTnppoxpinDDTp WLVVVV CWLVVCWLVVV −−+−++ = − 262 6262 2 626 .53)0.50.146108/0.843(0.5981.20.51) 0.690V 0.598.2108(0.690.53)0.546108/0.843(0.691.20.51)(10.11.2) 0.50.198.2108(0.690.53)0.50.146108/0.843 (0.69 outV +−+ = −−+−++ = −+− 2 2 3 4 1.20.51) 10V00V 1.2V 0V out out out V V V + =−→= = =
Long Channel Solution >
<
(b)How many stages are necessary to restore a true logic output level?
In long channel : Two stages
In short channel : One stage
(c)Verify your result with SPICE simulation. Two stages
( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 2 ,0, ,, ,0,, 2 ,0, ,, ,0,, 2 0, ,, 0,, 2 0, ,, 1 1 1 GSnTn nsatnoxnnDS GSnTncnn SGpTp psatpoxppDS SGpTpcpp thTn nsatnoxnnOUT thTncnn thDDTp psatpoxp thD VV WvCV VVEL VV WvCV VVEL VV WvCV VVEL VVV WvC VV + −+ =+ −+ + −+ = ( ) ( ) 0,, ,11 ,2 ,3 ,4 1() 8.8V00V 1.2V 0V 1.2V pOUTDD DTpcpp OUTout OUT OUT OUT VV VEL VV V V V +− −+ =−→= = = =
