International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395-0056
Volume: 07 Issue: 01 | Jan 2020
p-ISSN: 2395-0072
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Design of a Round Robin Bus Arbiter using System Verilog Ansuman Mishra M.Tech, ECE Dept., Manipal Institute of Technology, Manipal, India ---------------------------------------------------------------------***----------------------------------------------------------------------
Abstract – In SoC’s (System on Chip), the number of buses and their interconnection with different subsystems and functional blocks for communication have risen exponentially in the present generation designs. Bus arbiters are highly efficient in handling master bus requests and slave bus responses. The bus arbiter is usually coded according to an algorithm which dictates its operation and efficiency. A Round robin arbiter scheme is based upon the concept of fixed slot per requestor. The most common way of behavioral modelling a round robin arbiter is by using “nested-case” statement in Verilog. However, this coding style is not at all efficient and is lengthy, when the number of requestors are high. This paper describes how to code the arbiter efficiently and in a compact manner using System Verilog language.
coming of Fixed Priority Algorithm is that the time interval before the grant is provided to the lowest priority process has no limit [5]. In Round Robin Algorithm, every process request is allowed a grant in a cyclic order. Here, a pointer is designated, and it shifts to next process request. Hence, the maximum wait period before a request is re-serviced again is dependent on the number of requestors in the queue. 2. DESIGN METHODOLOGY The Round Robin Arbiter can be modelled in system Verilog using nested case statements. However, this style of coding being simple, and primitive is highly inefficient when the number of requestors is more. The style of coding also affects the synthesis output. The proposed way of coding involves the request process which is pointed by a pointer is assigned the top most priority and remaining all other requests are rotated behind it. This rotated request vector is then sent through a simple priority arbiter. The grant vector from the priority arbiter is then “unrotated” to come up with the Round-Robin Arbiter’s final grant signal. The Fig.1 depicts the operation.
Key Words: Round Robin Arbiter, Bus arbitration, System Verilog. 1. INTRODUCTION Modern generation SoC (System on Chip) design increases the complexity of on-chip bus-based communication architecture. Communication architecture generally deals with interaction of control and data signals amongst the various functional blocks[1]. Bus based architectures are usually preferred in SoC designs as they are power efficient and provide the framework for complex interconnections. An arbiter is a crucial component in shared bus architecture[2].
Fig -1: Operation methodology for Round Robin Arbiter.
Most of the arbiters are modelled based on an algorithm which governs its overall operation and performance. Some of the most commonly used algorithms are:
For this paper, a 4-bus round robin arbiter is considered. The block diagram of the Round Robin Arbiter modelled using System Verilog HDL is shown in Fig 2.
1. Fixed Priority Algorithm. 2. Round Robin Algorithm. The Round Robin Algorithm allows each requestor to be served and once served, the requestor is moved to the end of the queue. i.e. lowest priority is assigned to it the maximum wait period time interval a requestor has to wait before the re-service of its request is dependent on the total number of requestors in the queue[3]. Round Robin Bus Arbiter is widely used for shared bus arbitration, queueing & work load balancing[4]. 1.1 Round Robin Algorithm Round Robin is a CPU scheduling algorithm. A fixed time slot is assigned to each process in the queue. It is quite simple in implementation and avoids process starvation. The short
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Fig -2: Top Level block diagram for Round Robin Arbiter.
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