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pilers m o C d n a ectures t i h c r A d mbedde E e c n a Perform h g i H n o ellence c x E f o Network q u a r t e r ly appears

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Message from the HiPEAC coordinator

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Message from the project officer

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HiPEAC Conference

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Microthreads, Microcontexts and Microgrids - scaling performance to the end of silicon

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Steering Committee

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PHD News

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A presentation of HiPEAC Greece

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A presentation of HiPEAC Cyprus

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Upcoming events

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o t e m o Welc 2005 C A E P i H e c n e r Confe

www.hipeac.net HiPEAC Conference Barcelona November 17-18 2005

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Message from the HiPEAC coordinator

Mateo Valero Coordinator UPC Barcelona mateo@ac.upc.edu

Dear colleagues, After the summer recess, we are back and ready for a new series of HiPEAC activities.

This summer, HiPEAC celebrated its first anniversary. We marked the occasion with our successful HiPEAC summer school on advanced computer architecture and compilation for embedded systems (ACACES).

The ACACES summer school was held in L'Aquila, Italy, during the last week of July. 184 participants from 21 countries took courses taught by twelve top researchers from both academia and industry around the globe (including three Eckert-Mauchly award winners).

Highlights included a keynote talk by Sir Maurice Wilkes and an invited talk on the Cell processor by Jim Kahle from IBM. The poster session (with about 77 posters) was an interesting opportunity for students to share comments on their current research activities. The general appreciation for the summer school was

4.41/5, which is very high, and most participants expressed their intention to come back next year, which is the greatest compliment for us. Apart from the educational activities, the Summer School acted as a meeting point for the HiPEAC community, facilitating new contacts and the creation or consolidation of HiPEAC research clusters. As a result of these contacts, HiPEAC academia and industry members are preparing seven STREPs to be submitted to the fifth call of the IST priority strategic objective 'embedded systems' in FP6.

ACACES closed with a gala dinner, and

HiPEAC members had the opportunity to get to know one another better by sharing some beers and making good use of the dance floor at the party that followed, which was the high point of a successful event. I seized this opportunity to thank once again the summer school steering committee, Koen De Bosschere, Michiel Ronsse, the local staff from TILS, and the ACACES professors and students for their dedication and enthusiasm.

The first HiPEAC Conference will be held on 17-18th November 2005 in Barcelona. 18 papers have been selected

Message from the project officer To foster public/private R&D partnerships with the aim of boosting Europe's industrial competitiveness, the European Commission has proposed the launching of European Technology Platforms http://www.cordis.lu/technology-platforms/.

Relevant to the activities of HiPEAC is ARTEMIS (Advanced Research and Technology for EMbedded Intelligence and Systems), which aims to develop and implement a common European strategy for achieving global leadership in Embedded Systems.

See http://www.cordis.lu/ist/artemis/index.html Work on ARTEMIS started in January 2004 when, following demand from industry and the research community, Commissioner Erkki Liikanen called the first meeting of a High Level Group.

A number of meetings then followed to decide the scientif-

ic and technological directions, operational goals and application drivers, and to discuss rules for governance, openness and transparency. On 28-29 June 2004, the platform was launched at a Conference in Rome with more than 100 participants from industry, member states and academia. The vision document "Building ARTEMIS" is the result of that work.

ARTEMIS was also presented at the IST 2004 Conference in The Hague on 17th November 2004. A public session was organised and the Steering and Executive Boards were established. To complete the governance structure, there is a Mirror Group that ensures the participation of Public Authorities at national, regional and European levels, and an office that provides permanent secretarial, opera-

tional and public relations support.

The second ARTEMIS annual conference was held on July 2005 in Paris.

Around 200 delegates attended and the atmosphere was lively and enthusiastic with a real sense that the platform is now in motion. One of the key events was the presentation of the Strategic Research Agenda. ftp://ftp.cordis.lu/pub /ist/docs/artemis/june_sra.pdf The document is a first step to a more detailed one expected by the end of the year, which will contain deeper technical content and roadmaps.

HiPEAC and ARTEMIS have good links.

Mateo Valero, who is coordinating HiPEAC, is a member of the ARTEMIS Steering Board. I would like to invite the HiPEAC community to contribute actively to the Strategic Research Agenda. â–

Mercè Griera-I-Fisa (Merce.Griera-i-Fisa@cec.eu.int)

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out of 84 by a prestigious Programme Committee (97 reviewers, 50% European researchers, 50% US researchers).

The Conference Proceedings will be published in the Lecture Notes in Computer Science (LNCS) series. The best papers from the HiPEAC Conference will be published in the HiPEAC Journal, whose first issue is expected in January 2006. I look forward to seeing many of you in Barcelona!

HiPEAC research clusters have met again for two days in Ghent in October 2005.

The meeting has been enlarged to foster interaction among members and to allow them to participate in more than one cluster. We plan a new cluster call as well, with the purpose of integrating industrial contacts into existing clusters.

In this way, HiPEAC aims at strengthening the ties between academia and industry.

Another activity to which HiPEAC will devote much effort during the present

ACACES 2005 Participants

quarter is the production of a HiPEAC roadmap. A selected group of experts in processors, compilers and systems - with a balanced participation of industry and academia - will prepare a first draft to be ready by the end of the year.

A new collaboration between HiPEAC and Princeton University has been given the go-ahead by the USA NSF (USA National Science Foundation) within the framework of the EC - NSF joint research programme.

HiPEAC will participate in the EC/IST - NSF workshop to be held during the

eChallenges conference in October 2005.

Finally, HiPEAC will undergo its first official European Community review. We are confident that the work done, of which you have been informed through these newsletter, will please our reviewers. Nevertheless, our mission is to continue strengthening our community, and therefore we will do our best to continue offering high quality events and enlarging the participation of both industrial and academic members in HiPEAC activities.

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HiPEAC conference It is a pleasure for us to invite you to the HiPEAC Conference 2005, our next major event. It will take place in Barcelona, November 17-18, right after MICRO-38.

Since the last Newsletter, all the Chairs have been very busy, preparing the proceedings, the program, the registration and the conference facilities. We are all very excited and pleased with the quality and diversity of submitted papers. The Program Committee received a total of 84 submissions. Among them, 17 were selected for presentation as full-length papers and another as invited paper. Each paper was rigorously reviewed by three Program Committee members and at least one external referee.

The program, with contributions by authors from nine countries, is organized in five sessions. It presents important

results in a wide range of areas, including analysis and evaluation techniques, novel memory and interconnect architectures, security architectures, novel compiler and runtime techniques, and domain specific architectures. The Symposium proceedings are ready to be published as part of the Lecture Notes in Computer Science series (Springer-Verlag).

Besides the presentation of papers, there will be two keynotes delivered by prominent researchers from industry and academia. Markus Levy' s lecture will focus on the development of multicore processor benchmarks that address both heterogeneous and homogenous processor implementations. Per Stenström's lecture will cover new opportunities and challenges for the chip-multiprocessing paradigm. They will lead us to new directions for research and development in compilers and embedded systems.

The local Chairs have also prepared some coffee breaks, a relaxing excursion and a banquet. They will give the chance to meet with other researchers in the field during the tight two-day schedule. Great thanks and encouragement to all involved in the organization of the Conference!

Finally, don't forget: early registration is open. And if you are a full time student in a HiPEAC member institution, you can apply for a conference registration grant.

Please visit http://www.hipeac.net/ hipeac2005 and register soon.

We are looking forward to see you all in Barcelona!

Nacho Navarro

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In the spotlight

Microthreads, Microcontexts and Microgrids - scaling performance to the end of silicon For decades now the microprocessor industry has provided exponential growth in chip performance through clock speed.

This follows reductions in line width as well as architectural improvements, i.e. minimising the amount of work performed in a clock period through superpipelining. The good times, however, have now come to an abrupt end. Pipeline depths are now optimal and power density, which grows with clock rate, has reached a melt-down point, with the result that it is increasingly difficult to improve performance through frequency alone. Industry now finds itself in a position where it must undergo a radical change and shift its focus from clock speed to concurrency as a means of improving performance, mostly through the use of multiple cores or chip multiprocessors (CMPs).

Concurrency is difficult however, and has traditionally been extracted from sequential code through instruction-level parallelism (ILP), which is an inherently unscalable process. So what are the alternatives?

Current approaches are small scale and are programmed with multiple threads, but these will not scale, simply because of locality issues. Ideally, an ILP approach is required with legacy sequential code.

The good news is that transistor level concurrency grows at twice the rate of clock speed, but to translate this into speedup requires scalability in layout. This means all on-chip structures should scale with issue

width and scalability in performance, so that the exponential growth in transistors is translated into issue width, which in turn is translated into performance. These are non-trivial issues. At the University of Amsterdam we are working on explicitly concurrent ISAs that have these characteristics. They are fully scalable in layout, they can be programmed from sequential code and recently we have shown scalability across two and a half orders of magnitude of issue width (see figure 1) without significantly increasing the energy consumed (see figure 2).

Our approach breaks down code from a single context into small fragments, which can then execute concurrently - these are called microthreads. Microcontexts, iterations from loop-level concurrency, are then distributed to multiple processors with a known distribution, where instructions are scheduled according to data availability. This static placement with dynamic schedules is important for optimisation of data movement and is similar to two other research projects (TRIPS and Wavecache). Unlike these approaches however, microthreaded binary code contains parametric concurrency and is schedule invariant. The same binary code (a hydro fragment from the Livermore loops) was executed on our Alpha CMP simulator from 1 up to 2048 processors.

Figure 1. Relative speedup from running a single binary kernel on a microthreaded Alpha CMP, using from 1 to 2048 processors. The speedup is within 2% of the ideal over two and a half orders of magnitude.

Figure 2. Relative energy dissipated for the same computation using from 1 to 2048 processors. The energy is constant to with 2% over two and a half orders of magnitude.

For more information and publications on microthreading, see the CSA web site http://www.science.uva.nl/research/csa/,

where links can also be found to other CMP resources.

Chris Jesshope ■

in the ISI database.

2. HiPEAC will hire an engineer for the development of the simulation and compilation platform. The engineer will be based at INRIA. He starts October 2005.

3. New members: • Prof. Henk Corporaal (Technical University Eindhoven) was accepted as a new member of HiPEAC. • ACE Associated Compiler Experts

b.v. was accepted as new industry member of HiPEAC. 4. The steering committee decided to organize ACACES 2006 in L'Aquila - Italy again, in July 2006.

5. The industrial partners of HiPEAC will attend the steering committee meetings with the same rights as the academic members.

Steering committee 1. The steering committee decided to publish the HiPEAC journal with Springer.

The journal will be electronically available and once a year, Springer will publish all the papers of a particular year as an issue of Lecture Notes in Computer Science.

This procedure combines fast electronic publication with a widespread dissemination of the printed version in libraries.

Furthermore, the LNCS series is indexed

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PHD News

Alternative Array Storage Layouts for Regular Scientific Programs

By Jeyarajan Thiyagalingam, jeyan@doc.ic.ac.uk, Prof. Paul Kelly, Imperial College London, April 2005, currently at University of Westminster Current programming languages use rowmajor or column-major for two-dimensional arrays. Spatial locality is very poor if an array is not traversed in the order in which it is stored. Hierarchically-blocked

Morton layout competitive (even for nonblocked loops), and evaluates the results on a variety of different platforms. http://www.doc.ic.ac.uk/~phjk/PhDTheses -LocalCopies/JeyanPhD.pdf

non-linear storage layouts, such as Morton ordering have been proposed as a compromise between row-major and columnmajor layouts. This thesis analyses the compilation techniques needed to make

Design Alternatives In Multibanked First-Level Data Caches

By Enrique Torres, ktm@unizar.es, Profs. Pablo Ibáñez and Víctor Viñals, University of Zaragoza (Spain), June 2005.

This thesis addresses the distribution of the first level data cache and the memory structures related to it. In the context of the Sliced Memory Pipeline, we study bank predictors and propose new recovery schemes for latency misprediction. We analyze a set of specific policies to issue a

lifetime in the pipeline and the data forwarding behavior, we propose a two-level STB design in which forwarding is done speculatively from a distributed first-level STB made of extremely small banks, while a centralized, second-level STB enforces correct store-load ordering.

load to several banks in limited cases and evaluate different cache contents management policies. Last, we address the distribution of the Store Buffer. Our goal is to forward data from in-flight stores to dependent loads within the latency of a cache bank. Taking into account the store

Some directed graph algorithms and their application to pointer analysis

By David Pearce, david.pearce@mcs.vuw.ac.nz, Prof. Paul Kelly, Imperial College London, June 2005, currently at Victoria University New Zealand This thesis is focused on improving execution time and precision of pointer analysis, to determine the targets object set for all pointer variables in a program.

We present a novel, and very practical, approach to field-sensitive analysis of C.

Two new algorithms for dynamically maintaining the topological order of the resulting directed graph are presented, and we demonstrate how both algorithms can be extended to the problem of dynamically detecting strongly connected

components (i.e. cycles). Finally, we provide a detailed study of numerous solving algorithms, evaluating our techniques and algorithms against previous work. http://www.mcs.vuw.ac.nz/~djp/#thesis

The following clusters were granted: Title

Main applicant

Identification and Specialization of Frequent Patterns of Computations in Programs

University of Cyprus

Co-Exploration of embedded processor architectures and code transformations

RWTH Aachen

Budget 4000 10500

Confidence estimation and fetch gating using state-of-the-art branch predictors

INRIA

CMPs-based network and storage I/O subsystems

Delft University of Technology

33750

8000

System-level Software Optimization (Extension)

UPC

20600

Statistical simulation techniques for uniprocessor and multiprocessor systems

Ghent University

8000

Applying Self-x-techniques to Enhance Robustness of Networked Embedded Systems

University of Augsburg

4000

Scalable System Architectures: extension

FORTH

5000

GCC research platform cluster

INRIA

18000

The following paper presentation budgets were granted: Title

Applicant

Presentation of paper under HiPEAC label (ICS)

UPC

Budget 1400

Presentation of paper under HiPEAC label (ICS)

UPC

1400

Presentation of paper under HiPEAC label (DAC)

RWTH Aachen

2500

Presentation of paper under HiPEAC label (LCTES)

Ghent University

1450

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HiPEAC Partner

A presentation of HiPEAC Greece The word "Architect" is Greek, and comes from "archi" (beginning, leading) and "techton" (carver (esp. of wood), craftsman, builder, constructor): the architect is the chief constructor.

Interestingly, the same root "techton" has generated the Greek words "techni" (art), "techniki" (technique), and "technologia" (technology). Thus, depending on your

viewpoint, you may consider the architect to be either the chief artist, or the chief technologist, or both....

Talking of ancient Greece, the "Antikythera Calculator", dating from around 100 B.C., is the oldest known geared mechanism. It was found in a ship traveling from Rhodes to Rome, which sunk near the island of Antikythera, between the Peloponnese and Crete. This bronze mechanism, consisting of 32 gears, is believed to be an analog calculator designed to track the movements of the sun, the moon, Mercury, Venus, Mars, Jupiter, and Saturn.

FORTH The Foundation for Research and Technology Hellas (FORTH) is one of the largest Greek public research centers. It consists of 7 institutes in 4 cities other than Athens, and collaborates closely with many Greek and international Universities and companies. The Institute of Computer Science (ICS), located in Heraklion, Crete, is the largest FORTH institute, with about 40 researchers and faculty members, 100 student fellows, and 200 technical staff.

The Computer Architecture and VLSI Systems (CARV) Laboratory is one of the seven such Labs of ICS.

on Interconnection Networks, which have been a main R&D topic for the CARV Lab over the past 20 years. Past work emphasized per-flow queueing, multilane flow control, and advanced scheduling for robust networks with QoS guarantees. The 6-million-transistor single-chip ATLAS I switch, designed in 1996-98, featured credit-based flow control at the granularity of 32 thousand flows.

Other work included hardware for managing thousands of queues in DRAM at 10 Gb/s line rate and pipelined heap management for weighted fair queueing at line rates of 10 Gb/s or more. Current emphasis is on buffered crossbar switches, and on flow and congestion control for the future switching fabrics made out of emerging commodity switches. In addition, Network Interface (NIC) architectures are an essential component of future intercon-

nects, and a research topic of revived interest in FORTH.

(APEL) is one of the main laboratories in the Department (founded in 1975) and performs research and teaches courses in the areas of electronics, microelectronics, microprocessors and microcomputers, embedded systems, telecommunication electronics, and real time networks. Over 200 Masters and over 40 Ph.D. theses have been completed in the past twenty years. The Computer Systems Laboratory (founded in 1991) has as its main objective the teaching and research in the area of Computer and Information Systems. Among its areas of current research activity are security and special purpose computer architectures. The VLSI Design Laboratory (founded in 1986) covers research areas in microelectronics, integrated

circuits, modern electronic design, applications for DSP, CAD tools, and parallel processing.

In the architecture of modern computer, storage, communication, and networking hardware, the central open question is how to make Scalable Systems. Their architecture relies

University of Patras The University of Patras is established as one of the premier schools in Greece for Computer Engineering and Computer Science. The architecture group at the ECE Department of the University of Patras comprises several researchers, including among others Stefanos Kaxiras, Georgios Papadopoulos, Dimitrios Serpanos, Stavros Koubias, and Dimitris Lioupis (CS Department).

The architecture group taps into the combined research expertise of three laboratories: the Applied Electronics Laboratory, the Computer Systems Laboratory and the VLSI Design Laboratory. The Applied Electronics Laboratory

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In modern Greece high technology developed late, so many Greek scientists found themselves abroad in the second half of the twentieth century, especially in the USA. This significant pool of talent constituted the basis for modern Greek technological development; programmes like the

Systems Software (run-time systems & OS, compilers and middleware) goes hand-in-hand with hardware architecture in achieving the efficient operation of information systems. The Scalable Systems described above rely critically on run-time software, which is the focus of FORTH work.

CARV concentrates on clusters of commodity components because they can scale to very large numbers of processors. In particular, work is on low-latency, high-bandwidth communication subsystems, block-level storage architectures, storage virtualization, storage access protocols, computer systems dependability and security support (networked storage security, system reliability and availability, and

Several faculty members of the ECE Department, including members of the architecture group, are affiliated with the Industrial Systems Institute (I.S.I). This is also located in Patras, and operates under the supervision of the General Secretariat of Research and Technology of the Greek Ministry of Development. The charter of I.S.I. is to contribute to the improvement of the competitiveness of Greek industry, through transfer of knowledge and application of state-of-the-art technologies relating to integrated industrial systems. In many instances, I.S.I. is the bridge

EU Marie Curie fellowships still allow us to draw from that pool. The first two Greek University departments in Computer Science and Engineering started operating in the first half of the eighties, in Patras and in Crete. Today, there are about two dozen such departments in Greece; the most active ones in Computer Architecture are in the University of Crete (Heraklion) and the Technical University of Crete (Chania), in the University of Patras, and in the National Technical University of Athens. A number of research centers and institutes also developed in the same time frame.

High tech hardware industry has developed in Greece since the eighties; an early major contributor was the communicanetwork interface support for security-sensitive applications), and, more recently, on device miniaturization and sensor networks.

Other work is on VLSI circuit design, which has grown to be extremely complex. CARV currently works on Timing Methodologies for VLSI systems, because this will be a major issue in future systems due to very high clock frequencies, manufacturing variability, power consumption and EMI emissions. Asynchronous techniques have been investigated, since they lie at the basis of the most promising solutions.

Commercial EDA tools have been adapted to the use of asynchronous techniques, with excellent research results and good potential for application to real industrial projects.

Finally, FORTH-ICS has an active programme in

to industry and to real-world applications.

The department's composition and the affiliation to I.S.I. influence in large part the foci of research in architecture. There is significant interest in embedded systems (from architecture, to system software, to applications), lowpower (from electronics to architectural techniques for low power), parallel and chip-multiprocessor architectures, security, and networks (from wireless to on-chip interconnection networks). This range of interests allows wide interaction with many partners (both industrial and academic) and this is evident in the number of successful participations in European projects. Currently, attention and resources are

tions company Intracom. The field has flourished in the last ten years, with several SME's taking advantage of University graduates with research experience: ISD, Ellemedia, inAccess Networks, 4Plus, Globetech Solutions, Theta Microelectronics, Athena Semi, Helic, Photronics Hellas, Sciensis, Alma Technologies, GDT, and others. Some of these cooperate very closely with large international companies (ST Microelectronics, Lucent/Bell Labs), while in two other cases ATMEL and INTEL have bought Greek SME's making them into advanced R&D Labs of their own. â–

Information Security, which includes research in network monitoring for detecting worms, intrusions and DoS attacks. Such detection needs high-speed pattern matching, and work has included the required specialized hardware or parallel multi-core (network) processors.

People: Manolis Katevenis, Angelos Bilas, Dionisis Pnevmatikatos, Christos Sotiriou, Evangelos Markatos. http://www.ics.forth.gr/carv/ http://www.ics.forth.gr/infosec/

oriented towards researching various aspects of chip multi-core architectures (power management, on-chip memory architecture, onchip and off-chip communications, system software, etc.) but with an emphasis on the embedded world.

People: Stefanos Kaxiras, Georgios Papadopoulos, Dimitrios Serpanos http://www.ee.upatras.gr

A presentation of HiPEAC Cyprus The Department of Computer Science at the University of Cyprus was founded in 1992 and research in the area of Computer Architecture commenced in 1994. The activity in this area grew considerably in 2002 when two faculty members with specialty in Computer Architecture joined the department. Currently, three faculty, six graduate students, and nine undergraduates are conducting research in various areas of Computer Architecture.

The group expertise and contributions lie in several areas including: data-driven multithreading, pervasive computing, patterns of computation, prediction and speculation techniques, architecture-aware optimizations for database workloads, advanced memory technologies, power and temperature aware microarchitectures, multi-cores, cache redundancy, performance metrics, grid computing, graphics processors, performance evaluation and benchmarking.

Several of the research activities are done in collaboration with groups in industry and academic institutions in Europe, Israel, and USA, and are funded from various sources including: European Union FP6, Intel, Cyprus Research Foundation, and the University of Cyprus.

The objectives for the coming few years are to further establish Computer Architecture research at the University of Cyprus by: (a) attracting high caliber students and securing funding for cutting edge research projects, and (b) increasing visibility through networking collaborative work, organization of conferences, and publication in top level journal and conferences. The eventual goal is to be among the leading research groups in the area of Computer Architecture. Cyprus membership and contributions in HiPEAC are instrumental towards the realization of these objectives.

People: Skevos Evripidou, Pedro Trancoso, Yanos Sazeides http://www2.cs.ucy.ac.cy/carch/ â–

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Upcoming events MICRO-38 Barcelona, Spain, 12-16 November 2005, http://pcsostres.ac.upc.edu/micro38/ HiPEAC Conference Barcelona, Spain, 17-18 November 2005, http://www.hipeac.net/hipeac2005/ Workshop on Distributed Embedded Systems Leiden University, The Netherlands, November 21-24, 2005, http://www.lorentzcenter.nl/lc/web/2005/20051121/info.php3?wsid=177 The Future of Configurable Hardware - Free ACES Symposium Ghent, Belgium, 6 December 2005, http://www.elis.ugent.be/FCH ISSPIT2005: The 5th IEEE International Symposium on Signal Processing and Information Technology, Athens, Greece, December 18-21, 2005, http://www.isspit.org/isspit/2005/ INTERACT-10, The 10th IEEE Annual Workshop on Interaction between Compilers and Computer Architectures Austin, Texas, February 12, 2006, http://www.cs.pitt.edu/~jinlei/INTERACT/ 9th Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-9).

Austin (TX), February 12, 2006. http://www.elis.ugent.be/~leeckhou/caecw9/ International Symposium in Performance Analysis of Systems and Software (ISPASS-2006).

Austin, Texas, March 19-21, 2006.http://ispass.org 4th International Conference on Code Generation and Optimization (CGO 2006), Manhattan, NY, March 26-29, 2006, http://www.cgo.org/ ACM International Conference on Computing Frontiers Ischia, Italy, May 3-5, 2006, http://www.computingfrontiers.org/ Special issue on Embedded Systems for Portable and Mobile Video Platforms. Eurasip Journal on Embedded Systems, Deadline: June 1, 2006. http://www.hindawi.com Conference on Programming Language Design and Implementation, (PLDI 2006), Ottawa, Canada, June 11-14, 2006. http://research.microsoft.com/conferences/pldi06/ Conference on Languages, Compilers, and Tools for Embedded Systems, (LCTES 2006), Ottawa, Canada, June 14-16, 2006. http://www.elis.ugent.be/lctes2006/ PACT-2006, Parallel Architectures and Compilation Techniques, Seattle, September 16-20, 2006, http://www.pactconf.org/ Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS XII), San Jose, CA, October 21-25, 2006. http://www.princeton.edu/~asplos06/

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HiPEAC Info is a quarterly newsletter published by the HiPEAC network of excellence.

Funded by the 6th European Framework Programme (FP6), under contract no. IST-004408.

Website : http://www.hipeac.net.

Subscriptions: http://www.hipeac.net/newsletter

If you are a HiPEAC member, and you want to contribute to this newsletter, please contact Michiel Ronsse at Michiel.Ronsse@UGent.be

In the next issue: A presentation of HiPEAC Germany