info
3
mpilers o C d n a ectures t i h c r A d mbedde E e c n a Perform h g i H n o ellence c x E f o Network ly quarter appears
2
Message from the HiPEAC coordinator
2
Message from the project officer
3
HiPEAC’05 conference
3
General cluster meeting
4
A presentation of HiPEAC UK
5
ACACES 2005 Summer School
6
Steering Committee News
6
Community news
7
PhD news
8
Upcoming events
2005 | J u ly
o t e m o c l e W 5 0 0 2 S E C A C A www.hipeac.net
Call 5 of the IST priority Strategic objective ‘Embedded Systems’ Deadline: 21 September 2005 www.cordis.lu/ist/so/embedded-systems/home.html
intro
Message from the HiPEAC coordinator
Mateo Valero Coordinator UPC Barcelona mateo@ac.upc.edu
Dear colleagues, Once again, it is my pleasure to present to you the progress made on the activities in which the HiPEAC network is involved. We are all very excited about the response to the HiPEAC Summer School from the community. With a limit of 150 participants, applications soon outnumbered this figure. Fortunately, we were able to increase the capacity of the summer school to 200. The participation of top lecturers, along with the pleasant environment in L’Aquila, makes us look forward to a high quality event that will be the first one of a series.
With the passing of the paper submission deadline, the HiPEAC Conference world-class Program Committee is already at work. We expect our community to send first-class papers to the HiPEAC Conference (Barcelona, November 2005), thus, we hope for a high quality forum, devoted to computer architects and compiler builders working in the field of high performance computer architecture and compilation for embedded systems. The HiPEAC Conference is also open to general-purpose research, which is
becoming increasingly relevant to the embedded domain.
distributed among members for cluster related activities.
HiPEAC research clusters held their first meeting in Ghent in May 2005, with the participation of 60 HiPEAC members who had the opportunity to meet each other and share experiences and ideas. As announced in our previous newsletter, a new call for clusters opened with the purpose of admitting new participants to the existing clusters and defining new ones if need be. Up to now, 250.000 euro has been
The role of HiPEAC is fostering collaboration with companies and setting up relationships with academic groups outside Europe. With this aim in mind, HiPEAC industrial and academic members submitted an integrated project to the Call on Advanced Computing Architectures of the EC FET (Future and Emerging Technologies) programme in March 2005, and are working on a new proposal under Call 5 on Embedded
Message from the project officer I would like to start by reminding the HiPEAC community that 21st September 2005 is the deadline for submitting proposals to the IST 5th Call. The strategic Objective on Embedded Systems is calling for proposals on design methods, programming models and compilation tools for reconfigurable architectures. This research complements the Strategic Objective on Nanoelectronics the latter focuses on chip design including SoC and SiP, whereas in Embedded Systems the focus is on system design, from the application down to the embedded platform architecture. The call addresses both STREPs and Integrated Projects. STREPs are encouraged to explore emerging technologies or alternative approaches, opening new prospects in the field.
The research agenda of IPs should integrate basic and foundational research (e.g. computational models, architectures), component-based research (e.g. compilers, operating systems) and systems engineering and integration. Details on the call are at http://www.cordis.lu/ist/so/embedded-systems/home.html Meanwhile, we in the Commission are defining the content of the future 7th Framework Programme, which will determine the research topics that will be funded at the European level beyond 2006. In this context, last month we invited 15 experts to come to Brussels to discuss the main research challenges in a possible action on Computing Systems.
The experts concluded that the frontiers between Embedded Systems and General-Purpose Systems will be blurred. They considered that the challenges lie in increasing integration, performance and connectivity while preserving quality, reliability and security. New techniques, methodologies and tools to make computing systems easily adaptable to evolving market needs and to specific customer requests were the recommended research directions. The meeting’s report will soon be available on the Web with the aim of triggering a discussion within the community at large. Up to date information on the preparation of FP7 is available at http://europa.eu.int/comm/ research/future/index_en.cfm
Mercè Griera-I-Fisa (Merce.Griera-i-Fisa@cec.eu.int)
2
info3
■
HiPEAC ‘05 conference Systems of the IST programme. Furthermore, HiPEAC has begun a collaboration with two American universities within the framework of the EC - NSF (USA National Science Foundation) joint research opportunity. HiPEAC participates in the EC/IST - NSF workshop to be held in Paris on the 7th and 8th of July, with a view to furthering the joint efforts and exploring new opportunities for collaboration. As HiPEAC coordinator, I personally believe that the activities described above constitute steps taken in the right direction with respect to HiPEAC's mission of building an excellent, more cohesive community. But there is much more to be done. We invite you to take the opportunities that HiPEAC offers to our entire community and to participate in the upcoming events. ■
HiPEAC 2005, the first International Conference on High Performance Embedded Architectures & Compilers is scheduled to take place in Barcelona, Spain right after MICRO-38, so that you can attend both conferences. The 1st HiPEAC conference will be held at the Vincci Maritimo Hotel in Barcelona Diagonal Mar, the totally renovated area of Barcelona on the Mediterranean Sea shore that hosted the 2004 Universal Forum of Cultures. The Vincci is also one of the hotels used for Micro-38 and is less than 5 minutes walking distance from the Hilton Hotel in Barcelona Diagonal Mar where MICRO-38 is held. We expect a successful event, with an exciting program and keynote presentations. The conference is open to all researchers in our community. We encourage everybody, and HiPEAC members in particular, to participate in the conference. During the conference, a general HiPEAC assembly will also take place.
The details on the submission of papers, registration and all the important dates are on the conference website: http://www.hipeac.net/hipeac2005. ■
Report from the general cluster meeting, May 11, 2005 Following the decision of the steering committee to collocate the meetings of the different clusters, the first such meeting was organized in Ghent, Belgium on May 11th, 2005. There were 60 researchers registered across the different activities. After a plenary session in which Mateo Valero gave an update on the current status of HiPEAC, the participants spread out over the different cluster meetings (three in parallel at any given time). In total there were 10 cluster meetings
with the number of participants ranging between 10 and 20. During lunch there was a meeting of the steering committee. The general cluster meeting was quite productive. It was good to have a major portion of the HiPEAC community together in one location to discuss research. Several people showed interest in joining existing clusters, which was one of the aims of the general cluster meeting.
From the meeting we also learned the following: 1. It would be good to open up the cluster meetings for people that are not yet formally involved in a cluster. This will enable clusters to grow. 2. There should be more time for informal discussions and individual meetings during the general cluster meeting. 3. An event of this size needs more time than one day. A two-day meeting would have been more convenient. The next general cluster meeting will be organized during the Summer School in L’Aquila. Due to the nature of the summer school, the three improvements mentioned above will be automatically realized. ■
info3 3
HiPEAC Partner
A presentation of HiPEAC UK The UK’s involvement in Computer science stretches back to the 19th century with Charles Babbage. His Difference Engine, completed in 1832, was the first successful automatic calculator. His follow up, the Analytical Engine, was designed to perform symbolic manipulation, although it was never fully built. Nonetheless, it was a precursor to the computers of the 1940s, and for this reason Babbage is sometimes referred to as the “father of computing.”
foundations of computer science in his paper describing what later came to be referred to as Turing Machines. Shortly after, the UK developed the first electronic computer, the Colossus. Constructed in 1943, it was purpose built, solely designed for codebreaking, and deployed at Bletchley Park. Although powerful, the Colossus was not a general purpose programmable computer. However, the world’s first stored program machines were also developed in the UK - the Small-Scale Experimental Machine developed at Manchester by Freddie Williams and Tom Kilburn in 1948, and the EDSAC 1 developed at Cambridge under Maurice Wilkes in 1949.
The 20th Century has seen the UK pioneer the development of the theory and practice of computer science. In 1937, Alan Turing provided the theoretical
From these early foundations, many new companies and computer science departments developed throughout the second half of the 20th century to make the UK one of today’s world leaders in computer science.
Maurice Wilkes
HiPEAC UK contains the three highest ranked Computer Science departments in the UK: the University of Edinburgh, the University of Manchester, and Imperial College, London. It also includes the world’s leading semiconductor IP supplier, ARM Holdings PLC. ARM designs the technology that lies at the heart of advanced digital products, from wireless, networking and consumer entertainment solutions to imaging, automotive, security and storage devices. ARM licenses its IP to a network of partners, which includes some of the world’s leading semiconductor and system companies, including 19 out of the top 20 semiconductor vendors worldwide, shipping more than 2.5 billion ARM microprocessor cores. Overall, the UK is an international leader in computer science and will continue to help develop high performance embedded systems in the decades to come. ■
EDINBURGH: Institute for Computing Systems Architecture The ICSA is concerned with the architecture and engineering of future computing systems. In the microarchitecture group there is a strong emphasis on embedded computing and the migration of high-performance techniques into low-power embedded systems. This group is also researching new ways to automate the process of architecture and micro-architecture synthesis, primarily from a low-power perspective. Current research projects focus on the issues of design productivity in high-complexity deep sub-micron SoC systems, and the problems inherent in low-power highperformance embedded architectures for media-rich applications. This is addressed through the development of new automated micro-architecture synthesis methods that bridge the gap
4
info3
between physical design and high-level synthesisable structures. There is also research activity in asynchronous design styles and re-configurable processors. The compilers and high-level architecture group has particular strengths in iterative compilation and high-level compiler transformations. These concepts have been successfully applied, for example, in the areas of: automatic parallelisation of pointer-rich C code on parallel DSP systems; dynamic power reduction in superscalar out-of-order microprocessors; and code restructuring for high performance embedded applications. Current projects focus on the use of machine learning to produce compilers that learn how to optimise. ICSA works with industry both in
publicly-funded research programmes and industrially-funded research contracts as well as providing consultancy services. In recent years ICSA has collaborated with a broad range of industry partners including: ARM, ARC, Cadence, Hitachi, Lucent, Philips, Sharp, TRW, Lucas Aerospace and Xilinx. People: Michael O’Boyle, Nigel Topham http://www.icsa.inf.ed.ac.uk/
MANCHESTER: The Advanced Processor Technology group (APT) at the University of Manchester is active in a number of areas of computer architecture and compilation techniques. A particular strength of the group is in asynchronous processor design. The JAMAICA project is focusing on chip-multiprocessors with particular emphasis on exploiting parallelism by the use of a dynamic compilation virtual machine. This work extends into other areas such as native code execution (binary translation) and Java based operating systems. Members of the project are working with a version of the IBM Jikes RVM built on top of a flexible, cycle-accurate multiprocessor simulator.
The group has recently completed a contract to develop an ISA for a processor for ultra-low-power sensor networks. The resulting design employs a hierarchy of data processing engines from hardware, through a dataflow coprocessor for inner-loop power optimisation and DMA engines for bulk data movement, to a more conventional general-purpose core for overall control. The general-purpose core employs a variable length ISA for optimum code density, with variable length operands and 1- or 2-byte opcodes. Internal operations are also variable length, with the datapath deactivating unused fields to save power, and the ISA includes a set of bit manipulation operations for efficient peripheral control. ■
People: Ian Watson, Steve Furber http://www.cs.manchester.ac.uk/apt/
IMPERIAL: Much of research on computer systems at Imperial College London involves high performance embedded architectures and the corresponding compiler technology. Research on embedded architectures has resulted in many exciting developments for a wide variety of applications. Examples include several multi-processor engines, such as the SONIC architecture for video image processing, adopted by Sony for commercial broadcast quality production work, and the fastest-known single-chip field multiplier for elliptic curve cryptography. Research on compiler technology includes the theory and practice of specifying and manipulating design representations for their compilation, transformation into hardware structures, analysis involving pointer aliasing or bitwidth optimisation, and exploration of the hardware-software codesign space. Members of Imperial have developed a
pointer/array bounds checking technique that forms a substantial element of the Mudflap technology in the recentlyreleased GCC4.0. Their field-sensitive pointer alias analysis algorithm has been adopted for inclusion in a future release of GCC4. Two of their hardware compilers, ASC and Handel-C, have been successfully commercialised by Maxeler and Celoxica respectively. Other major software tools resulting from their research include: the TaskGraph Library, a C++ library for run-time code generation and code restructuring; Pebble and Quartz, compilers for declarative languages for hardware analysis and synthesis. Finally, the group has close links with industry: Altera, Cisco, Celoxica, HP, IBM, Microsoft, Motorola, Sharp, Sony, and Xilinx. People: Paul Kelly, Wayne Luk.
ACACES 2005 International summer school on advanced computer architecture and compilation for embedded systems July 24 to July 30, 2005, L’Aquila, Italy The deadline for application to the summer school was May 15, 2005. Originally we expected in the region of 80 applications, but ultimately we got more than 200. The majority of the applications come from Europe, but in total there are 20 different nationalities, which makes the summer school a truly international event. Nine companies will also attend the summer school. Given the huge number of participants from HiPEAC institutions, the steering committee decided to increase the number of grants from 45 to 70, which allowed us to give grants to more than 80% of the HiPEAC PhD students that would otherwise not have had the financial means to attend the summer school. More than 80 students will present their work during the summer school. We decided to publish the poster abstracts in a small booklet that will provide the participants with an overview of the work in progress at the different HiPEAC institutions and beyond. During the summer school, there will be three additional events taking place: 1.Cluster meetings for different clusters 2.A meeting of the program committee for the HiPEAC conference 3.A HiPEAC external review meeting. The massive interest in the ACACES summer school clearly shows that there is a real need for this type of event. The HiPEAC network of excellence is committed to further develop the ACACES summer school into a major event in our community. ■
Koen De Bosschere Summer school organizer
http://www.doc.ic.ac.uk/~phjk/SoftwarePerfomanceOptimisation/iSPELHomePage.html
info3 5
Steering committee • The steering committee has decided on the list of top conferences in the domain of high-performance embedded architectures and compilation. This list is important in that the HiPEAC net-
work can sponsor the participation of a HiPEAC member in one of these conferences on the condition that he or she presents a paper that explicitly carries the HiPEAC label. This instrument is
International Conference on High Performance Embedded Architectures and Compilers - HiPEAC Design Automation Conference - DAC International Symposium on Computer Architecture - ISCA Real-Time Systems Symposium - RTSS International Symposium on Microarchitecture - MICRO
meant to stimulate the visibility of European research at these top international conferences. • The steering committee has decided to organise 4 general cluster meetings a year – ideally to be collocated with another HiPEAC event such as the summer school or the HiPEAC conference. The first general cluster meeting took place in Ghent on May 11, 2005. The second one is scheduled during the summer school in L’Aquila, June 24-30, 2005. • Given the huge number of applications for Summer School grants by HiPEAC members, the steering committee decided to increase the number of grants from 45 to 70.
Design, Automation and Test in Europe - DATE Conference on Programming Language Design and Implementation - PLDI International Conference on Computer-Aided Design - ICCAD International Conference on Compilers, Architectures and Synthesis for Embedded Systems - CASES International Symposium on Low Power Electronics and Design - ISLPED Conference on Languages, Compilers and Tools for Embedded Systems - LCTES
• 8 projects were evaluated: 4 new projects and 4 projects that were postponed during the last Cluster Call. Of these 8 projects, 1 project was not accepted and 7 were accepted. ■
Architectural Support for Programming Languages and Operating Systems - ASPLOS International Conference on Hardware - Software Codesign and System Synthesis – CODES-ISSS International Symposium on High-Performance Computer Architecture - HPCA International Conference on Parallel Architectures and Compilation Techniques - PACT International Conference on Supercomputing - ICS
Results of the second Cluster Call:
Community news Prof. Stamatis Vassiliadis (HiPEAC partner, TU Delft, The Netherlands) received an ACM Fellowship on June 11, 2005 “for inventions in processor architecture and design”. Hans Vandierendonck (postdoc at the department of electronics and information system, UGent, Belgium) won the IBM Prize Belgium for Computer Science for his PhD thesis “Avoiding Mapping Conflicts in Microprocessors”. The prize will be awarded in fall 2005 at the Fund for Scientific Research in Brussels.
Coordinator
Title
Amount granted
University of Amsterdam
System Level Performance/Power Evaluation of Stream Processing Embedded Systems
1800
UPC
Collaboration on vector processing research
6000
University of Patras
Power-efficient Cache technologies
32000
University of Cyprus Activation/Deactivation of Overriding Predictors in High-Performance Processors for Increased Power Efficiency
4500
University of Augsburg
Reconfigurable SoC with multithreaded processor core (extending the “Collaboration on Multiprocessor design” cluster)
13900
University of Patras
Travel funding for INFOCOM
2000
INRIA
Presentation of an article at the ISCA symposium
2340
TOTAL: 62540
6
info3
PhD news Data scheduling management in multi-context reconfigurable systems focused on low energy Marcos Sánchez-Élez Martín, marcos@fis.ucm.es, Prof. Milagros Fernández Centeno and Prof. Nader Bagherzadeh, ArTeCS, Complutense University, Madrid, Spain, November 2004. This dissertation presents data scheduling for coarse-grain reconfigurable architectures targeting DSP and multimedia applications. The main goal is the reduction of the energy consumed by these applications through the integration of the data management frame-
work within a compilation framework specifically conceived for these architectures. The data manager tries to optimally exploit the storage hierarchy by saving data transfers among on-chip and external memories. Also, a data placement and replacement policy has
been designed. A dynamic scheduler has been also developed, which avoids reconfigurable processing unit stalls due to operands unavailability, through profiling methodologies and search algorithms.
Instruction Set Extensions for Elliptic Curve Cryptography over Binary Finite Fields by Irina Branovic, branovic@dii.unisi.it, Prof. Roberto Giorgi and Prof. Enrico Martinelli, University of Siena, April 2005. Elliptic Curve Cryptosystems (ECC) employ shorter operand lengths compared to other public-key cryptosystems and are thus especially attractive for use in embedded devices. In this dissertation, we present ISA extensions for an embedded processor for ECC over bina-
ry finite fields that can efficiently replace a coprocessor that is typically used for improving performance of ECC. We proposed to extend the ISA with instructions for word-level polynomial multiplication and evaluated the impact of such extensions for Intel
XScale processor (ARM architecture). The proposed instructions improve the execution time on average by 37%, compared to the pure software implementation.
Advanced Stream Prediction Oliverio J. Santana, osantana@ac.upc.edu, Prof. Alex Ramirez and Prof. Mateo Valero, Universitat Politecnica de Catalunya, Barcelona, Spain, May 2005. The work presented in this dissertation describes complexity-effective branch prediction mechanisms, which provide accuracy comparable to state-of-the-art predictors, while requiring lower implementation cost and complexity. Moreover, our proposals also increase
the capabilities of the branch prediction architecture. We describe techniques for tolerating the access latency of the prediction tables, as well as reducing their energy consumption. In addition, we extend the branch predictor functionality to guide a novel decoding
architecture that allows removing the complex instruction decoders from the critical path. All together, our proposals open a path toward the design of complexity-effective fetch architectures for high-performance processors.
CRISP: A Scalable VLIW Processor for Low Power Multimedia Systems By Francisco Barat, Prof. Henk Corporaal and Prof. Rudy Lauwereins, IMEC, Belgium, May, 2005. This dissertation shows that widening a very long instruction word (VLIW) processor can be an effective way to improve the energy efficiency of multimedia applications if the adequate architectural and compilation techniques are used to overcome the scaling limitations of VLIW processors. It pres-
ents and evaluates the coarse-grained reconfigurable instruction set processor (CRISP) architecture and its compiler. The CRISP architecture is a cross-breeding of clustered VLIW architectures and reconfigurable instruction set processors. Its foundations are a clustered data-path with support for predication
and two novel architectural features, namely an instruction fetch path with scalable bandwidth, and software controlled functional unit chaining. This dissertation also presents an extensible design space exploration framework for CRISP.
Reliable, Retargetable and Extensible Link-Time Program Rewriting By Bruno De Bus, bruno.debus@elis.ugent.be, Prof. Koen De Bosschere, Department of Electronics and Information Systems, Ghent University, Belgium, May 2005. This dissertation presents Diablo, a LinkTime Program Rewriting (LTPR) framework that is reliable, extensible and easy to retarget. The framework consists of a flexible internal program representation, and a variety of reusable
whole program analyses, optimizations and transformations that can be used to develop LTPR applications. We present three mature link-time rewriting applications: the program optimizer Diablo (with backends for ARM, x86,
MIPS, IA64, SH3, PowerPC and Alpha), the program instrumentation tool Fit (ARM, x86 and Alpha) and the information hiding program Stilo (x86).
info3 7
Upcoming events SAMOS V: Embedded Computer Systems: Architectures, MOdeling, and Simulation Samos, Greece, July 18-19-20, 2005, http://samos.et.tudelft.nl/samos_v/ ACACES 2005 First International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems L’Aquila, Italy, July 24-30, 2005, http://www.hipeac.net/acaces2005/ Euro-Par 2005 Lisbon, Portugal, August 30 – September 2, 2005, http://europar05.di.fct.unl.pt/ PACT-2005: The Fourteenth International Conference on Parallel Architectures and Compilation Techniques Saint Louis, Missouri, September 17-21, 2005, http://pact05.ce.ucsc.edu/ MEDEA Workshop - MEmory performance: DEaling with Applications, systems and architecture held in conjunction with PACT 2005, Saint Louis, Missouri, Sept. 17-21, 2005, http://garga.iet.unipi.it/medea05/ CODES+ISSS 2005: International Conference on Hardware - Software Codesign and System Synthesis New York, September 19-21, 2005, http://www.codes-isss.org/ PATMOS 2005: International workshop on Power and Timing Modeling, Optimization and Simulation Leuven, September 20-23, 2005, http://www.imec.be/patmos/ ISSWC: 2005 IEEE International Symposium on Workload Characterization Austin, Texas, October 6-8, 2005, http://iiswc.org/iiswc2005/ MICRO-38 Barcelona, Spain, 12-16 November 2005, http://pcsostres.ac.upc.edu/micro38/ HiPEAC Conference Barcelona, Spain, 17-18 November 2005, http://www.hipeac.net/hipeac2005/ The Future of Configurable Hardware - Free ACES Symposium Ghent, Belgium, 6 December 2005, http://www.elis.ugent.be/FCH ISSPIT2005: The 5th IEEE International Symposium on Signal Processing and Information Technology, Athens, Greece, December 18-21, 2005, http://www.isspit.org/isspit/2005/
HiPEAC ‘0c5e confer17e-1n8, 2005
r General Chai ho Navarro Tom Conte - Nac mittee Chair m Program Co Mateo Valero Wen-Mei Hwu -
November pain Barcelona, S
If you are a HiPEAC member, and you want to contribute to this newsletter, please contact Michiel Ronsse at Michiel.Ronsse@UGent.be
8
info
3
HiPEAC Info is a quarterly newsletter published by the HiPEAC network of excellence. Funded by the 6th European Framework Programme (FP6), under contract no. IST-004408. Website : http://www.hipeac.net Subscriptions: http://www.hipeac.net
In the next issue: A presentation of HiPEAC Greece • HiPEAC Conference