Design and Analysis of Content Addressable Memory

GRD Journals | Global Research and Development Journal for Engineering | International Conference on Innovations in Engineering and Technology (ICIET) - 2016 | July 2016

e-ISSN: 2455-5703

Design and Analysis of Content Addressable Memory 1Abarna.

I 2Mythili. R 1,2 Research Scholar 1 Department of Information and Communication Engineering 2Department of Electronics and Communication Engineering 1,2 KIT-Kalaignarkarunanidhi Institute of Technology, Coimbatore-641 402 Abstract The Content addressable Memory (CAM) is high speed memories that are used in high speed networks, lookup tables and so on.

The data to be searched will be compared with the data stored in the CAM cell and the address of the cell will be returned for the matched data. The parallel search operation in the memory is the important feature which improves the speed of search operation in CAM cells. However this parallel search operation will have its impact on the power dissipation, delay and various other parameters. This paper discusses the various low power CAM cells and analysis of its important parameters.

Keyword- XOR cell, XNOR cell __________________________________________________________________________________________________

I. INTRODUCTION Most of the memory devices store and retrieve data with respect to memory location address in specific. In Content Addressable Memory the data to be accessed is identified by its content instead of memory location. Therefore the time required to identify the data is greatly reduced. The CAM may be either binary or ternary CAM based on the values stored. The binary CAM stores either ‘0’ or ‘1’ whereas ternary CAM stores a don’t care value ‘x’ in addition and it causes a match regardless of the input bit. In a conventional CAM cell [1][3] the data will be written into the cells during the write operation (i.e. WL=1) using the bit line BL and its complement ~BL. During search operation (i.e. WL=0) the search bits are compared with the stored bits of data in each CAM cell. If the bits in the search line are same as the content of the CAM cell then the match line will be high (i.e. ML=1) or else it will be low (i.e. ML=0 The basic CAM cell operation is discussed in section II. In section III NAND, NOR and XOR cells are explained in detail. In section IV the parameters are compared and the conclusion is provided in section V.

II. OVERVIEW OF CAM The CAM cell provides two basic functions Bit storage (like RAM) and Bit comparison (Special feature in CAM). Mostly CAM cell makes use of SRAM for the purpose of bit storage. The SRAM is used because of its stability to (i.e. they hold the bits with less swapping. The content addressable memory cells are classified into NAND, NOR, XOR, XNOR, XOR using transmission gates and so on.

Fig. 1: Schematic of 4x4 CAM

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Design and Analysis of Content Addressable Memory (GRDJE / CONFERENCE / ICIET - 2016 / 083)

The bit lines and search lines are used together in many CAM cells so that the complexity of interconnection will be less. The Fig. 1 shows how the cells are interconnected to the match line, search line and bit line. During write operation it acts asbitlines whereas in search operation it acts as search lines. The sense amplifiers are feed through the match lines from each cell.

The match lines are recharged high so that they are temporarily in match state. If there is any match in the bits they remain high and incase of at least one cell mismatch match lines become low by discharging them.

III. LOW POWER CAM CELLS The WL determines the write or search operation and it is enabled using access transistors. The XOR cells are implemented using parallel connection of nMOS (i.e. NOR operation) and the XNOR makes use of series connection (NAND operation). The XOR CAM provides low match line during match condition and high during mismatch condition. The parallel connection of nMOSgates acts as NOR gate. Whenever the match lines of all the XOR CAM cells are low the NOR gate provides high at the output so that the net match line will be high. The XNOR CAM provides high match line during match condition and low during mismatch condition. The series connection of nMOS gates acts as NAND gate. Whenever the match lines of all the XOR CAM cells are high, the NAND gate provides low at the output so that the net match line will be low and the precharge line will be maintained high. A pMOS transistor with its gate grounded is used for recharging the match lines [2][4]. The various types of basic CAM cells are as follows: A. NOR Type Cell

Fig. 2: 10T NOR Type CAM Cell

The stored bit and its complementary stored bit are compared with the searchline bits SL and its complement. As shown in Fig. 2. M1, M2, M3 and M4 are used for the comparison operation which leads to pull down path as dynamic XNOR. Both M1, M3 pair and M2, M4 pair will be disconnected from ground during the match condition so that there won’t be any pulldown path. During mismatch atleast one of the path will be pulled down as a result the matchline will be low.

B. NAND Type Cell The three transistors M1, MD and ~MD are used for the comparing the stored bit with the search bit. M1 will be ON incase of match or else it will be OFF. The M1 transistor is used as the pass transistor. The nMOS connected in series will provide the NAND [3] operation. If every cell has high ML then the match is obtained.

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Design and Analysis of Content Addressable Memory (GRDJE / CONFERENCE / ICIET - 2016 / 083)

Fig. 3: 9T NAND Type CAM Cell

C. XOR Type Cell

Fig. 4: XOR Type CAM Cell.

Here only two transistors M1 and M2 are used to obtain the comparison between the stored bits and bit to be searched.

When match is obtained the output of the comparator circuit is low and for mismatch the output will be high. During mismatch M1 and M2 will conduct to provide high output. The outputs of the XOR [3][4] comparator CAM as shown in Fig. 4 are connected to nMOS in parallel along with the prechargedmatchlines. The XOR CAM cell has important application in networks for packet forwarding.

D. XOR Using Transmission Gates The operation is same as the XOR type CAM where the transmission gates used for the comparison operation instead of pass transistors. The entire voltage range can be made to pass using transmission gates. The switching voltage determines the transition resistance and the voltage will not loss. If the stored bit value is 0 then TG1 will be ON and for the bit value of 1 then TG2 will be ON. If the match is found then the out from anyone of the transmission gate will be high.

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Design and Analysis of Content Addressable Memory (GRDJE / CONFERENCE / ICIET - 2016 / 083)

Fig. 5: XOR Using Transmission Gates

E. XNOR Type Cell

Fig. 6: XNOR Type CAM Cell

The XNOR gate operation similar to the operation of the XOR gate but reverse in its function. During the search operation the data in the bitline will be compared with the stored bit q. If both q and the value in the bitline are 0 then the nMOS connected to the ~bl will be ON and for 1 the nMOS connected to bl will be ON and the output will be high for match. Incase of mismatch both the transistor M2 and M8 will be off and the matchline will be low.

IV. EXPERIMENTAL RESULTS The power dissipation between various CAM cells is shown in Table I. The low power circuits have high demand in today’s industries. The delay is the important parameter while designing the circuits. The low power dissipating circuits will dissipate less heat. The extended delay may cause incorrect values at the output so the detailed delay analysis will provide the better information before designing the circuit. The total delays for the various CAM cells are shown in Table II. Type of CAM Cell Power dissipation NAND cell 85.0321 µw NOR Cell 96.4578 µw XOR Cell 111.0318 µw XOR using Transmission Gates 54.9598 µw XNOR Cell 21.7649 µw Table 1: Power comparison between various CAM cells

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Design and Analysis of Content Addressable Memory (GRDJE / CONFERENCE / ICIET - 2016 / 083)

Type of CAM Cell Delay NAND cell 98.127ns NOR Cell 54.734ns XOR Cell 24.84ns XOR using Transmission Gates 67.69ns XNOR Cell 74.258us Table 2: Delay parameter of various CAM cells

V. CONCLUSION CAM is defined as a functional memory with a large amount of bits stored that simultaneously compares the input search bits with the stored bits. The speed at which the data to be searched is also more. From the experimental results it is clear that XNOR cell have less power dissipation when compared with other CAM cells. The delay is less in XOR cell so that they are often used in router memories. The power estimation is made using EDA tool with 180nm technology and the operating voltage is 1.8V.

REFERENCES [1] Byung-Do Yang and Lee-Sup Kim, “A Low-Power CAM Using Pulsed neither NAND–NOR Match-Line and ChargeRecycling Search-Line Driver,” IEEE journal of solid-state circuits, vol. 40, no. 8, pp. 1736 – 1744, August 2005.

[2] Jian-weizhang, Yi-zheng ye, and bin-da liu, “a current-recycling technique for shadow-match-line sensing in contentaddressable memories,” IEEE transactions on very large scale integration (vlsi) systems, vol. 16, no. 6, pp. 677 - 682, June 2008.

[3] Kostas pagiamtzis, “Content Addressable Memory circuits and architectures: A tutorial and survey”, IEEE journal of solid state circuits, Vol 41, No. 3, March 2006.

[4] Yen-Jen Chang and Tung-Chi Wu, “Master–Slave Match Line Design for Low-Power Content-Addressable Memory” IEEE Transactions On Very Large Scale Integration (VLSI) Systems, pp. 1-10 August 2014.

[5] L. Frontini, S. Shojaii , A. Stabile , V. Liberali, “A New XOR based Content addressable memory Architecture”, IEEE International Conference on Electronics Circuits and Systems, pp. 701-703, December 2012.

[6] Kuo-Hsing Cheng, Chia-Hung Wei, Yu-Wen Chen, “Design of Low power content addressable memory cell”, IEEE symposium on Circuits and Systems, pp. 1447 - 1450 Vol. 3, December 2003.

[7] Sreenivasa Rao, B. S. N. S. P. Kumar, S. Raghavendra, V. Malleswara Rao “Design and Implementation of CAM architecture memory cell” Trends in Network and Communication, Vol. 197, pp 159-166, October 2011.

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