BISR SCHEME USING BENCH MARK TESTING SEQUENTIAL CIRCUIT S27

GRD Journals | Global Research and Development Journal for Engineering | International Conference on Innovations in Engineering and Technology (ICIET) - 2016 | July 2016

e-ISSN: 2455-5703

BISR Scheme using Bench Mark Testing Sequential Circuit S27 1R.

N. Nivethitha 2Dr. A. Kaleel Rahuman 1 PG Scholar 2Assistant Professor 1,2 Department of Electronics and Communication Engineering 1,2 PSNA College Of Engineering and Technology, Dindigul Abstract In this bench mark testing sequential circuit S27 is tested by using Built in Self Repair concept. This paper describes an on-chip test generation method for functional broadside tests. The hardware is based on the application of primary input sequences initial from a well-known reachable state, therefore using the circuit to produce additional reachable states. Random primary enter sequences are changed to avoid repeated synchronization and thus differed various sets of reachable states. Functional broadside tests are two-pattern scan based tests that avoid over testing by ensuring a circuit that traverses only reachable states in the functional clock cycles for a check. This consist of the input vectors and the equivalent responses. They check the proper operation of a verified design by testing the internal chip nodes. This test is useful to cover a very high percentage of modeled faults in logic circuits and their generation is the main topic of this method. Often, functional vectors are understood as verification vectors, these are used to verify whether the hardware actually matches its specification. Though, in the ATE world, any one vectors applied are understood to be functional fault coverage vectors applied during developing test, then the fault coverage area easily detected. This paper shows S27 circuit is used in Multiplier Circuit for Testing Application and it is done

by Verilog Programming and simulated by Modalism 6.5version and Synthesis by Xilinx Tool Keyword- BISR, BIST, LFSR, S27 __________________________________________________________________________________________________

I. INTRODUCTION Built in self-Repair concept was proposed by bench mark testing sequential circuit S27.It can be describes the on chip test generation method for functional broadside test .Functional vectors are understood as verification vectors. As circuits approach the limits of Moore’s law, and as power considerations have placed a limit on increases in clock frequency, stacking bare dies to form a 3-D die-stack has been proposed as one method that will allow significant increases in system performance to continue.

Performance gains are expected to arise primarily from the fact that the routes between dies in a stack are much shorter than routes from chip to chip across a board or routes from one end of a chip to another. Unfortunately, high volume manufacturing has proven difficult. One of the main problems preventing the large-scale manufacturing of 3-D integrated circuits is the difficulty in testing dies and obtaining high yields. The insertion of through-silicon vias (TSVs) may damage the die during the “drill and fill” process or when the silicon is ground away to expose the TSV so that it can be “micro bumped.” The TSVs themselves are difficult to probe without damaging them making testing of individual dies difficult as well. Fortunately, a 3-D stack also provides new opportunities for repair. Specifically, if a die containing programmable logic is included in the stack, it may be harnessed to bypass defective components of other dies. Many levels of granularity for repair are possible from replacing the functionality of an entire die to replacing a single pipeline stage or functional unit. Repair is particularly well matched to the repair of functional units in out-of-order processors because such processors are already designed to naturally handle multiple functional units with different latencies. In some cases, repair is mandatory when the only copy of a critical component is found to be defective. However, even when the lack of a defective component only causes performance degradation, replacement of the defective functionality may still be desirable. This paper extends the concept of BISR to the digital logic in 3-D stacks. We utilize two separate dies in the 3-D stack: the original circuit implemented in an ASIC process and a separate FPGA die that can be programmed when needed to create spare functional modules. This approach harnesses the advantages provided by 3-D architectures including potentially large numbers of TSV connections and short distances between dies to increase the flexibility and improve the performance of repair. To the best of our knowledge, we are the first to propose such an approach. Similarly, multiplexers must be inserted between the outputs of the partition being repaired and the downstream part of the circuit to allow the rest of the circuitry to be driven by the FPGA instead of by the defective partition. In this figure, each of the inputs to the partition fan out not only to the by passable partition, but to a tri-stated buffer (or possibly a series of buffers) that is capable of driving the TSV as well.

The driving buffers should be sized so as to minimize the load and delay seen by the circuit. Each of these TSVs is connected to the FPGA such that it becomes an input to the FPGA. The FPGA itself will need to be programmed to realize the functionality of the partition using those inputs. The outputs of the FPGA-implemented module will then travel through other

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BISR Scheme using Bench Mark Testing Sequential Circuit S27 (GRDJE / CONFERENCE / ICIET - 2016 / 082)

pre-defined TSVs until they reach the level of the ASIC being repaired. MUX are used to select the values sent by the FPGA if the circuit is in repair mode as indicated by the value of the select line on the MUX.

Fig. 1: Schematic View Of Through Silicon via (TSV) Module

II. RELATED WORK One approach has been to use reconfigurable modules in FPGAs, such as logic blocks or routing resources, to replace the defective modules. Another approach is to use spare functional units on FPGA, such as spare ALUs. These approaches implement both the original and spare modules on a single FPGA. FPGAs and ASIC hardware may also be implemented on the same die in a SoC, to provide capabilities for modifying the design later when design errors or specifications (such as communication standards) change in fig 1.2 On-chip DRAM main memory and analyse the performance, power, and temperature trade-offs of 3D CMPs. Runtime optimization policy to maximize performance while maintaining power and thermal constraints. 3D stacking main memory architecture for CMPs behaviour and selects among low-power and turbo operating modes accordingly. Under the fixed voltagefrequency (V-F), the IPC of runtime optimization policy improves a 16-core 3D CMP with stacked DRAM compared to a statically optimized 3D system. The energy-delay product (EDP) is reduced compared to a 3D system managed by a temperature triggered dynamic VF scaling policy. Complex interplay of performance, energy, and temperature for 3D CMPs with stacked DRAM main memories.

Fig. 2: 3D stacking main memory architecture for CMPs

These functional vectors are used to verify whether the circuit actually matches its specification. Depending upon this the fault coverage area easily detected.

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BISR Scheme using Bench Mark Testing Sequential Circuit S27 (GRDJE / CONFERENCE / ICIET - 2016 / 082)

Fig. 3: Built in self-Repair scheme for s27

Built in self-repair concept for testing sequential circuit s27 was treated as a bench mark circuit.in proposed work 12 bit LFSR S27 was compared to specification of functional vectors .then the fault coverage area easily detected. This can be describes the on chip test generation concept for functional broadside test.Testing sequential circuits substantially more complex to large circuits.

Faulty circuit can be detected by the help of original circuit then the process can be done by “comparator�.

Logic Gates are taken at primary input combination in testing sequential circuit.s27 circuit have three scan circuits and the inputs are noted in the functional vectors.S_A_0 Faults generates at logic gates.

Linear Feedback shift register values initially at given to primary input of the built in self-repair circuit. We note the unspecified in the two unscanned state variable this implies that can be used as a scan in state of this test and the first two patterns of the test can be omitted. Suppose that is specified to functions and broadside vectors. In general to obtain the highest time unit such that scanned state variables for a full-scan circuit. This is due to the fact that all the states are fully specified.

Fig. 4: Self Repair Circuit

Self-repair circuit shows the BIST controller, and the comparator. For combinational circuits, the greedy heuristic performed better (and faster) than the heuristic with a proven performance guarantee.

This shows that in practice, approximation algorithms with performance guarantee may not be the best heuristics.

Experimental results using repetition of vectors showed that if time is not an important Criterion as compared to power dissipation, considerable savings can be obtained by repeating some of the test vectors. For simplicity, all the other clock cycles were referred to as scan shift cycles. This paper described a test generation procedure that limits the switching activity during scan shift cycles by using an increasing upper bound during test generation to find the lowest value for which tests exist. The procedure also preferred tests that have high switching activity during fast functional capture cycles.

III. PROPOSE WORK Linear Feedback shift register (LFSR) can be treated as a 12 bit circuit.LFSR is one of the best Testing circuit. The goal of this brief is to derive skewed-load test cubes from functional broadside tests, and use them for the generation of low-power skewed-

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BISR Scheme using Bench Mark Testing Sequential Circuit S27 (GRDJE / CONFERENCE / ICIET - 2016 / 082)

load tests. This procedure will benefit from the advantages listed above when generating a low-power skewed-load test set. The procedure can also be extended to generate a mixed low-power test set that consists of both broadside and skewed-load tests.

Fig. 5: LFSR 12 Bit circuit

The patterns of signal transitions are important for the following reasons: 1) The transition fault coverage achievable by functional broadside tests is lower than the transition fault coverage achievable by arbitrary broadside tests. Therefore, nonfunctional broadside tests are necessary for achieving the highest possible transition fault coverage. A test generation procedure should prefer an arbitrary broadside test whose pattern of signal transitions matches perfectly that of a functional broadside test. When it cannot find such a test, it should search for a test with the smallest possible deviation from such a pattern. In this way, the procedure can minimize the deviations from functional power dissipation.

2) Two tests that have the same power dissipation, where power dissipation is represented by a single number, can have very different patterns of signal transitions. Thus, minimizing the power dissipation as a single number does not necessarily lead to patterns of signal transitions that match those possible during functional operation. This can result in power dissipation that the circuit is not designed for even though the single number representing the power dissipation is acceptable. Only the power dissipation during the second, fast functional capture cycles of broadside tests is considered in this paper. In addition, the complete circuit is considered for the computation of power dissipation or the patterns of signal transitions. The paper does not address the case where very low-power test sets are needed. Instead, it assumes that it is sufficient to ensure that the power dissipation (represented by the pattern of signal transitions) would match that possible during functional operation as well as possible.S27 bench mark circuit is the standard sequential circuit. Here we are used s27 bench mark circuit for as a testing circuit. Apply the test vectors as input to the s27 bench mark sequential circuit.

Fig. 6: Benchmark Testing Circuit of S27

Generation for functional and pseudo functional scan based tests were generate the external tester .under the test generation of on chip vectors noted that the delay fault coverage achievable using functional broadside tests. Bench mark sequential circuit is compare to faulty s27 circuit depends on the specification functional vectors .that can be used to detect the faults on the circuit easily. Then the presence of delay including defects is causing increasing concern in the semiconductor industry today.

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BISR Scheme using Bench Mark Testing Sequential Circuit S27 (GRDJE / CONFERENCE / ICIET - 2016 / 082)

Fig. 7: S27 Faulty circuit

IV. RESULTS A. Standard Sequential Testing Circuit S27

Fig. 8:

Output waveform of the standard MUX DFF. In this Ckt Logic, ScanIn, Clk, Rst, Scan are the given inputs and the outputs are ScanOut. Here normal operation means give a input scan=0,scan operation means give a input scan=1. MUXDFF. ScanRepair, TestRepair, Clk, Rst are given inputs and the outputs are scan out here the normal operation means scan=1,test mode=1,repair operation means scan=0,test mode=1.

Pseudo random test generation has the primary goals to develop a battery of statistical tests to detect nonrandom in binary sequence Algorithmic test generation provide input conditions to activate a fault and to sensitize the primary Faulty sequential testing circuits27 Compare all the specifications then detect the fault coverage area easily detected by this BISR scheme. Then the built in self-repair using bench mark circuit of sequential circuit s27 was verified and faulty area can be detected easily.

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BISR Scheme using Bench Mark Testing Sequential Circuit S27 (GRDJE / CONFERENCE / ICIET - 2016 / 082)

Fig. 9:

Fig. 10:

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BISR Scheme using Bench Mark Testing Sequential Circuit S27 (GRDJE / CONFERENCE / ICIET - 2016 / 082)

Fig. 11:

RTL Schematic view of the functions represented the internal blocks and specifications.

V. CONCLUSION On chip test generation has the built in self-repair a bench mark sequential testing circuits S27 has the merits like reduces the test data volume and facilitates at speed test application then it achieves high fault coverage.

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