FPGA Implementation Of Content Addressable Memory

GRD Journals | Global Research and Development Journal for Engineering | International Conference on Innovations in Engineering and Technology (ICIET) - 2016 | July 2016

e-ISSN: 2455-5703

FPGA Implementation of Content Addressable Memory 1S.

Gokila 2R. Mythili 3S. Chandra Kala 1 Department of Information and Communication Engineering 2,3Electrical and Electronics Engineering 1,2,3 KIT- KalaignarKarunanidhi Institute of Technology, Coimbatore-641 402 Abstract To reduce the power dissipation in circuits, the reversible logic design is implemented. Reversible logic design is one of the main low power techniques. In the proposed design the address decoder is designed using basic reversible logic gates Fredkin gate and Peres gate. The encoder is designed using Fredkin and Feynman gate. In the use of Peres gate in proposed design reduce the quantum cost and power dissipation of the decoder. The Content Addressable memory architecture will be realized using FPGA Keyword- Decoder, Fredkin gate, FPGA, Peres gate, Reversible logic __________________________________________________________________________________________________

I. INTRODUCTION Reversible logic design is one of the main low power techniques. It has less heat dissipation. The reversible logic circuit has equal number of input and output. A reversible gate has equal input and output in order to have one to one mapping, also the inputs of a reversible gate can be uniquely determined from its outputs. In a reversible gate fan out of every signal involving primary inputs must be one. Garbage output is one of the most important features of a reversible gate. Every gate output that is not used as input to other gate or as a primary output is called garbage output. Each reversible gate is associated with a cost called quantum cost. The quantum cost of a reversible gate is the number of 2×2 reversible gates or quantum logic gates required for design.

When a small bit of information erases in computational system, ln2 × kT energy will be dissipate, where K is denoted as Boltzmann's constant and T is denoted as the temperature. When room temperature T = 300 Kelvin’s, the dissipation is 2.9 x 10^-21 joules. This energy is equal to single air molecule kinetic energy at room temperature. While computer perform a logic operation every time it will erase a bit of information. This is called "irreversible". Here very inefficiently erasure is performing for each bit erased more than kT is dissipated. If we are to continue the revolution in computer hardware performance we must continue to reduce the energy dissipated by each logic operation.

This paper aims at presenting an address decoder design using reversible logic elements an alternate circuit for minimize the consumption of power in the address decoder of memory.

The rest of the paper is deal as follows. Section II discusses about the reversible logic gates. Section III discusses about the conventional decoder design. Section IV discusses about the address decoder design using reversible logic design. Section V discusses about the results of the proposed reversible design. Section VI concludes the paper.

II. BASIC REVERSIBLE LOGIC GATES At present many number of reversible logic gates exists. An important optimization parameter of reversible logic gate is quantum cost[11].The 1x1 reversible gate quantum cost is assumed to be zero and a 2×2 reversible logic gate quantum cost is unity.

A. Feynman Gate The inputs of Feynman gate are A, B and the outputs are P, Q. The outputs are derived as P=A and Q=AXOR B. It is also called as controlled NOT gate. The Quantum cost is 1.

Fig. 1: Block diagram of Feynman gate

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FPGA Implementation of Content Addressable Memory (GRDJE / CONFERENCE / ICIET - 2016 / 050)

A 0 0 1 1

B P 0 0 1 0 0 1 1 1 Table 1: Truth table of Feynman gate

Q 0 1 1 0

B. Fredkin Gate The inputs of Fredkin gate are A, B, C and the outputs are P, Q, R. The outputs are derived as P=A, Q= ((NOT A) AND B) XOR (A AND C) and R=((NOT A) AND C) XOR (A AND B).The Quantum cost is 5.When input value A=0 then P=A,Q=B,R=C. When input signal value A=1 then P=A,Q=C,R=B.

Fig. 2: Block diagram of Fredkin gate

C. Peres Gate The inputs of Peres gate are A, B, C and outputs are P, Q, R. The outputs are derived as P=A, Q=A XOR B and R=( A AND B)XOR C. The Quantum cost is 4.

Fig. 3: Block diagram of Peres gate A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C P Q 0 0 0 1 0 0 0 0 1 1 0 1 0 1 1 1 1 1 0 1 0 1 1 0 Table 2: Truth table of Peres gate

R 0 1 0 1 0 1 1 0

D. Toffoli Gate The input of Toffoli gate is A, B, C and the outputs are P, Q, R. The outputs are derived as P=A, Q=B and R= (A AND B) XOR C. The Quantum cost is 5.

Fig. 4: Block diagram of Toffoli gate

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FPGA Implementation of Content Addressable Memory (GRDJE / CONFERENCE / ICIET - 2016 / 050)

A 0 0 0 0 1 1 1 1

B C P Q 0 0 0 0 0 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 0 1 1 1 1 0 1 0 1 1 1 1 Table 3: Truth table of Toffoli gate

R 0 1 0 1 0 0 1 1

III. CONVENTIONAL DECODER AND EXISTING DECODER A. Conventional Decoder The input n data value given to the decoder and 2n data value taken as an output of the decoder. A decoder is a device which does the reverse operation of an encoder, undoing the encoding so that the original information can be retrieved. The same method used to encode is usually just reversed in order to decode. It is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. Decoders are the collection of logic gates fixed up in specific connections. Thus, when an input combination changes, two outputs will change. Let, there are n inputs, so number of outputs will be 2n.

Fig. 5: Representation of 2Ă—4 Decoder

In case the n bit coded information has unused bit combinations, the decoder may have less than 2n outputs. The input to a decoder is parallel binary number and it is used to detect the presence of a particular binary number at the input. The output indicates presence or absence of specific number at the decoder input. For any input combination only one of the outputs is low and all others are high. The low value at the output represents the state of the input.

B. Conventional Encoder A Digital Encoder more commonly called a Binary Encoder takes all its data inputs one at a time and then converts them into a single encoded output. So we can say that a binary encoder is a multi-input combinational logic circuit that converts the logic level 1 data at its inputs into an equivalent binary code at its output. Generally, digital encoders produce outputs of 2-bit, 3-bit or 4-bit codes depending upon the number of data input lines. An n-bit binary encoder has 2n input lines and n-bit output lines with common types that include 4-to-2, 8-to-3 and 16-to-4 line configurations.

Fig. 6: Representation of 4Ă—2 Encoder

The output lines of a digital encoder generate the binary equivalent of the input line whose value is equal to 1 and are available to encode either a decimal or hexadecimal input pattern to typically a binary or BCD (binary coded decimal) output code.

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FPGA Implementation of Content Addressable Memory (GRDJE / CONFERENCE / ICIET - 2016 / 050)

IV. PROPOSED DESIGN A. Proposed Reversible 2×4 Decoder The proposed reversible decoder consists of 2 input,4 output. It has a 4 constant inputs and 2 garbage outputs.Where in the proposed system 2 fredkin gate and 1 peres gate is used.the quantum cost of peres gate is 4 and fredkin gate is 5.

Fig. 7: Proposed 2×4 Decoder

The quantum cost of the proposed design is 14.The quantum cost of the peres gate is less compare to fredkin gate. In reversible decoder in1, in2 are two input signals and o0, o1, o2, o3 are four outputs. Four constant inputs are three inputs logic 0 .Constant one input logic 1 is provided to the circuit and g1, g2 are two garbage outputs. Input1 is given to the Peres gate and input2 is given to Fredkin gate. The output of Fredkin gates depends on the Peres gate output and input 2. Fredkin gates output are the decoded output signal of the given input signals.

B. Proposed Reversible 4×2 Encoder In 4 ×2 encoder has been proposed using Fredkin gate and Feynman gate.

Fig. 8: Proposed 4×2Encoder

In reversible encoder A, B, C, D are four input signals and Y0, Y1 are two outputs. The circuit have G1, G2 are two garbage outputs. Where Feynman gate is a 2×2 gate it has a quantum cost as 1.the quantum cost of 3×3 fredkin gate is 5.the total quantum cost of proposed reversible 4×2 encoder is 8.

V. RESULT AND DISCUSSION The simulation wave form is analysed and the power is obtained. The power calculation is taken by the simulation waveform.

The power requirement of the proposed reversible decoder is 0.321 microwatts. Compare to the conventional design the power consumption is minimized. The simulation result of the proposed design of address decoder is given below.

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FPGA Implementation of Content Addressable Memory (GRDJE / CONFERENCE / ICIET - 2016 / 050)

Fig. 9: Timing diagram

The power comparison table is given below.

PROPOSED DESIGN 15.906 0.321 2×4 DECODER MICRO WATTS MICROWATTS Table 4: Power comparison of decoder TYPE

CONVENTIONAL DESIGN

The power requirement of the proposed reversible encoder is 0.187 microwatts. Compare to the conventional design the power consumption is minimized. The simulation result of the proposed design of address encoder is given below.

Fig. 10: Timing diagram

The power comparison table is given below.

TYPE 4×2 ENCODER

CONVENTIONAL PROPOSED REVERSIBLE 6.765 MICRO WATTS 0.187 MICRO WATTS Table 5: Power comparison of encoder

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