Design Of 8-Bit Full Adder Based On Spin Transfer Torque Magnetic Tunnel Junction

GRD Journals | Global Research and Development Journal for Engineering | International Conference on Innovations in Engineering and Technology (ICIET) - 2016 | July 2016

e-ISSN: 2455-5703

Design of 8-Bit Full Adder based on Spin Transfer Torque Magnetic Tunnel Junction 1K.

Brindha 2R. Christy 3S. Indhu 4J. Madhubala 5P. Sathyaraj 1,2,3,4,5 Assistant Professor 1,2,3,4,5 Department of Electrical Engineering 1,2,3,4,5 Arasu Engineering College, Kumbakonam Abstract

In conventional technology, CMOS logic circuits are used. This technology suffer from high power issues due to long traffic delay and leakage current. After that, Hybrid logic-in memory architecture using Magnetic Tunnel Junction(MTJ) to overcome these limitations. Magnetic Tunnel junction is a non-volatile device to achieve high access speed and infinite endurance. Recently, 1-bit non-volatile full adder using MTJ have been proposed to build low-power highdensity arithmetic/logic unit for processor. However, this method has partial non-volatile property because MTJ is used as one of their operands. For this purpose, extending 1-bit to multi bit structure offers full non-volatility. Synchronous 8-bit non-volatile full adder presented in this paper, the input signals are stored in MTJ instead of CMOS register. MTJ with CMOS logic circuits three possible structures are proposed with respect to different location of NV data. The design is simulated in 180nm CMOS technology using cadence EDA tool.

Keyword- 3-D integration, 8-bit flip-flop, 8-bit full adder, full non-volatility, STT-MTJ __________________________________________________________________________________________________

I. INTRODUCTION A CMOS technology for mainstream logic circuits faces severe challenges due to both increasing static and dynamic power, especially as technology node shrinks below 45nm. Non-volatile (NV) devices such as magnetic tunnel junction (MTJ) to overcome these power issues. MTJ as one of the NV device thanks to its high access speed and infinite endurance. MTJ is made of a thin insulating oxide barrier and its sandwiched between two ferromagnetic (FM) layers.

The spin direction in one FM layer is fixed, whereas in the other FM layer is free to change. Due to tunnel magnetoresistance effect, MTJ is able to present low resistance or high resistance by changing the relative magnetization orientation of two FM layers. i.e., parallel (P) or Anti-parallel (AP). Spin transfer torque (STT) is a promising mechanism to switch the magnetization direction of the free layer by injecting a bidirectional current through the stack. STT provides simpler switching mechanism and low power consumption.

Hybrid NV logic-in-memory architecture, where NV memory elements are distributed over a logic-circuit plane, is expected to ensure ultra-low power and ultra-short interconnection delay. The implemented NV memory elements should have the capabilities of short access time (10 ns) , infinite endurance, small dimensions and resistance value with CMOS transistors. STT based MTJ is an available candidate that can satisfy all the requirements and allows one to design hybrid V logic-in-memory circuits with high performances. Based on the logic-in-memory architecture, 1-bit non-volatile full-adders (NV-FA) have been investigated to build low-power high-density arithmetic/logic unit for processors.

The 3-input (A,B, and Ci)NV-FAspresented in are partially non-volatile. In this paper , we focus on synchronous multi-bit fully non-volatile FA design, whose input signals are all stored in non-volatile state. Simulations are then performed to validate their functionalities and confirmed their advantages in low power consumption, high frequency and small area by using an industrial CMOS 28nm design kit and a 0 STT-MTJ compact model.

II. DETAILED DESIGN OF SYNCHRONOUS 8-BIT NV-FAS A compact model was proposed in based on the PMA CoFeB/MgO/CoFeB STT-MTJ. This model is programmed in Verilog-A language, integrating physical static, dynamic, and stochastic behaviors and experimental measurements. It provides a feasible way to perform hybrid electrical simulations through integrating MTJ signals into CMOS circuits.

In this section, three synchronous 8-bit V-FAs are first proposed with respect to the locations of NV data. Here, A and B are stored inputs, Ci and Co are carry-in and carry-out respectively. The basic 8-bit NV-FA structure is composed of one halfadder (HA) and seven FAs in series, performing addition operation of two 8-bit words A7-A0 and B7-B0. Inputs data A7-A0 and

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Design of 8-Bit Full Adder based on Spin Transfer Torque Magnetic Tunnel Junction (GRDJE / CONFERENCE / ICIET - 2016 / 079)

B7-B0 are all stored in V states to realize full non-volatility. The final 9-bit output includes eight SUM bits (SUM7-SUM0) and one CARRY bit (Cout).

The basic components of the 8-bit NV-FAs and their principles of operation will be detailed in the following subsections.

A. 1-bit CMOS HA and FA Circuits As the basic addition cells, traditional 1-bit CMOS –only HA and FA from the standard cell library of STM microelectronics 28m design kit. “A” and“B” are generated by two NV-FFs and”Ci” comes from the output “C0” of the lower stage adder. For the purpose of synchronizing the outputs “SUM” and ‘C0” with clock signal “CLK”, registers are added onto the outputs of each CMOS-only adder.

B. 1-bit NV-FF Circuit NV-FF is mainly composed of two parts read-circuitand write-circuit part. It is used to store and generate input data A7-A0 and B7-B0.

For the read part, pre-charge sense amplifier (PCSA) is employed for the logic evaluation due to its ultra-low power, fast speed and high reliability. It is mainly composed of two pre-charge transistor ( MP0,3), a discharge transistor (MN4) and a pair of inverters ( MN0,1 and MP1,2) . A couple of STT-MTJs that are always in complementary stages are integrated in the circuit to store a binary non-volatile data(logic “1” or logic “0”). Here, we use complementary data storage in order to achieve high computing speed and minimize the sensitivity to the process variations. Both MTJs are connected in series with a separate transistor (MN2 or MN3) dedicated to separate them with the read circuit when performing writing operation. Two inverters act as output buffers and a dynamic register is applied for data transition.

The 4T writing circuit part, which consist of two NMOS and two PMOS transistors. Is employed to generate a bidirectional current and switch the magnetic configurations of MTJs. Data stored in MTJ is programmed by controlling external signals :WE”, “CLK”, and “DATA” through a writing control circuit. “WE” AND “CLK” are activation signals for writing operation, while “Data” controls the direction of writing current. I the case of storing “0” into the corresponding MTJs, “Data” should be set to “0” and the transistors MP4 and MN6 are turned on while the transistors MP5 are turned off. As MTJs are serially connected with a common central point, a current will flow from the top of MTJ0 to the top of MTJ1. “CLK” is turned off during the above writing operation, thereby isolating the MTJs from the read-circuit part. To write logic “1”, a reversed current is generated by setting “Data” to “1” and thus transistors MP5 and will be open.

Reading operation of the 1-bit NV-FF includes two phase: pre charge phase and evaluation phase. During the precharge phase (“CLK”=’0’), PMOS transistors MP0 and MP3 are turned on and they charge the inputs of the two inverters to VDD, hence the two outputs (Qm and Qm’)are pulled down to gnd. During the same phase, writing current source can be enabled to program the data stored in MTJs by setting “WE” to “1”. During the evaluation phase(“CLK”]=”1”), writing current source is disabled and MN4 is open to drive reading currents on both sides flowing to the ground. A differential current will be created because of the resistance difference between MTJ0 and MTJ1, and one output will be pulled to VDD while the other one will be pulled down to the ground. Two complementary outputs, which correspond to two opposite logic values represented by two branches, can be then obtained.

C. 1-bit NV-HA and NV-FA circuits Based on the hybrid non-volatile logic-in memory architecture 1-bit NV-HA and NV-FA are employed to perform addition operation. They are both composed of a SUM-circuit part and a CARRY-circuit part, whose reading and writing circuits are the as those of the 1-bit FF presented in the previous section. Simple PCSA-based reading circuit, non-volatile adders are possible to consume less read energy by reducing the number of current path from VDD to GND when compared with the CMOS onlyadders.

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Design of 8-Bit Full Adder based on Spin Transfer Torque Magnetic Tunnel Junction (GRDJE / CONFERENCE / ICIET - 2016 / 079)

Fig. 1: Schematic of CMOS-only full adder

Fig. 2: Waveform of CMOS-only full adder

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Design of 8-Bit Full Adder based on Spin Transfer Torque Magnetic Tunnel Junction (GRDJE / CONFERENCE / ICIET - 2016 / 079)

D. 8-bit NV-FF circuit In this circuit PCSA-based sensing circuit is shared by sixteen MTJs. In such configuration, an MTJ is selected when the connected NMOS transistor is open. This is controlled by three external signals “S2S1S0” through a 3 to 8 decoder. During a sensing operation, only one out of eight NMOS transistor in the left sub-branch and another in the right sub-branch are turned on to connect the upper PCSA part with the addressed MTJs. As a result, 1-bit NV data stored in couple of MTJs will be read and then transferred into the input of a NV adder.

The size of four writing transistors (MN5-MN6 and MP4-MP5) should bf largely increased. In order to overcome this problem, four more writing transistors and one more discharge NMOS transistors are added to separate the write current-path into two.

Fig. 3: Transient simulation of CMOS-only half adder

III. FUNCTIONAL SIMULATION By using the compact STT-MYJ model and a 180nm STM microelectronics design kit, transient simulations are performed on spectre simulator of cadence to validate the functionalities of these proposed 8-bit NV-FAs. Periodic 1.0v-peak-to-peak voltage signals are applied to “CLK” in all the simulations.

In this simulation of 1-bit NV-FF, two MTJs (MTJ0 AND MTJ1) are initialized at logic “1” and “0”, respectively. Four transistors in the writing circuit are set as W=1m in order to get ensure large writing circuit and reduce the switching time, while keeping relatively small area overhead. All the other CMOS transistors are kept in minimal size. During the first cycle, write enable signal “WE” is initialized at logic “0” and no writing current passes through MTJs. NV data stored in MTJs is and propagated to “Qm” node during the evaluation phase (E) with delay as low as 132ps, duo to the dynamic sensing approach of PCSA. This data is then propagated to “output” ode of the slave registers when “CLK” meets a falling edge. During the precharge phase (P) of the second cycle, writing operation is activated (“WE” =”1”) and the configuration of MTJs1 in the left subbranch is switched from anti-parallel to parallel with a short delay of 6.46ns.

S.NO HALF ADDER FULL ADDER

CONVENTIONAL PROPOSED POWER DELAY POWER DELAY 2.55mW 6.439ps 1.35mW 4.593ps 5mW 49.560ps 0.00459mW 26.05ps Table 1:

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Design of 8-Bit Full Adder based on Spin Transfer Torque Magnetic Tunnel Junction (GRDJE / CONFERENCE / ICIET - 2016 / 079)

Fig. 4: Schematic of 8-bit non-volatile full adder

IV. CONCLUSION Emerging hybrid STT-MTJ/CMOS logic circuits such as NV-FA has been investigated to address the power issue of the traditional CMOS circuits. However, the published NV-FAs are partially volatile in order to keep high operation frequency. I this paper, three possible synchronous 8-bit NV-FA structures were proposed according to the location of non- volatile data and system requirements. All their input data are stored in non- volatile state instead of charge storage in CMOS register. They extend the 1-bit FA to multi-bit case and realize full non-volatility to promise nearly zero stand- by power and instant ON/OFF. By using a commercial CMOS design kit and a precise STT-MTJ compact model, functionalities, performance and reliabilities are investigated at 180nm technology node. Based on these synchronous 8-bit non-volatile FA, more complex logic circuits could be built to create true normally-off system according to different application requirements.

REFERENCES [1] Deng.E.Y, Jan 2015 “Design optimization and analysis of multicontext STT-MTJ/CMOS logic circuits.” IEEE Trans.Nanotechnol., [2] Hariyama.M. 2008 “Non-volatile multicontext FPGAs using hybrid multiple valued/binary context switching signal.”

[3] Trinh.H.P. Jun 2013 “Magnetic adder based on racetrack memory.” IEEE Trans., [4] Zhao,W.S. 2009 “High speed, high stability and low power sensing amplifier for MTJ/CMOS hybrid logic circuit.” IEEE Trans., [5] Zhang.Y.March 2012 “Compact modeling of perpendicular/ anisotrophy CoFeB/MgO magnetic tunnel junction.” IEEE Trans., [6] Zhang.Y. july 2013 “Electrical modeling of stochastic spin transfer torque writing in magnetic tunnel junction for memory and logic application.” IEEE Trans., [7] Zhao.W.S Oct 2009 “Spin transfer torque(STT)-MRAM based run time reconfiguration FPGA circuit.”

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