CMOS VLSI ARCHITECTURE OF LOW POWER LEVEL SHIFTER

GRD Journals | Global Research and Development Journal for Engineering | International Conference on Innovations in Engineering and Technology (ICIET) - 2016 | July 2016

e-ISSN: 2455-5703

CMOS VLSI Architecture of Low Power Level Shifter 1A.Vidhyalakshmi 2S.Sobana 1

1

PG Scholar 2Assistant Professor Department of VLSI Design 2Department of Electronics and Communication Engineering 1,2 PSNA College Of Engineering and Technology, Dindigul Abstract

Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter implemented in a flip-flop to minimize energy, delay, and area penalties due to level conversion. A novel level-up shifter with dual supply voltage is proposed. The proposed design significantly reduces the short circuit current in conventional cross-coupled topology, improving the transient power consumption. Compared with the bootstrapping technique, the proposed circuit consumes significantly less area, making it more practical for ICs with a large number of supply voltages. TINA tool has been used to show the existing and proposed results.

Keyword- Dual Power Supply, Short Circuit Current __________________________________________________________________________________________________

I. INTRODUCTION Ultra-low power consumption often comes at the price of reduced performance for energy conscious electronics – particularly reconfigurable circuits. Operating devices at ultra-low voltage levels provides the lowest energy per operation, but can penalize the frequency of operation by several orders of magnitude. A more optimized approach is to segregate the logic based on performance requirements and use multiple voltage levels to supply separate voltage islands in an integrated circuit. The concept can be extended such that the low performance circuits can be supplied with a voltage below the threshold voltage of the transistor (i.e. sub-threshold logic), however no analysis has been completed to date with regards to the performance and operation of the level shifters required for communication between voltage islands of such disparate levels. Traditionally, level shifters were employed exclusively to allow chip core signals to be transmitted to the outside world through the pad ring, which often operated at a different voltage to maintain compatibility with older technology used at the system level. More recently, with the increased use of voltage islands within chips, functional units are being operated at different voltages allowing the core processor to execute the critical algorithm while running at a higher voltage (VddH) thus maximizing the performance. Simultaneously, all other noncritical circuits operate at a lower voltage (VddL) to improve the power efficiency. [8], reported that optimized multi-Vdd with multi- Vth designs provide a dramatic dynamic power reduction by 40-50% as compared to the original single Vdd design. In order to effectively interface critical cells at higher voltage, with non-critical cells at lower voltage, level shifters are required to fully turn-off the PFET (P channel Field Effect Transistor) of the driven gate and – in some cases – to ensure that no gate oxide voltage exceeds the reliability limits set by the technology node. To date, no report has been published that examined the use of level shifters to convert ultra-low sub-threshold signals to higher, traditional super-threshold voltages.

II. EXISTING LEVEL SHIFTERS (SURVEY) In this study the existing CMOS level shifters are broadly classified into two main categories: 1) Dual Supply Level Shifters (DSLS) and 2) Single Supply Level Shifters (SSLS). The advantages of SSLS over DSLS has been illustrated in [9] on the grounds of pin count, congestion in supply routing, complexity and overall system cost SSLS circuits do not require access to the lower supply voltage other than the signal to be converted. However in our target applications, all level shifters have unhindered access to both supply voltages without increasing routing congestion. In the spirit of maintaining comprehensiveness, one SSLS circuit was included in this comparison. Figures 1-a and 1-b illustrate the two traditional DSLS circuits that were evaluated in this analysis [10]. Figure 1-describes the traditional DSLS1, which is a differential cascode voltage switched logic gate, using a cross-coupled PMOS half latch operating at the higher supply voltage. The low input voltage, Vin, is shifted-up due to the positive feedback action of the cross-coupled transistors MP1 and MP2 to VddH. When Vin is low, MN1 and MP2 are activated and thus raise the voltage at node b1 to VddH, which results in the output being driven to low. Subsequently, if Vin asserts, MN2 and MP1 are activated thereby raising the output voltage to VddH. The pull down transistors MN1 and MN2 are required to be much larger size than MP1and MP2 as each has to overcome the PMOS latch action driven with a higher supply voltage. DSLS1 has the advantage of a simple design and is well suited for higher core voltages. However, for low input supply voltages, the performance degrades

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CMOS VLSI Architecture of Low Power Level Shifter (GRDJE / CONFERENCE / ICIET - 2016 / 075)

as the NFET devices (operating essentially with leakage in sub-threshold operation) are incapable of flipping the super-threshold PFET half-latch. In fact, for typical transistor sizing, this circuit may not operate at all when converting sub-threshold signals.

The DSLS2 in Figure 1 provides improved performance and stable current driving capability compared to DSLS1 by replacing the PFET half-latch with a PFET Current mirror. This design is well suited for wide voltage range conversion with regards to performance; however, DSLS2 suffers from increased power consumption resulting from the leakage path formed by either PFET in the current mirror and one of the NFET pull down devices – one of which is always on in a static sense. The final traditional level shifter evaluated in this

Fig. 1: Level Shifters

Comparison is the SSLS as shown in Figure 1-c and only requires access to the higher supply voltage, thus potentially easing routing congestion for cross supply signals. This circuit has high performance but can have significant leakage currents if there is a wide difference in the supply voltages.

Other level shifters have been reported which include thick gate oxide transistors, ideal capacitors and low threshold transistors [11-12] – all of which are not necessary in the context of sub threshold operation and also increase the cost of the standard CMOS process.

Consequently, these circuits have been excluded from this analysis. Furthermore, other level shifters [13] have been reported that have pass gate inputs which were also excluded as these devices are susceptible to above-Vdd and below-ground noise as well as being a source of potential reverse stage leakage.

For each of the conventional level shifters described above, an incremental improvement is possible by adding a voltage doubler at the input of the level shifter as shown in figure 2. Voltage doublers have been proposed in [14] that bootstrap the true and complement signal to almost double the low supply voltage.

For sub-threshold circuits, this means that the outputs are typically raised to super threshold levels (i.e. 0.35V doubled to 0.70V) and this has an exponential impact on the drive strengths of the NFET devices used subsequently in the level shifter – significantly improving performance.

A. Cross-coupled Level Shifter Conventional level shifter using cross-coupled PMOS transistors is depicted in Fig. 1(a). As shown in this figure, the incoming low voltage signal is inverted using an inverter connected to a low voltage domain, VddL. Cross-coupled PMOS transistors P1 and P2 are used to pull output to the high voltage, VddH. Leakage issue of the conventional buffer is alleviated since P1 and P2 are not driven by the incoming signal. However, this topology exhibits relatively high short circuit current during transition (either through P1 and N1 or through P2 and N2) even when the input transitions are fast.

III. BOOTSTRAPPING LEVEL SHIFTER Bootstrapping technique, as depicted in Fig. 1(b), has been proposed to reduce the transient power during level shifting. Voltage swing at specific nodes is reduced, thereby saving power [10]. In Fig. 1(b), two boot capacitors Cboot1 and Cboot2 replace NMOS transistors to maintain the voltage difference at the gate terminals of P2 and N2. Thus, the pull-down NMOS N2 at the output stage is driven between 0 and VddL whereas the pull-up PMOS is driven between VddH − VddL and VddH.

Bootstrapping technique achieves lower power at the expense of significant increase in physical area due to the relatively large boot capacitors, determined by where CA is total capacitance at node A, excluding Cboot1. Vdiode is the voltage drop across a single diode, similar to D0 in [9]. When VddL is sufficiently close to 2Vdiode, boot capacitor becomes considerably large. In [10], cross-coupled load is divided into half and only one boot capacitor is required, partially reducing the overall area requirement.

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CMOS VLSI Architecture of Low Power Level Shifter (GRDJE / CONFERENCE / ICIET - 2016 / 075)

A. Multi Threshold Level Shifter

Fig. 2: MCMOS LS

The LS circuit is shown in Figure 2. It combines the multi-threshold CMOS design technique along with novel topological strategies. The circuit consists of an input inverter, a main voltage conversion stage and an output inverting buffer. The input inverter (MP1/MN1) is designed using low threshold voltage (lvt) transistors. This provides fast differential low-voltage input signals to the main voltage conversion stage. To have higher strength of the pull-down network, also MN2 and MN3 are lvt transistors. Then, two lvt pMOS devices (MP2 and MP3) are added to both the branches of the circuit.

B. Proposed Level Shifter

Fig. 3: Proposed LS The proposed level-up, as illustrated in Fig. 3, is based on a traditional buffer with certain modifications to minimize short circuit current, reduce delay while minimizing the overall number of transistors. Since an input signal at the VddL level cannot completely turn off PMOS transistors, an inverter is designed with two NMOS transistors (N1 and N2) where N2 is driven by inverted input signal. When input signal is at logic low, N1 is off and N2 is on. Node A is at VddH − Vth sinceN2 cannot pass a full VDD. To compensate for the threshold voltage drop, two keeper PMOS transistors, P1 and P2, are added. When output node goes low, P2 is on. Since input signal is also at logic low, node A is pulled to VDDH. Note that P1 is added to prevent short-circuit current when node A is being discharged through N1. A pull down NMOS transistor, N5, is added to reduce the delay when the output is having a high to- low transition. If the input signal is at logic high, N1 is on, N2 is off. Node A is discharged through N1. Since P1 is off, no short-circuit current exists. As node A is discharged, output rises to VDDH through P4. The input and output waveforms of the proposed level shifter are illustrated in Fig. 3 where the low voltage domain is 0.7 V and high voltage domain is 1 V.

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CMOS VLSI Architecture of Low Power Level Shifter (GRDJE / CONFERENCE / ICIET - 2016 / 075)

IV. EXPERIMENTAL RESULTS The experimental results are given in Table 1 and the simulation results of layout and the waveforms are shown in the fig.4 and fig.5 S.no

Parameter

Existing

proposed

1

Power

300n

100n

Table 1: Experimental result

Fig. 4: proposed layout

Fig. 5: Waveform of proposed layout

V. CONCLUSIONS A novel dual supply level-up shifter is proposed for multivoltage operation. The proposed topology achieves less power than the most commonly used cross-coupled topology, while also consuming less area. As compared to bootstrapping technique, proposed topology achieves 10% reduction in physical area. Corner simulations are also performed, demonstrating the superior performance of the proposed level shifter.

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CMOS VLSI Architecture of Low Power Level Shifter (GRDJE / CONFERENCE / ICIET - 2016 / 075)

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