LAYERS2016
Power Semiconductor Devices Senior Scientist Dr. Oliver Rattunde shows how sputtering combined with the right choice of wafer handling and process control achieves successful metallization processes on thin 8 and 12 inch wafers.
Solid state semiconductor power devices, e.g. IGBTs (insulated-gate bipolar transistors) or MOSFETs (metal oxide semiconductor field-effect transistors) have gained large technological importance in efficient processing of electrical energy through means of electronic switching devices on different power levels. The sketch of an IGBT device (Fig. 1) shows that currents in power devices flow vertically through the silicon substrate. Reducing wafer thickness brings opportunities for optimized device performance including a) reduced electrical on-state resistance and thermal resistivity of the remaining substrate thickness, and b) decreased forward saturation voltage and turn-off losses. In current state of the art power device manufacturing the wafers are first processed on the frontside and then ground down to wafer thicknesses below 100μm prior to backside metallization (BSM). Semiconductor roadmaps are even targeting wafer thicknesses below 50μm in the near future. A variety of wafer support systems to handle these ultra-thin wafers already exist, the most prominent being the so called “Taiko”-wafer where only the inner area of the wafer is thinned, leaving an edge support ring. Fig 1: Structure of a typical IGBT device