Page 1

EDITION 2

ADVANCED PACKAGING

POWER DEVICES

WIRELESS COMMUNICATION

Solving challenges in Fan-out

Driving down energy consumption

Deposition of AlScN for 5G networks


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LAYERS magazine is produced by Evatec AG, Hauptstrasse 1a, CH-9477 Trübbach, Switzerland. All information is correct to the best of our knowledge at the time of going to press. Evatec AG cannot be held responsible for any errors or omissions. For any comments or queries contact allan.jaunzens@evatecnet.com. ©2016 Evatec AG. Cover image ©123rf.com/profile_everythingpossible Editor-in-Chief: Allan Jaunzens. Design: Doubletake Design (UK). Photography: Peter Fuchs (Buchs/Switzerland).


01

CONTENTS

Contents 02 Welcome to The Thin Film Powerhouse Andreas Waelti, CEO with a flavour of things to come in LAYERS

04-09 Introduction to Evatec

Overviews of our markets, products and company

10-25 Technology Overview

A round up of developments for Evatec platforms and process control technologies

26-39 Advanced Packaging

Solving challenges in the Advanced Packaging industry

40-47 Power Devices

From Silicon to SiC and GaN - whats coming up in Power Devices

48-57 MEMS

Developments in advanced functional materials for MEMS applications

58-65 Wireless Communication

New materials and manufacturing approaches for Wireless Communication

66-71 Optoelectronics

Leading the way in even higher performance and lower costs for the LED industry

72-79 HP Optics

From small batch to true mass production manufacturing solutions for a diverse market

80-81 Contacts

Contact details for our global sales and service network


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03

CEO’S INTRODUCTION

Welcome

to the “Thin Film Powerhouse” “The IoT a future connecting 7 trillion devices across a global population of 7 billion”

Connecting individuals, complete cities and even whole global populations, the so called Internet of Things (IoT) promises the power to connect 7 trillion devices across a global population of 7 billion, shaping every aspect of our daily lives. Driving forward the technologies at the very foundation of the IoT is part of our daily business. From the new advanced piezoelectric materials for the next 5G networks to the precision optical interference coatings required for 3D Sensing and Gesture recognition capability in our next generation smart devices, our thin film platforms and processes are designed to bring outstanding customer value with the highest yields and throughputs in the industry. Within our second edition of LAYERS, you will be able to read about the latest hardware and process developments in each of our core markets. I wish you “a good read” and look forward to the opportunity to meet many of you in the course of our daily work together over the year to come.

Andreas Waelti, CEO


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Evatec

Markets

Using the know-how built from 70 years in the market Delivering production solutions across each of our 6 core markets, we leverage our process competences in one area to accelerate process developments for customers in others. For example, our know-how in precise deposition of complex stacks for High Precision Optics is now helping customers in Wireless and LED achieve the refractive indices and thickness control they need in the thin films for their next generation devices.

A long history in optics and electronics

1946 R&D facility for thin film coatings established in Balzers, Liechtenstein

1850

1980 Optical Coatings established in late 1960s

First sales of optical disc (CD) metallizers

Optical disc technology (CD-R, DVD, BluRay in late 1990s

Merger Leybold & Heraeus

Merger with Leybold AG - selected Balzers businesses divested

1967

1994


05

EVATEC MARKETS

ADVANCED PACKAGING POWER DEVICES MEMS WIRELESS COMMUNICATION OPTOELECTRONICS HIGH PRECISION OPTICS

2015

Evatec continues rapid growth with acquisition of Oerlikon’s Advanced Technologies Segment

Front- & Backend Semiconductors

Merger with Plasma-Therm Inc. and ESEC

Foundation of EVATEC in a MBO of the Evaporation Technology business

2000

2004


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Evatec

Platforms

Delivering the right customer solution every time

Together with our Solution Design and Product Marketing teams, its our Heads of Business Units’ (BU) responsibility to make recommendations to our customers based on the thin film performance, throughput and wider production needs for new process developments. However, in other cases our customers have well established production lines and processes. They already know what tool type and deposition technology they want and our job is to make sure we deliver exactly that, with the latest improvements in production performance they need.

Silvan Wuethrich

Albert Koller

Dr. Volker Wuestenhagen

BU BATCH

BU CLUSTER

BU INLINE

BAK LLS EVO II MSP

CLUSTERLINE HEXAGON RADIANCE

SOLARIS

ÂŽ


07

EVATEC PLATFORMS

BAK – Evaporators between 0.5 & 2.0 metres Choose from standard, long throw and split chamber architectures with ‘Autoload’ option for full automation. Our source technologies for enhanced layer quality and Advanced Process Control (APC) techniques help you increase your yields across a wide range of applications.

LLS EVO II – Vertical Sputter for Metals, TCOs & Magnetics LLS EVO II is a load lock system with a proven track record across metals, TCOs and aligned magnetic films. Rapid exchange between substrate sizes up to 200x230mm and high speed loadlock pumping makes the LLS a flexible, high throughput production tool.

MSP - Mass Production in High Precision Optics The MSP batch sputter coater family delivers new performance levels in mass production for HP Optics. Evatec’s APC technology delivers accuracy and environmental stability in complex optical stacks for substrate sizes up to 560x380mm.

CLUSTERLINE® – 200 and 300mm Cluster Platforms The CLUSTERLINE® family are high volume single wafer processing production solutions enabling integration of PVD, Highly Ionized Sputter (HIS) , Soft Etch and PECVD process technologies. Choose CLUSTERLINE® for proven handling of thin wafers and proven PVD production knowhow including Wireless, BAW/SAW, Thin Film Heads, MEMS, Backside Metallization and Advanced Packaging.

HEXAGON – Your advantage in Advanced Packaging From UBM and RDL, TSV, Fanout and eWLB, Evatec’s Hexagon is dedicated to volume production at the lowest cost of ownership. Process organic passivated wafers at typical throughputs of 45wph without downstream contamination and enjoy strict process chamber and wafer temperature control.

RADIANCE – Sputter Cluster Platform RADIANCE is a 200mm sputter cluster platform integrating batch and single process module technology for high throughput deposition of TCOs , multi metal layers and high accuracy dielectrics for complex optical stacks in HP Optics, HBLED, and Optical MEMS.

SOLARIS – Fully automated solutions in thin film deposition SOLARIS platforms deliver high speed deposition of metals, dielectrics, oxides and TCOs on substrate sizes up to 15 inch diagonal. Full integration into automated fab lines enables handling of rigid or flexible substrates at throughputs up to 900 substrates / carriers per hour eliminating operator costs in high throughput applications like PV, Touch Screen and EMI shielding.


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A view from the outside Evatec is strategically positioned to continue its rapid growth in the thin film market with an enhanced technology portfolio, focused innovation and excellence in customer support.


09

A VIEW FROM THE OUTSIDE

Thibault Buisson Business Unit Manager, Advanced Packaging & Semiconductor Manufacturing

Evatec has grown out of a long tradition and history in thin film deposition, going back 70 years, to the Gerätebau-Anstalt (Equipment-making Institution) and to Balzers Coatings, originating in 1946 in Balzers, Liechtenstein. Starting with an objective of developing and manufacturing systems for production of thin film coatings on an industrial scale, the first production site was established in 1957 in Trubbach, Switzerland, the same beautiful Alpine location where Evatec’s headquarters are found today. From those first vacuum based systems providing simple anti-reflection coatings for camera lenses,. Evatec today provides flexible platforms for thin film deposition not just for the optical world but across, Advanced Packaging, Power Devices, Wireless Communication, MEMS, and Optoelectronics too The company has grown significantly over the years through internal development but the acquisition of the Advanced Technologies segment of Oerlikon in 2015 has largely enhanced the capabilities of Evatec in its core markets as well as added new markets. Mergers and acquisitions are not always successful, but here is a great example of a fruitful and symbiotic integration of two similarly sized businesses into a new more powerful entity. Of course, sharing the same culture has helped a lot (both originate from the same parent company), but, even though product portfolios were complementary, a strong strategic vision was

critical. As a result the product portfolio was enlarged, opening new opportunities for the new organization as a whole. Evatec’s strength in providing batch systems, has been greatly augmented by the capabilities of Oerlikon, a very well-known single substrate equipment supplier to the semiconductor, touch screen and PV industry. Building on the combined strengths and expertise, Evatec has widened its ability to support a broad spectrum of applications, providing a complete set of innovative solutions that can address both low and high-end markets. Evatec has a great future ahead and opportunities to both build and strengthen its position in the existing markets and to penetrate new markets. Evatec today is a trusted supplier providing a broad range of innovative thin film deposition solutions to its customers with well-known Swiss precision and highquality, recognized customer support and service. Yole Développement had the opportunity to visit Evatec’s headquarters and production site in Trubbach. Besides the great hospitality making us feel part of the team, we were impressed with the focused approach and capabilities: from batch evaporators to etch and sputter tools addressing low end but also high end silicon processing needs for several markets, the ability to support customized requests from its customers in addition to the standard platforms offerings, a wide range of process capabilities, batch, single as well as clusters, covering all type of wafer sizes (2”-12”), different shapes and type of substrates. Congratulations to the entire Evatec team for continuous growth in the future!

This article has been written in collaboration with Rozalia Beica, formerly CTO & Business Unit Director of Yole Développement.


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011

A CLOSER LOOK AT EVATEC TECHNOLOGY

Technology A closer look

The process of driving platform performance forward is a continuous one. In our Technology Chapter you can read about some of the latest developments for individual platfoms as well as how implementation of Advanced Process Control (APC) capabilities across platforms can brings fast track developments in process capability and production yield. Marco Padrun, CTO


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Hubert Breuss, Senior Product Manager

Ewald Strolz, Senior Product Manager Klaus Muendle, Product Manager

Cluster Strategy Driving down our customers’ Cost of Ownership

Ewald Strolz, Hubert Breuss and Klaus Muendle from the Cluster Business Unit explain how Evatec strategy for driving forward the performance of all the platforms in the portfolio means we can keep the very flexibility our customers demand and reduce their cost of ownership.


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COMPETENCES IN TECHNOLOGY

The acquisition of Oerlikon Advanced Technologies brought Evatec both an extended portfolio in existing markets and access to additional markets with the CLUSTERLINE®, HEXAGON and RADIANCE platforms. But far from replicating what existed already, the combined portfolio has brought our customers immediate benefits of wider capability within each of the markets we serve. Take LED for example: the RADIANCE with its batch module processing architecture is perfect for high throughput damage free deposition on GaN of the TCOs, metals and dielectrics needed for the transparent current carrying layers, contact stacks and DBR reflectors required in HBLEDS. Adding capability of CLUSTERLINE® for economical PVD of AlN buffer layers prior to MOCVD processes, deposition of barriers, contacts and solder materials means our LED customers can get more process capabilities from a single supplier.

…Or in the MEMS market: the CLUSTERLINE® offers superior performance on advanced functional materials like piezoelectric films of AlN, AlScN, ZnO, PZT or magnetic materials for the manufacturing of magnetic sensors or low coercivity magnetic cores. Completed with RADIANCE capabilities for optical films and it’s flexibility for general metallization needs, customers can now cover all their thin film needs with the Evatec cluster tool portfolio. Our portfolio today means we can serve customers with cost effective solutions all the way from prototyping and small volume production for 2 inch substrates using single process chamber, “multi source” for batch sputter capability all the way up to 24/7 production with up to 300mm formats.

CLUSTERLINE® 200 II

CLUSTERLINE® 300 II

RADIANCE

HEXAGON

TYPICAL MARKETS

ƒƒPower Devices, Wireless, LED, MEMS, Thin Film Heads, Advanced Packaging

ƒƒAdvanced Packaging, Power Devices

ƒƒLED, MEMS, Wireless, HP Optics

ƒƒAdvanced Packaging

PLATFORM ARCHITECTURE

ƒƒ8 sided platform ƒƒUp to 6 single process modules ƒƒUp to 6 aux. modules

ƒƒ8 sided platform ƒƒUp to to 6 single process modules ƒƒ1-2 aux. module ƒƒBatch degasser

ƒƒ4 sided platform ƒƒBatch process modules ƒƒUp to 3 single ƒ process modules

ƒƒUp to 6 process modules (including Degasser)

SUBSTRATE HANDLING

ƒƒUp to 200mm ƒƒThin/ TAIKO wafers ƒƒMulti-flat/notch aligner for 4”, 6”, 8” and square substrates ƒƒThin and thick wafer or glass handling

ƒƒUp to 300mm with or without carrier ƒƒThin/ TAIKO wafers ƒƒFan-out (mold) wafers ƒƒWafer flip

ƒƒUp to 200mm. Carrier or direct wafer ƒƒWafer flip

ƒƒ300mm with or without carrier ƒƒFan-out (mold) wafers

SOURCE CAPABILITIES

ƒƒSputter, ICP soft etch, PECVD ƒƒMultitarget module MSQ ƒƒHighly Ionized Source for via filling or denser films

ƒƒSputter, degas and ƒƒArctic ICP etch ƒƒMultitarget module MSQ ƒƒHighly Ionized Source for via filling or denser films

ƒƒSputter & ƒƒICP soft etch ƒƒMultitarget module MSQ

ƒƒSputter, Degas ƒƒArctic ICP etch

KEY PROCESSES

ƒƒAlN, AlScN, Oxides, aligned magnetic films, Metal stacks

ƒƒRDL & UBM, fan-out, TSV ƒƒFront- and backside metals

ƒƒLow damage TCOs ƒƒHigh precision optical interference coatings ƒƒMetal stacks

ƒƒRDL & UBM, Fan-out, TSV

KEY PLATFORM FEATURES

ƒƒThin Wafer handling/ direct 200mm wafer down to 70micron & 6mm bow ƒƒProcessing from ƒ -30ºC to +860ºC ƒƒHandling piezo materials

ƒƒThin Wafer handling direct 300mm wafer down to 300micron & 4mm bow

ƒƒIn situ measurementOptical monitoring, film stress ƒƒActive gas conduction cooling ƒƒHeating up to 320ºC ƒƒLow temperature processing ƒƒHandling piezo materials

ƒƒBatch degasser technology ƒƒHigh speed wafer transfer ƒƒSafest wafer handling for bowed substrates


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“Central to our strategy is the philosophy of maintaining flexible platform architectures whose process capabilities and throughputs can be enhanced for the future with the addition or upgrade of new source and control technologies.” THE ROAD TO REDUCED COST OF OWNERSHIP (COO)

MAINTAINING FLEXIBILITY FOR OUR CUSTOMERS

Of course there are specific roadmaps for each individual platform to raise its performance. For example, new rotating target technology on RADIANCE will enable high uniformity dielectrics for high performance optical layers without shapers- eliminating particles, raising deposition rates and increasing customer throughputs. On CLUSTERLINE® 200 II, our new Facing Target Cathode (FTC) technology will enable low damage deposition for TCOs and contacts on doped (epi) layers or to create ultra fine grained films while on both HEXAGON and CLUSTERLINE® 300 the new Degas and Arctic ICP Etch technologies for processing PI/PBO and Fanout (mold) wafers in Advanced Packaging offers both reduced Rc values and longer shield kit lifetimes at lowest substrate temperature.

Central to our strategy is the philosophy of maintaining flexible platform architectures whose process capabilities and throughputs can be enhanced for the future with the addition or upgrade of new source or new control technologies. Maintaining a strong in house engineering and process development capability is key. This allows us to respond quickly and cost effectively as our customer’s process demands change or production needs grow. We are already making engineering changes to do just that. Implementing the flexible platform control hardware and software already introduced successfully on RADIANCE in 2014 on the new CLUSTERLINE® family platform will reduce costs and simplify service, but will also give our customers freedom to exchange source and process control features across different platforms more easily than ever.

Working as a team within the Cluster Business Unit makes for accelerated developments across all platforms. For example, sharing experiences in TCSAW applications for both RADIANCE and CLUSTERLINE® has already helped us improve the performance of SiO2 deposition processes for all our customers- whether its optimisation of film density, surface quality or gap filling.


COMPETENCES IN TECHNOLOGY

015


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EVAPORATION TECHNOLOGY REACHES NEW HEIGHTS Evaporation may be a 50 year old technology, but that doesn’t mean there aren’t still lots of development possibilities and today’s BAK box coaters offer more choice in geometry, deposition sources and tighter process control capabilities than ever before. Product Manager Kurt Flisch tells us why evaporation remains one of the most flexible thin film deposition techniques available in the cleanroom. MORE FLEXIBILITY IN SIZE AND PROCESS GEOMETRY

MORE PERFORMANCE FROM SOURCE TECHNOLOGIES

From standard and long throw geometries to split chamber systems for shorter cycle times or sensitive deposition materials, todays standard BAK batch evaporators are already available in a wide range of sizes from 0.5m to 2m diameter to ensure there’s just the right evaporator to fit your batch size and throughput requirements. But now evaporation technology just got even more flexible. Here are just some of the ways in which custom engineering opens up new possibilities.

ƒƒ Higher capacity e guns and new barrel sources now open up possibilities for thicker layers up to 1000 microns.

ƒƒ Motor driven tooling systems that change throw distance to convert between standard and lift off geometries in a few seconds ƒƒ Custom substrate handing systems like “Pacman” that open up possibilities to consolidate different processes in a single cycle (‘Innovation in small batch manufacturing’ on page 78) for cost reduction in small batch processing.

ƒƒ The latest generation of plasma sources enable dense films but without costly daily maintenance and consumables, and provide opportunities for combined high precision dep and etch processes. ƒƒ “UNICALC” shaper simulation technology reduces shaper area for single or multiple source operation without compromise in distribution for enhanced deposition rates, lower process times and reduced materials costs.

UNICALC Shaper Optimisation reduces shaper size


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COMPETENCES IN TECHNOLOGY

Assisted calotte load is just one of many options for the BAK range

MORE FLEXIBILITY IN HANDLING

MORE PRECISION IN PROCESS CONTROL

From traditional manual loading to fully automated load lock systems, batch evaporators can now be delivered with cost effective handling systems that fit your process and throughput.

Without doubt however, its in the area of process control where evaporation technology has made the biggest leaps forward in the last decade including in situ Advanced Process Control (APC) technologies for more precise control of thickness, refractive index, film stability and stress.

ƒƒ Load lock systems bring shorter cycle times and enhanced throughputs. ƒƒ Semi automatic front end single piece calotte loading brings a higher load capacity, faster exchange using a second preloaded dome, and reduces chamber opening times. ƒƒ Fully automatic “Autoload” systems with front end cassettes eliminate manual handling, track each wafer, and enhance process yield. ƒƒ Single substrate load lock systems are ideal for for small evaporators.

ƒƒ Quartz control technology now measures more frequently and responds more quickly to crystal changes for more accurate layer termination. ƒƒ 12 way quartz head and chopper technologies offer more accurate control of thicker, complex stacks.

ƒƒ In situ stress measurement during deposition protects thin wafers against breakage or prevents the distortion of optical substrates. ƒƒ In situ optical pyrometry brings precise control of temperatures for critical Infrared processes or sensitive substrates.

ƒƒ Simultaneous measuring of 4 sources enables accurate “phasing” and codeposition processes.

SO WHERE DO WE GO FROM HERE? Evaporation technology and the BAK box coater looks set to remain a workhorse for deposition of metals, dielectrics TCOs and a whole range of compounds. It offers unrivalled flexibility - handling different substrate sizes, thicknesses and

ƒƒ In situ broadband optical monitoring combined with real time process re-optimisation during deposition enables deposition of complex optical interference coatings with new levels of precision and yield.

curvatures, and enables swap between different coating materials and new sources or alternative substrate tooling easily. And now evaporation technology is finding its way onto Evatec Cluster platforms too.

“The sky really is the limit!”


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SOLARIS S380 High speed processing brings the “fab of the future” one step closer

Head of BU Inline Systems Dr. Volker Wuestenhagen explains how the new large S380 joining the SOLARIS family brings more high speed sputter capability in mass production applications for consumer devices, and brings the dream of the automated fab one step closer. THE HIGH SPEED SOLARIS FAMILY JUST GOT BIGGER The SOLARIS S151 is already well proven as a high volume production tool in both Power Device and Photovoltaic applications, depositing metal contact stacks, transparent current carriers (TCOs) and Antireflection (AR) coatings. SOLARIS S380 now brings the same high speed processing capabilities but on substrates up to 15 inch diagonal, and just as importantly, with the same film quality and uniformities already proven on the smaller S151.

SPEED & FLEXIBILITY ARE AT THE HEART OF THE SOLARIS CONCEPT SOLARIS handles glass, silicon or polymeric substrates with ease. Parallel carrier transfer around the individual process stations is the perfect solution for high speed processing and lowest cost of ownership in true mass production applications on S380 including “Touch Panel” and EMI Shielding for todays mass market wireless consumer devices. ƒƒ Handle carriers for individual substrates or mini batches without compromise on process uniformity. ƒƒ Convert between rigid, 2.5D substrates and foils with ease. ƒƒ Make multiple passes in front of process stations for complex thin film stack designs.

SPEED WITHOUT COMPROMISE IN QUALITY SOLARIS S380 delivers precise deposition of dielectrics, metal oxides, TCOs, metals stacks and even alloys using MSQ multource technology for co-deposition. ƒƒ Evatec cathode technology allows deposition uniformities of < ±2% over the whole 380mm diameter carrier, essential for the optical quality of layers required for hand held mobile devices. ƒƒ Carrier design engineering means that mini batches can be processed without edge effects. ƒƒ “Penta Plus” cathode technology available on S380 delivers perfect step coverage and the process cost reductions essential for high performance EMI shielding for our smart phones.


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COMPETENCES IN TECHNOLOGY

SOLARIS S151

SOLARIS S380

ƒƒUp to 8 inch diagonal or mini batches on carrier

ƒƒUp to 15 inch diagonal or mini batches on carrier

Delivering ever growing volumes and lower costs but without compromise in film quality needs new thinking in PVD production. The fully automated fab is coming and SOLARIS is ready. ƒƒ “Inline” handling compatibility eliminates the need for any operator intervention. Yields can be increased and with the benefit of reduced manpower costs at the same time. ƒƒ Continuous processing offers the potential for improved reproducibility and overall quality. ƒƒ Capability for automatic change of substrate size or shape if production demands change means downtime can be avoided and better fab loading achieved.

SUBSTRATE CAPABILITY

Carrier Ø 245mm

THE “AUTOMATED FAB” IS GETTING CLOSER

Carrier Ø 430mm

Head of Technology BU Inline Systems Stephan Voser in action testing “Penta Plus” cathode technology

3.5” carrier

8” carrier

3.5” carrier

8” carrier

15” carrier

SOURCE TECHNOLOGIES

ƒƒUp to 6 process stations for RTP, PVD, ETCH & CVD

ƒƒUp to 5 process stations for RTP, PVD, ETCH & CVD

DEPOSITION UNIFORMITIES

ƒƒ<±2% over whole carrier

ƒƒ<±2% over whole carrier

THROUGHPUT

ƒƒUp to 1200 carriers per hour

ƒƒUp to 900 carriers per hour

FOOT PRINT

ƒƒ2.5 x 3.5 meters

ƒƒ3.6 x 8.4 meters

FAB INTEGRATION

ƒƒFully automatic -- Load unload -- Change substrate size ƒƒHost connection via MES

ƒƒFully automatic -- Load unload -- Change substrate size ƒƒHost connection via MES

“Its time to let SOLARIS help you turn your high speed processing dreams into reality”


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Patrick Biedermann, Product Manager

Both the LLS and MSP may be well proven production tools in their target markets but that doesnâ&#x20AC;&#x2122;t mean we arenâ&#x20AC;&#x2122;t as determined as ever to introduce new features that enable new processes and deliver new levels of productivity. Patrick Biedermann and Martin Bless introduce the latest developments for the LLS EVO II and the latest version MSP launched in late 2015.


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COMPETENCES IN TECHNOLOGY

RAISING THE BAR IN VERTICAL BATCH SPUTTER TECHNOLOGY

Martin Bless, Senior System Engineer

LLS EVO II

MSP FAMILY

TYPICAL MARKETS

ƒƒMEMS including Thin Film Head Technology

ƒƒHigh Precision Optics & Optoelectronics

PROCESS CAPABILITIES

ƒƒUp to 5 cathodes for sequential or co-sputter ƒƒDegas, etch and heat in loadlock ƒƒTCOs, Metals and aligned magnetic films

ƒƒUp to 6 cathodes ƒƒHigh Precision Dielectrics ƒƒTCOs and Metals ƒƒPlasma source for etch or assisted processes

SUBSTRATE CAPACITIES

ƒƒ9 x 8 inch wafers per batch ƒƒSubstrate sizes up to 200mm x 300mm

ƒƒ16 or 32 x 8 inch optical substrates per batch according to platform size ƒƒSubstrate sizes up to 560mm x 380mm

KEY TECHNOLOGIES

ƒƒCustom cathode technologies with higher rates and lower materials consumption ƒƒRobot load including buffering and mask handling

ƒƒAdvanced Process Control for precise control of optical layers ƒƒPlasma source technology for PIAD


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THE NEW MSP MEANS MORE POSSIBILITIES From smart consumer devices that keep us in touch 24/7 to Head Up Displays (HUD) or GPS satellite navigation systems that keep us on the right road, our world relies on mass production of high precision optical interference coatings. Here are some of the changes to make the new MSP an even more flexible tool.

SPUTTER CAPABILITY ƒƒ Up to 6 cathodes in DC / Dual Magnetron Operation ƒƒ Deposition of TCOs, dielectrics and metals

MORE…

LAYERS ƒƒ Higher stack thickness up to 20μm without compromise in stability ƒƒ Better surface qualities

PROCESS CHOICES ƒƒ Integrate pre-cleaning steps ƒƒ Add DLC or antismudge layers ƒƒ Achieve better adhesion on plastics

CONTROL Plasma Emission Monitoring and Broadband Optical Monitoring for: ƒƒ Shift free coatings with edge repeatabilities <0.2% in mass production

FLEXIBILITY ƒƒ Simple exchange between substrate sizes ƒƒ Up to a maximum of 560mm x 380mm with better uniformity then ever

THROUGHPUT ƒƒ Choose from the MSP 1225 with useable area of 1.5m2 or the MSP 1232 with useable area of 2.2m2 without compromise in optical performance ƒƒ Longer target lifetimes, quicker target changes


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COMPETENCES IN TECHNOLOGY

WHY LLS EVO II LIFTS YOUR PERFORMANCE The LLS EVO II packs in a whole host of new features that enhance productivity and reduce material consumption. Whether its new cathode technology, new magnetic film aligning field technology or new high speed pumping solutions, the new LLS EVO II platform raises yields and lowers production costs.

SPUTTER CAPABILITY ƒƒ New oval cathode technology (Fig.1) for improved utilization, even lower particle counts and 20% lower target costs. ƒƒ “High Energy Cathode” technology at 12kW for improved throughput in high rate metallization processes (Al & Al alloys). ƒƒ High performance magnet systems for extended target life in sputter of both magnetic (up to 15 times) and non magnetic materials (up to 2 times). ƒƒ Modified rotary cage housing incorporating aligning field magnet systems (Fig. 2).

FLEXIBLE SUBSTRATE HANDLING Fig. 1: Oval cathode technology

ƒƒ Manual loading for complete or mixed batches of substrate sizes of 2, 3, 4, 5, 6 & 8 inch. Change configuration of substrate sizes in just a few minutes. ƒƒ Batch processing of substrates up to maximum size of 200mm x 300mm. ƒƒ 6 axis automated robot solution with cassette buffer, flat/notch aligner and bar code reader with new mask handling solutions that simplifies set up and raises throughput.

Fig. 2: New performance levels for magnetic stacks are made possible by the “In situ” aligning field magnet system on the LLS


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ADVANCED PROCESS CONTROL Levels of reproducibility and repeatability can now be reached which were considered impossible not long ago. Senior Scientist R&D Dr. Silvia Schwyn Thoeny explains how. Advanced Process Control (APC) methods have made tremendous advances over the last years enabling the deposition of thin film coatings of unprecedented complexity with new levels of accuracy, repeatability and yield. Evatec offers a number of APC technologies across its range of production platforms. We use our know-how across optical, optoelectronic and compound semiconductor layer processing to drive down cost of ownership. Our customers can benefit from cross-disciplinary synergies, e.g. by using techniques developed for precision optics in electro-optic applications. â&#x20AC;?In situâ&#x20AC;? measurement methods available today include broadband optical monitoring, plasma emission monitoring, pyrometry and the measurement of film stress and sheet resistance.

OPTICAL MONITORING Optical monitoring is a technique originally developed for the deposition of precision optical coatings. Such coatings are composed of a number of transparent layers with high and low refractive index and individual layer thicknesses in the range of a few to a few hundred nanometers, which need to be controlled very tightly. There are two basic types of optical monitoring available, namely monochromatic and broadband optical monitoring. Monochromatic monitoring has been in widespread use for

over three decades and uses a single wavelength to measure the thickness of a growing film. With the advent of ever faster computing power broadband monitoring has also now become available enabling simultaneous measurement of transmittance or reflectance over the entire visible and NIR spectrum using a diode array spectrometer. The spectrum is repeatedly measured during the layer growth. Deposition is terminated once best match between calculated final spectrum and measured spectrum is reached. Additional process accuracy is gained by using direct monitoring on the original work piece or at least the position of the original work piece, which eliminates inaccuracies of tooling factors. On-line re-optimization was added lately to broadband monitoring (Figure 1). This feature uses the information of the spectral data at the end of each layer to determine any thickness errors in layers already deposited. The thickness of the remaining layers will be automatically refined if the cumulated errors exceed a predefined threshold value. The combination of direct broadband monitoring with online re-optimization allows us to reach unprecedented precision in manufacturing of complex filter coating and to cut development times since new layer designs can often meet spectral specifications within the first test run.


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COMPETENCES IN TECHNOLOGY

This same control system originally developed for precision optics can also be used for the deposition of nanometer thin metal layers (Figure 2) achieving thickness reproducibility for optoelectronics applications not achievable by other methods. SAW and BAW filters in Wireless Communication applications also benefit largely from dielectric layers with reduced thickness variations, which allow tighter device specifications and reduced manufacturing costs.

the chamber and without the need to premeasure the sample. Test series which formerly took a day or two to be performed can now be done within some hours.

PLASMA EMISSION MONITORING

For high precision optics applications preservation of a very precise surface figure is of utmost importance, which can only be obtained with low stress coatings. We could show with a series of experiments (Figure 3) that depending on the deposition parameters the stress in a dielectric SiO2/TiO2 mirror can be tailored from tensile to compressive.

Plasma emission monitoring PEM is an APC method enabling increased deposition rates in reactive processes. Typical examples would be dielectrics like SiO2 and Nb2O5. Oxides can be sputtered by using an RF sputter technique, but with the drawback of low deposition rates. Thus, oxides are most often sputtered by pulsed DC power mode from metallic targets with the addition of oxygen to the sputtering gas. Under the appropriate deposition conditions this gas can react to form completely oxidized films. However, the reaction not only takes place in the growing film but also on the target. When the reactive gas flow exceeds a certain value, the metallic target surface is rapidly covered by oxidic reaction products, which reduce the target conductivity and results in a sudden drop of the sputtering rate. The process point in the transition region between metallic and oxidized state, which yields both highest deposition rate AND fully reacted films tends to be unstable. Plasma Emission Monitoring PEM allows us to work in a stable way at this point by measuring the intensity of a spectral emission line of the gas or the sputtered metal and keep it constant by a feedback loop to e.g. the reactive gas or the target voltage.

As an illustration, the stress in a metal contact stack needed to be reduced. Being able to see stress evolve in situ let us identify which of the materials contributed most to the stress. By adapting the process parameters the overall stress of the stack could be reduced by half.

On-line reoptimisation during deposition for improved yields

Figure 1

Deposition of thin metal films

Deposition rate can be boosted up to a factor of 4 compared to DC pulsed sputtering with constant flow. In addition to increasing rates PEM is also highly beneficial for processes which need to keep an oxidation level within a close margin, such as in the deposition of ITO or VOx.

MANAGING STRESS Stress is another important film characteristic which may need to be tightly controlled. In the in situ stress measurement system two parallel beams are reflected from a surface. Depending on the surface curvature these beams will diverge or converge after reflection. The separation of the beams is detected and used to calculate the radius of curvature and the stress in the layer provided the material properties of the substrate and the film thickness are known. Being able to measure the stress in situ brings major time savings in situations where test series have to be performed to optimize the stress. In the classical way, the surface figure of a test sample has to be measured before coating, then the coating run is made, the sample is taken out and the surface figure is measured again. From the difference between pre and post measurements the stress can be determined. In the in situ measurement however, the change of the radius of curvature and thus the stress can be observed as it changes during the process. Thus different process parameter settings can be run one after the other all on the same substrate without venting

Figure 2

Mirror stress at various deposition conditions

â&#x20AC;&#x153;APC techniques open up new possibilities in Thin Film Processesâ&#x20AC;?

Figure 3


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ADVANCED PACKAGING

Advanced Packaging

Andreas Erhart, Senior Manager Product Marketing

The past five decades in Advanced Packaging have been driven by the increase of performance and integration but also by a reduction of form factor and costs. Evatec has been a strong partner supporting this evolution of Semiconductor packaging and is very well prepared to pursue this path in the coming decades whether it is for Cu pillar, Interposer, TSV or the more recent requirements for embedded chips in a mold on 300mm wafer. With industryleading recent results of 30â&#x20AC;&#x2122;000 wafers sputter etch shield kit life, we look forward to continuing to provide customers with outstanding process solutions and the lowest cost of ownership.


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Advanced Packaging

The Rising Wave of the Semiconductor Industry

The introduction of new functionality, miniaturization and cost down- Advanced Packaging has the potential to offer it all. Thibault Buisson from Yole DĂŠveloppement reviews the prospects for the technologies within the Advanced Packaging market over the next 5 years.


COMPETENCES IN ADVANCED PACKAGING

029

WHERE ARE WE TODAY ?

AN OPPORTUNITY FOR ADVANCED PACKAGING

For more than five decades the semiconductor industry has followed Mooreâ&#x20AC;&#x2122;s law, driving miniaturization of transistors and scaling of the CMOS technology to smaller and more advanced technology nodes while at the same time reducing the cost significantly. This miniaturization process has resulted in higher performance devices, increased I/O density and a more efficient utilization of the silicon space.

To overcome these limitations, the industry has turned its attention to the alternative approach of Advanced Packaging that can address both current and future market demands with more flexible manufacturing and integration approaches, bringing new technologies faster to market at a lower cost, and still addressing further performance increases and miniaturization.

The semiconductor industry is expected to start another cycle that will be driven largely by consumer products and the Internet of Things (IoT). Although performance and cost were the 2 main drivers historically, todaysâ&#x20AC;&#x2122;s growing portfolio of applications and a higher diversity of products means that the ability to incorporate various new functions within a system and product, while continuing the miniaturization,and cost down trends, is becoming even more challenging. Building various functionalities within the chip was traditionally done using a system-on-chip (SoC) type architecture, but its becoming more and more difficult and costly to use the same structure for more complex systems where integration of various disparate technologies is required. While the scaling process continues and more advanced technology nodes are being developed, the investment and developmental time required are increasing significamtly.

Its no surprise that a significant level of activities are currently taking place in this segment. Advanced Packaging brings a broad range of platform and interconnect technologies that can address requirements across various markets, from low to mid and high end applications for consumer, computing, industrial, automotive, renewable energy, military and aerospace, etc. Packaging of devices was done traditionally with lead-frames and wirebonding, but newer advanced packaging technologies have been developed and commercialized addressing both single and multiple die integration. There are several platforms available today in the market: platforms using encapsulation based technologies (especially applied for MEMS and sensors, wafer level optics), packages with electrical redistribution layers (either within the die, as would be the case of fan-in, or extending outside the die in case of fan-out), embedding dies within organic substrates, flip chip bumped packages using intermediary substrates and stacked devices using through-silicon-via interconnect technologies. The suitability of each of these platforms and market adoption will depend on the final product and application needs.


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THE EVOLUTION OF SEMICONDUCTOR PACKAGING

(Source: Advanced packaging & Semiconductor Manufacturing Workshops, Yole Développement, July 2016)

ADVANCED PACKAGING PLATFORMS

Source: Advanced Packaging and Manufacturing Business Unit at Yole Développement, July 2016)

FUTURE GROWTH OF ADVANCED PACKAGING

(Source: Status of the Advanced Packaging Industry report 2015, November 2015, Yole Développement)


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COMPETENCES IN ADVANCED PACKAGING

WHAT ARE THE FASTEST GROWING ADVANCED PACKAGING PLATFORMS TODAY? Although the Advanced Packaging market today enjoys only a small share (around 20% in wafers) within the total packaging market of the semiconductor industry, it has potential to grow and is expected to reach by 32% market share by around 2020 as more and more applications transition from traditional packaging platforms like wirebonding and lead-frames to more advanced ones. In terms of revenue, by 2020, Yole Développement estimates that Advanced Packaging will reach approximately 44% of the total revenue for the semiconductor packaging. Increased performance and functionality, miniaturization and low cost will continue to be the key drivers for Advanced Packaging. However, fab space to accomodate this increased capacity is also at a premium so individual tool throughput and footprint will also be key factors going forwards. Which packaging platform will have the fastest growth in the coming years, will be highly impacted by market demands, high volume applications, and ability to meet market requirements, availability and readiness of the infrastructure and supply chain necessary to support its manufacturing but there are some trends.

faster speeds, higher bandwidth needs, lower form factor and reduced power consumption, its adoption is expected to expand and further grow (25% CAGR until 2020). ƒƒ Fan-out: A very promising platform that embeds dies in a molding compound. It brings several advantages over other platforms, such as reduced package thickness, better thermal and electrical performance, and enabler of 3D and System-inPackage integration of multiple dies as well as lower cost. As a result, this platform is expected to have the highest growth in the coming years (55% growth). The major OSATs have also been very actively involved in developing their own solutions in addition to the already well established eWLB technology.

REVENUE FORECAST BY ADVANCED PACKAGING PLATFORM FROM 2014 TO 2020 – IN US$ BILLION

Yole Développement continues to see strong interest in high throughput platforms offering low cost of ownership addressing single die needs (such as fan-in) as well as platforms enabling multi-die and System in Package (SiP) integration, such as fan-out, flip-chip and 3DIC: ƒƒ Flip-chip: Still the dominant platform in Advanced Packaging (representing over 70% of the total Advanced Packaging revenue) this could be impacted significantly by the application processors (APU) market in high-end smartphones if fan-out will replace the typical flip-chip package known as package-on-package (PoP), limiting its growth to 5% over the next 5 years> ƒƒ Fan-in: Expected to have a stable growth of 8%, mainly driven by low cost and form factor packaging needs (continues to represent a large share, approximately 30%, as type of package in the high end smartphones) ƒƒ 3D IC: 3D integration using through-siliconvia (TSVs) can be applied directly for stacking devices or using an intermediary interposer (2.5D integration). Applied to CMOS IS initially, its adoption has broaden to other devices as well, such as MEMS, FPGAs, most recently GPUs and activities are ongoing for the first processor using TSVs to commercialize. Due to its ability to address

(Source: Status of the Advanced Packaging Industry report 2015, November 2015, Yole Développement)

ITS AN EXCITING TIME FOR ADVANCED PACKAGING ! Advanced Packaging is a very dynamic offering a wide variety of platforms for the future. Driven especially by consumer and IoT applications, it brings great flexibility in integrating and packaging devices, from single to multiple dies and addresses a wide range of requirements.

“Advanced Packaging is expected to reach more than a 40% market share by revenue of the total packaging market in 2020”

This article has been written in collaboration with Rozalia Beica, former CTO & Business Unit Director of Yole Développement.


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Solving challenges in processing FOWLP substrates Senior Scientist Mohamed Elghazzali explains how challenges of achieving low contact resistance of the UBM or RDL metallization to the contact pads in FOWLP technology can now be overcome using the latest degas and etch technologies.


033

COMPETENCES IN ADVANCED PACKAGING

The use of polymer materials has been a standard for many years already in the field of wafer level packaging.

Sputter etching by argon ions is used for the removal of metal oxide from the contact pads. This process is non-selective and has the disadvantage that the etched polymer forms a thick “not dense” deposit on the chamber shielding during the use of the tool, which would ultimately lead to particle generation. Since the etch process is required to remove the oxide and organic residue at relatively high rate, it induces heating of the wafers, and an increasing amount of VC outgassing – mainly water vapour and organic residuals - occurs over the process time. Fig. 1 shows an RGA tracing during the ICP etch process. Excessive VC presence will make the plasma process unstable and contaminate the contact pads resulting in a bad contact resistance.

While processing silicon wafers coated with PI (polyimide) or PBO (polybenzobisoxazole) in vacuum deposition tools already poses challenges due to heavy outgassing and critical temperature limitations, FOWLP technology (Fan-out wafer level package) creates a significantly bigger challenge as the wafers are constituted out of silicon dies embedded in epoxy mold compound and polymers where low cure temperatures need to be used Achieving low contact resistance of the UBM or RDL metallization to the contact pads of such wafers in a conventionally equipped PVD tool is virtually impossible due the challenges mentioned above. The following key criteria must be addressed at temperature levels of 120 to 150°C: 1. 2. 3.

The two major requirements of the etch process are: a) To guarantee a low contact resistance and b) To keep particle generation low An essential measure to combat particle generation is the use of pasting wafers where Al is backsputtered intermittently to enhance the adhesion of the material deposited on the shields.

Sufficient degas at compliant temperature Removal of the native metal oxide from the contact pads by sputter etch Deposition of the metal contact, typically by sputtering Ti followed by Cu

The degas step is critical; on one hand a certain degas temperature should not be exceeded to avoid over curing of the polymer, while on the other hand outgassing needs time according to the thickness of the polymer material. However, long outgassing times reduce the throughput of a tool and should be avoided, thus alternatives with stack degassing capability had to be developed.

Figure 1: RGA of VC during sputter etch process

After the etch process, the wafer is transferred to the sputter chamber without delay so any contamination is minimized. Once the wafer is covered by the first metal, the contact pad as well as the polymer is sealed and no further impact on the contact resistance can occur.

SINGLE WAFER DEGAS SOLUTION Simple hot plate degassers with substrate clamping and backside-gas coupling have been successfully used for single wafer degassing over many years. Our new concept heats up the wafer embedded in a shallow pocket as shown in Fig. 2. Very effective dual sided heat transfer is achieved. After heating up the wafer to typically 150°C in less than 20s, the pocket is opened wide to enable effective pump-out of the VCs. The faster heat up rate compared to the hot plate concept provides a much shorter degas time at any given temperature to enable the best possible throughput.

Figure 2: Principle of single wafer degasser


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The same design can also be used as a cooling station which may be required prior to the etch step. The degassing output from PBO coated silicon wafers has been analyzed by RGA. VC emission starts much earlier compared with the previous hot-plate design due to the higher heating rate which is ideal as organic volatile compounds are desorbing with a delay compared to water vapor. Figure 3: Degas spectra of a PBO wafer during degassing at 150°C in new single wafer degas module.

high if a laminar flow of inert gas is applied, while in vacuum the degassing of the volatile components has to take place via less efficient molecular diffusion. Atmospheric Batch Degassers with laminar flow concept do not show any change in process pressure if new wafers are loaded into the same environment as already outgassed wafers. Vacuum Batch Degassers on the other hand with molecular flow show a much higher risk of contamination of outgassed wafers by new incoming wafers resulting in possible unstable Rc. Eliminating this potential risk would require new wafers only to be added once all outgassed wafers have left the degas chamber resulting in very low throughput. On completion of degas, the load lock is pumped and the wafers are cooled down ready for the next low temperature process steps. Mold wafer outgassing on Atm. Batch Degasser (ABD)

Figure 5: H2O partial pressure comparison of mold wafers in etch chamber, not-degassed and degassed in atmospheric batch degasser.

BATCH DEGAS SOLUTION Fan-out wafers with the much thicker polymer/ epoxy mold compound need a much longer degas time than the cycle time of a single wafer. In this case a batch type degasser is used where several heated slots are available and the wafers are degassed in parallel. Two different concepts of batch degassers are used, for either atmospheric or vacuum operation. The advantage of the batch degasser in atmosphere is a much faster and better controllable heat-up of the wafers along with a simpler design. Diffusion of volatile components from the bulk material to the surface is only driven by temperature. Desorption is driven by the concentration gradient which is the same whether desorption takes place in vacuum or in atmosphere. However, the advantage in atmosphere is that the concentration gradient can always be kept

THE NEW ICP ETCH SOLUTION The ICP sputter etch module covers one of the most important steps in WLP - the removal of oxide from the final metal pads to allow contact formation. To efficiently handle the polymer materials and adhere


035

COMPETENCES IN ADVANCED PACKAGING

Fig. 8, the particle level after 30’000 processed wafers, based on 300Å (SiO2 eq.) removal and PBO passivation, is extremely low. Figure 8: Particle performance during 30’000 wafer Marathon

40 1.5-10µm

>10µm

30 20 10 0

The design of the RF application on the chuck has also been improved significantly resulting in a higher etch rate, a better uniformity and a reduction of RF noise.

0

5’000

10’000 15’000 20’000 Wafer count #

25’000

30’000

PRODUCTIVITY FOR FOWLP

Figure 7: ICP etch rate (SiO2 equivalent) over 30’000 wafers

Figure 10: Wafer Temperature profile of Fan-out wafer

Evatec’s single wafer sputter tools CLUSTERLIN® and HEXAGON provide highest throughput in the industry for Fan-Out wafers when taking advantage of the new features of the atmospheric batch degas and the new ICP etch.modules Critical aspect like thermal budget in the ICP etch module and optimized process flow ensure that high productivity is achieved. As shown in Fig. 9 the thermal budget depends on the incoming wafer temperature as well as the wafer mass/thickness. For standard thickness wafers, a throughput of 50 wafers/hr was achieved,based on 30nm removal of SiO2 equivalent in a 2-step etch process. Airlock

ABD

Artic Cool

Etch 1

Etch 2

PVD Ti

PVD Cu

160 140 120 Temperature [ºC]

The module has been tested during full production with the ICP Etch process, showing that all cooled surfaces stayed stable at a temperature of -30°C. An etch rate 50% higher than previously could be achieved. As Fig. 7 shows the etch rate is stable over the entire marathon test of 30’000 wafers. Production data - Etch rate stability

Production data - Particle adders over a single kit life 50

Particle adders

to the low processing temperature requirements, a number of new design ideas had to be implemented, especially the improved cooling of the ICP dome, shielding and the substrate pedestal. An optimized shield set combines the highest possible pumping conductivity with full protection of the chamber walls and ,any possible particle generation is kept at an absolute minimum. These combined measures provide significantly shortened maintenance times, i.e. faster cool down/heat from room temperature to -30°C, an easier shield change, and an optimized conditioning.

100 80 60 40 20 0

0 10 20 30 Time [sec]

0

100

200

300

400

500

Time [sec]

CONCLUSIONS New improved solutions for processing of highly outgassing Fan-out wafers have been developed and tested. A batch degas module for Fan-out wafers and an improved ICP etch chamber capable of running higher throughput with reduced maintenance frequency were designed resulting in excellent process results including low contact resistance. The new solutions provide significant savings in terms of maintenance and cost of ownership and extend tool capability for the next generation wafer level packaging requirements.

Even with this high etch rate the new ICP Etch solution achieves extremely low contact resistance (Rc). The Rc shows a high stability over the whole lifetime of the chamber shield kit. As illustrated in


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Pushing the boundaries in Ionized PVD Evatec’s Senior Scientist Dr. Juergen Weichart and Fraunhofer’s Kay Viehweger* explain how Highly Ionized Sputter (HIS) source technology now enables TSV processing for Aspect Ratios of up to 20:1


037

COMPETENCES IN ADVANCED PACKAGING

Kay Viehweger Fraunhofer

Fig.1: Cross section of liner plated TSVs AR 20:1 center position

Highly Ionized Sputtering (HIS) has been developed for the deposition of metal barrier and copper seed layers in Through Silicon Vias (TSV) with very high aspect ratios, where PVD continues to be the preferred method for metal barrier and seed layers before subsequent electroplating. The process flow consisting of deep silicon etch, oxide liner deposition, seed deposition and electroplating on TSVs with aspect ratio 10:1 has been developed in a joint development project between Evatec and Fraunhofer IZM ASSID. and results have been published elsewhere. In recent experiments however, we investigated the limits of HIS in even higher aspect ratios up to 20:1. Vias with 10µm diameter and 200µm depth were etched in 300mm wafers and a seed layer of ~300nm Ti and ~2.2µm Cu was deposited using the Evatec CLUSTERLINE®300 cluster tool with HIS. The 20:1 vias were cut and analyzed by cross-section SEM showing that the minimal seed thickness for a successful electroplating process of >20nm could be achieved in every location of the via. From experience we know that the region between 50% and 75% of the via depth is most critical here. Subsequently a liner was deposited by electroplating and the result is shown in Figure 1. As this cross-section shows, the seeding is free of defects, however the plating chemistry has reached its limits. A complete filling could by achieved at ASSID for aspect ratios up to 15:1, but they are still under investigation for 20:1. Nevertheless the plated liner could be used to verify the completeness of the liner over the entire 300mm wafer by using X-ray tomography, which is currently the best non-destructive method showing that all vias on the entire wafer received a flawless liner. Figure 2 shows X-ray tomography pictures of the dense pattern of vias in the center and at the edge of the wafer. This tilted view allowed confirmation that the electroplating is complete in every individual via by measuring its length.

*Kay Viehweger, Fraunhofer IZM ASSID, Ringstraße 12, 01468 Moritzburg, Germany

Fig. 2: X-ray tomography of liner plated TSVs with AR 20:1, left: center of the 300mm wafer, right: edge of the wafer

COST EFFECTIVE PROCESSING OF TSVS WITH AR 20:1 IS A GO! Liner plating on TSVs with AR 20:1 has been demonstrated successfully, suggesting that PVD seed deposition can still be used with all its advantages of equipment, process costs, and integration issues. What’s more, the comparatively close target-to-wafer spacing results in high specific deposition rates, and high target utilization provides very good cost-of-ownership compared to other directional sputtering techniques. In addition the same PVD module also allows deposition of UBM and/or RDL metal layers at even lower target-to-wafer spacing without the need of a re-configuration or venting of the tool.


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A leap forward in EMI shielding EMI shielding of Chips on a package level makes PCB substrate design simpler and more compact as package densities increase and shielding demands get tougher. Senior Product Manager Markus Frei explains why multilayer PVD coating by sputter on SOLARIS S380 is the perfect cost effective solution for high performance applications.


039

COMPETENCES IN ADVANCED PACKAGING

GETTING EMI SHIELDING RIGHT

FINDING THE RIGHT MANUFACTURING SOLUTION

Shielding uses multilayer stacks to reduce EMI by reflection and/ or absorption of electromagnetic waves. The primary mechanism of EMI shielding is usually reflection where conductive materials with mobile charge carriers are needed – typically metals like aluminum, silver, gold or copper. The secondary mechanism is absorption where the shield material should have electric and or magnetic dipoles which can interact with the electromagnetic fields in the radiation. Materials like stainless steel and nickel with high values of magnetic permeability are typical. At high frequencies, most of the wave energy is reflected from a shield’s surface, while a smaller portion is absorbed. At lower frequencies, absorption generally predominates. Shielding performance is a function of the properties of the shielding materials and the quality of the coating, the frequency, and the distance from the source to the shield. Step coverage and good adhesion are essential, and packages must be protected from high temperatures during coating to avoid damage.

Low cost solutions like painting or plating may have been good enough in the past, but as portable electronics like smartphones become smaller and lighter, work at multiple frequencies, increasing data transfer rates and higher chip densities, older RF shielding techniques simply are not up to the job. Sputtering however, is an inherently flexible process. Changes in layer materials or thicknesses as shielding process needs change can be implemented quickly and cheaply. The challenge however is to achieve the demanding cost targets in volume production.

LARGE AREA COATING ON SOLARIS S380 FITS THE BILL The new SOLARIS S380 with its dedicated sputter cathode and cooling technologies delivers reduced cost of ownership at typical throughputs of 20,000,000 chips per month.* ƒƒ Integrated precleaning process module for removal of any organic residues ensures good layer adhesion and higher process yields. ƒƒ Deposition of metals stacks using “Penta Plus 380” cathode technology brings enhanced side wall coverage at a larger radius allowing more substrates to be coated on a single carrier. ƒƒ Simple 150mm diameter monoblock targets with lower manufacturing costs combined with high target utilisation reduce overall materials costs. ƒƒ Integrated cooling station keeps backside temperature under control for prevention of package damage ƒƒ Tool architecture ideal for automated fab integration reducing cost of ownership in high volume manufacturing.

SST 0.3µm1) Cu 3 - 5µm1)

SST 0.1µm1) x

Wi-Fi or RF amp etc.

Substrate mounting plate

Requirement of side wall deposition thickness ,x’ of copper: ≥ 2µm1)

Design of typical shield structure on an RF Amplifier

TYPICAL PROCESS FLOW IN THE SOLARIS S380 Plasma Clean

Degas

Adhesion Layer

TAKE A LOOK AT THE RESULTS

Conductive Layer

1.

Passivation Layer 2.

Fig 1: 430mm carrier with coating area 380mm diameter holding 940 chips with 1mm separation* Fig 2: Side Wall Coverage measured at 50% Fig 3: SOLARIS flexibility allows simple management of process temperatures with its cooling station combined with its multi-turn facility

3. Typical monthly throughputs according to process conditions for a standard shielding stack. PROCESS

NO. OF MULTI-TURNS

MAX. BACK SIDE TEMP [°C]

TURN TIME PER CARRIER [S]

EFFECTIVE CYCLE TIME PER CARRIER [S]

SUBSTRATES / CARRIER (BASED ON CHIP SIZE 8 X 8 MM)

SUBSTRATES / HOUR

SUBSTRATES / MONTH

0.2µm-3µm–0.2µm 2)

8

154

14.95

120

940

28300

20’300’000

0.2µm-3µm–0.2µm 2)

9

141

14.75

133

940

25500

18’300’000

0.2µm-3µm–0.2µm 2)

10

130

14.60

146

940

23200

16’600’000

* Based on chip dimensions 8 x 8 mm


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POWER DEVICES

Power Devices

Hans Auer, Senior Manager Product Marketing

Power electronics, or more specifically “solid state electrical devices” are used to control electric power. Silicon semiconductors have been employed in power circuits since the invention of the solid state diode by William Shockley in 1960. Today the discrete power device market has achieved nearly 20 billion USD of market size with a predicted CAGR of ~7%. This continuous growth is driven by the ever increasing needs for energy management and control in domestic and industrial markets, mobile communication/ computing and most recently by greenhouse gas reduction initiatives. Electric vehicles like cars and trains as well as renewable energy generation looks set to spur the major part of power device development and growth in the near future. Evatec has a strong footprint in the power electronics sector – both as the industry leader in metallization of traditional power devices and also now for latest generation MOSFET and IGBT devices with very thin wafers for 8“ and 12“. Current state of the art technology includes fully automated handling and processing platforms for wafers down to 50µm with high equipment uptimes and device yields. Delivering solutions to deposit stress sensitive 4- layer backside metal stacks with integrated “in situ” clean-etch for oxide removal and annealing capability for the ohmic contact formation is just part of our daily work. A large part of the innovation for next generation power transistors takes place in wide bandgap GaN and SiC technology. Evatec’s existing experience in silicon power devices and in related technologies such as GaAs III-V devices or GaN technology from the LED industry means we are ideally positioned to contribute to the development and industrialization of these new innovative power device types.


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Power Semiconductor Devices Senior Scientist Dr. Oliver Rattunde shows how sputtering combined with the right choice of wafer handling and process control achieves successful metallization processes on thin 8 and 12 inch wafers.

Solid state semiconductor power devices, e.g. IGBTs (insulated-gate bipolar transistors) or MOSFETs (metal oxide semiconductor field-effect transistors) have gained large technological importance in efficient processing of electrical energy through means of electronic switching devices on different power levels. The sketch of an IGBT device (Fig. 1) shows that currents in power devices flow vertically through the silicon substrate. Reducing wafer thickness brings opportunities for optimized device performance including a) reduced electrical on-state resistance and thermal resistivity of the remaining substrate thickness, and b) decreased forward saturation voltage and turn-off losses. In current state of the art power device manufacturing the wafers are first processed on the frontside and then ground down to wafer thicknesses below 100μm prior to backside metallization (BSM). Semiconductor roadmaps are even targeting wafer thicknesses below 50μm in the near future. A variety of wafer support systems to handle these ultra-thin wafers already exist, the most prominent being the so called “Taiko”-wafer where only the inner area of the wafer is thinned, leaving an edge support ring. Fig 1: Structure of a typical IGBT device


043

COMPETENCES IN POWER DEVICES

Although evaporation is a long established metallization method for power devices especially on wafer sizes up to 6”, sputtering has become more common over the last 10 to 15 years. Batch sputtering tools with manual handling were the initial solution of choice for thin wafers due to the lack of automated thin wafer handling solutions, but nowadays with 8” and even 12” in production, reliable thin wafer handling has become a must. Applying the backside metallization on these wafers poses several challenges for semiconductor manufacturing tools, both handling and process wise – all of which have been successfully addressed by the EVATEC CLUSTERLINE® and RADIANCE cassette-to-cassette cluster tools.

Fig 2: Cassette design handles large wafer bows

THIN WAFER HANDLING The EVATEC CLUSTERLINE® and RADIANCE apply a variety of dedicated end effectors and dedicated metal cassette geometries with different slot pitch for reliable handling of thin wafers with less than 100µm wafer thickness tolerating wafer bow of up to 4mm (Figs. 2 & 3).

PROCESS CHALLENGES Fig 3: End effector for thin wafer handling

Sputter source Plasma Wafer Chuck Fig 4: Pyrometer set-up with light pipe and optical fiber integrated in the chuck body looking at the backside of the wafer during processing

Light Pipe Fiber Optics Pyrometer

BSM process optimization requires superior stress control (low wafer bow + warp required for subsequent process steps) as well as advanced temperature management. Wafer temperature is both a major parameter for stress control as well as the activator of good ohmic contact of the backside metal to the semiconductor device, which relies on inter-diffusion or alloying of the BSM with the silicon at elevated temperatures. EVATEC CLUSTERLINE® manufacturing equipment offers dedicated chuck-top hardware for enhanced temperature control including “black” chucks for enhanced IR radiative heat absorption, and electrostatic chucking for superior thermal contact to the chuck. In addition an optional in situ pyrometer for IR temperature measurement can be installed for monitoring and documenting wafer temperature and process stability (See Fig. 4). Fig 5. shows in situ pyrometer data during NiV deposition proving excellent repeatability and thus process stability in the EVATEC CLUSTERLINE®. Final bow of thin wafers with complete layer stack Etch / Al / Ti / NiV / Ag has been reduced to values below 10µm with optimized Evatec process settings e.g. by optimizing the NiV process step (Fig. 6).


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Fig. 5: Pyrometer signal during 200nm NiV deposition for 15 Taiko wafers (130µm) processed during several days

Fig.6: Measured wafer bow for 130µm 8’’ Taiko wafers with complete layer stack Etch / Al / Ti / NiV / Ag for different NiV process settings (NiV film thickness 1100nm).

TEMPERATURE SIMULATIONS

Fig.7: Temperature simulation for BSM layer stack ICP etch / 200nm Al (hot chuck) / 200nm Ti / 600nm NiV / 200nm Ag for different wafer thickness.

Wafer temperature simulations enable modeling and understanding of the effects of different parameter changes on wafer temperature during BSM processing. Fig 7. shows simulated wafer temperatures for different wafer thickness clearly indicating the effect of lower thermal mass for very thin Si substrates. The observed saturation temperature for thin wafer processing depends on both heat input from etch and film deposition as well as on heat loss mechanisms, mainly by radiation. Thus the nature of the wafer (e.g. bare Taiko wafer vs. processed device wafer with reduced frontside emissivity) has a large influence on the final temperature as can be seen in Fig 8. where reduced emissivity of the device wafer (devices facing towards the chuck) leads to far less heat exchange with the chuck underneath.

IN SITU ANNEALING Additional heat sources for in situ annealing enable contact formation at elevated temperatures independent of individual layer thicknesses of the deposited layer stack. This is mandatory for layer stacks that do not provide sufficient thermal budget during the deposition. Also, the combination of depositing thin films at lower temperatures and annealing afterwards reduces thermal stress and thus bow and warp of the ultra-thin substrates.

Fig.8: Temperature simulation for BSM layer stack ICP etch / 200nm Al (hot chuck) / 200nm Ti / 600nm NiV / 200nm Ag for different wafer types. A device wafer usually has reduced heat exchange with the underlying chuck and thus requires process adaptions (in this case for NiV) in order to not exceed 400°C wafer temperature.

For EVATEC CLUSTERLINE® and RADIANCE systems customers can choose from two options for in situ annealing: 1) a lamp anneal module for top side heating by halogen lamps, and 2) bottom side IR radiative heating by resistive heating elements integrated into the chuck.


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COMPETENCES IN POWER DEVICES

Pyrometer Crystal lens assembly IR lamp

Wafer

Fig. 9a: Schematic of the lamp anneal module

LAMP ANNEAL MODULE ANL200

Fig. 10: Heater power and temperature signals during a two-step lamp anneal process for a 725µm thick SensArray wafer.

Infrared Heating

Fig. 11: Microscopy image of Al spiking into the Si for chuck annealing after 200nm Al deposition. Note: Al film has been chemically etched away in order to visually inspect the wafer surface.

Sitting in a highly reflective (mirror-like) chamber the wafer can be heated by an arrangement of six halogen lamps upto a heating rate of 6°C/sec for standard thick wafers and 30°C/sec for 100µm thin wafers respectively. Since heat radiation hits the wafer on the top side first absorption is mainly governed by the emissivity of the (already deposited) backside metals and thus rather independent of the device structure on the front side of the wafer. In situ pyrometer data gives additional information on the stability of the annealing process. Wafer processing in the anneal module usually involves a ramp-up step at high heater power followed by a second step at reduced heater power in order to maintain the desired equilibrium temperature. This process sequence is displayed in figure 10 where heater power of 100% and 20% respectively are used to reach an equilibrium temperature of 430°C for a 725µm thick Si-wafer equipped with thermo-couples (SensArray). Also displayed is the pyrometer signal which shows good correlation to the thermocouple temperature.

IR CHUCK HEATER Another in situ annealing option which has been applied successfully on EVATEC CLUSTERLINE® and RADIANCE systems consists of a resistive heating element which is completely integrated into the chuck body and thus emits IR heat radiation onto the bottom (device) side of the wafer. Specific designs of the resistive heating elements allow tailored temperature uniformities on the wafer. In principle the IR chuck heater can be mounted in any PVD module; for standard BSM applications it may be installed in the Al module e.g. for in situ anneal after the Al deposition. Experiments have shown reproducible spiking patterns for Al on Si for in situ post-anneal after low temperature deposition of 200nm Al on thin Taiko device wafers (Fig.11).


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Driving deployment of Wide Band Gap Power Devices on 200mm Hans Auer and Scientist, Dr. Dominik Jaeger introduce the advantages of Wide Band Gap (WBG) power devices and some of the development challenges ahead.

Today silicon power device technology has evolved to a very mature state. However, with limited options for major future innovation steps thatâ&#x20AC;&#x2122;s where wide bandgap (WBG) semiconductors now have the opportunity to step in. Their capabilities to operate at higher voltages and temperatures along with significantly lower switching losses enable power circuits to run at much higher frequencies resulting in reduced size. For example, the heat sink size for variable speed drives of industrial electric motors could be reduced by more than 50%. Battery operated vehicles, mobile computing or wearable electronics could all benefit from longer battery lives. Electric drives like fans, pumps, compressors, conveyer systems could all use less power, achieving overall energy savings of more than 20% once wide adoption is achieved.

Pw 1MW

RAIL TRACTION SMART POWER GRID WINDMILLS

GaN SiC DC AC Inverter

DC DC Converter

350kW Hybrid Automotive

100kW

HEV / EV PHOTOVOLTAIC INDUSTRIAL DRIVES

HEV / EV PHOTOVOLTAIC

50kW 30kW 5kW 1kW

POWER SUPPLY HOME APPLIANCE NETCOM, SERVER, NOTEBOOK

Rated voltage 600V

1000V

1200V

Figure 1: application fields for SiC & GaN power devices


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COMPETENCES IN POWER DEVICES

The two most interesting materials to build WBG power devices are silicon carbide (SiC) and Gallium Nitride (GaN). Although their use is still small today, the projected sales growth for these devices is between 50 and 80% for the next 5 to 10 years. SiC is the preferred material for device ratings in excess of 600 volts with applications in hybrid/ electric vehicles, solar inverters and industrial power supplies, while GaN is expected to dominate low voltage applications due to it’s low switching loss with a focus on DC/DC converters/ commodity power supplies and motor drives.

Figure 2: (right) HEMT structure as overgrown by Fraunhofer Institute for Applied Solid State Physics (IAF)

GaN cap layer

25nm

GaN:nid

Figure 3: (below) AFM image by Fraunhofer (IAF)

400nm

GaN:C

1050nm

AlN interlayer

25nm

GaN:C

710nm

AlN interlayer

AN ALTERNATIVE PRODUCTION APPROACH While the SiC power devices are manufactured from bulk SiC wafers, GaN devices are made on Si wafers with epitaxial grown GaN, a lower cost method than building the devices from bulk GaN. The main challenge in manufacture of GaN on Si substrates is the high lattice strain at the GaN / Si interface which necessitates an AlN buffer layer for subsequent GaN crystal growth. While this layer is traditionally made by MOCVD , sputtered AlN has recently made inroads due to the significantly lower cost over MOCVD. Compared to MOCVD deposition, sputtering of AlN enables higher deposition rates and the amount of cleaning cycles in the MOCVD reactor can be reduced dramatically. Furthermore the pit density in the GaN MOCVD is reduced by the AlN PVD buffer layer and hence results in a higher yield.

3nm

AlGaN barrier 25%

25nm

GaN:C

550nm

Al0.25Ga0.75N

550nm

Al0.65Ga0.35N

300nm

Al0.83Ga0.17N

250nm

AlN

100nm Si (111)

FILM DATA OF SPUTTERED ALN OVERGROWN WITH ALGAN: XRD FWHM 00.2 (tilt) of 0.127º Surface roughness comparable to reference (RMS<0.2nm) 2DEG depth 35.0nm Nmin ≈ 1013/cm3 Vth ≈ -3.3V Ns ≈ 5·1012 /cm2

HARDWARE INFORMATION Standard soft etch-module Heated chuck in the process module at T>800ºC with good uniformity (<40ºC) Standard AlN deposition hardware (cathode) for full face deposition Temperature-characterization in Transfer-Module

Figure 4: CLUSTERLINE® 200 II

THE PVD SOLUTION IS READY TO IMPLEMENT A manufacturing solution already used in the LED market for GaN on Si is also now ready to be deployed to the power device market. Process integration work with focus on 8” Si wafers is ongoing with multiple partners. The sputtered AlN buffer layers represent savings in MOCVD capacity of > 20%.

Data of sputtered AlN buffer layer: FILM PROPERTIES (100NM ALN ON SI) Deposition Rate (nm/s)

0.2

Thickness Uniformity

± 3.5%

Film Stress (GPa)

0.6 (tensile)

XRD Rocking Curve AlN (002)

< 2500arcsec

XRD Rocking Curve GaN (102)

Comparable to MOCVD AlN buffer

Roughness (AFM, rms)

< 1nm

“SiC and GaN look set to grow rapidly”


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MEMS

MEMS

Maurus Tschirky, Senior Manager Product Marketing

Micro-Electro-Mechanical Systems, or MEMS, is a technology that in its most general form can be described as miniaturized mechanical and electromechanical elements (i.e., devices and structures). MEMS devices can vary from relatively simple structures having no moving elements, to highly complex electromechanical systems with multiple moving elements under the control of integrated microelectronics. A more imaginative perspective might see in MEMS no less than another â&#x20AC;&#x153;REVOLUTIONâ&#x20AC;?. They are the bridge between the digital and the real world. Look at inertial instruments for example: Such complex mechanical and optical instruments once weighing several kilos and restricted to submarines and missile war-heads for those who could afford it, are now size of a fraction of a fingernail and cost a few tens of cents. Such devices allow for more natural and intuitive communication with machines. The next step here is already demonstrated by yet another concept involving optics for gesture recognition. All of this is summarized as Heterogeneous Integration of various physical stimuli into a single device where the integration actually happens on silicon wafers. Thin film technology is at the core of the MEMS fabrication and Evatec delivers deposition solutions for advanced functionality materials with optical, magnetic, piezoelectric, thermoelectric and chemical properties to enable the required multidisciplinary approaches now and in the future. We strive to advance MEMS fabrication methods that promise an enormous design freedom wherein any type of sensor or actuator can be merged onto a single substrate combining approaches in microelectronics, photonics and nanotechnology.


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Challenges in characterization of piezoelectric thin films Professor Paul Muralt, from Ecole Polytechnique Fédérale de Lausanne talks about measurement techniques and explains the challenges in proper characterization and measurement of thin piezoelectric films like AlN and AlScN approach is long, complex, and not practical for materials research targeting at processproperty relationships for a large number of process parameters. For this reason, materials scientists use a simplified approach, i.e. to produce controlled deformations without making much of micromachining before (thus film on full substrate), and to measure resulting charges, or to apply an electric field in a well defined capacitor structure, and measure the resulting strain or stress.

Figure 1: Schematic drawing of the wurtzite structure as e.g. for an AlN-ScN alloy having the Al position partially occupied by Sc. The polar characteristics of wurtzite is based on the fact that all tetrahedrons of the same type (either formed by 4 N, or by 4 metal ions) are pointing in the same direction. In the drawing, N tetrahedrons are pointing up, metal tetrahedrons are pointing down.

Piezoelectric coefficients are the most important property parameters for a piezoelectric material. Unfortunately, the electromechanical response is not a simple one because dielectric, elastic, and piezoelectric properties are linked together. For the characterization of a single crystal material, one would prepare several samples (platelets) with different orientations, in order to measure the elastic, dielectric, and piezoelectric properties (11 in total for AlN) along all major directions. For a thin film, this approach is not feasible for all orientations. The most easy one to realize is the geometry of a thin film bulk acoustic wave resonator, i.e. a platelet with (0001) faces and measure e33, c33D, ε33S and ε33T through the excitation of standing waves along the thickness of the plate, and measurement of the impedance or admittance as a function of frequency. With other vibration modes one can derive further properties. This


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COMPETENCES IN MEMS

However, this approach is not as simple as measuring a bulk sample. We can see the difference considering the assessment of the direct piezoelectric effect with a bulk sample equipped with 2 parallel electrodes (see fig. 2), and which is based on the following constituent equation:

D3 means the displacement field or charge density produced at electrodes perpendicular to the 3-axis, equal to the charge Q3 divided by the electrode area. When applying an exclusive T3 stress, and measure the charge at a virtual short (which is the case when using a charge amplifier), then we get , or when applying an exclusive stress T1, then we can derive also. When we try to do the same with a thin film sample we have several problems. In theory, it is possible to apply T3, because the stress will be the same in the substrate and in the thin film. However, the substrate will expand in the transverse direction (S1, S2 different from zero as T1=T2=0) differently as the piezoelectric thin film would do alone, because the respective s31 compliance values are different in general. The strain of the substrate is imposed to the piezoelectric thin film, causing more charges on the electrodes due to the transverse piezoelectric effect. The latter is best expressed in terms of the e-coefficients in this case:

The second problem is that we cannot a defined apply a transverse stress (T1, T2) to the piezoelectric film, because the substrate will dictate the elastic reaction, and not the film. What we can do, however, is to impose a defined transverse strain (S1, S2) to the substrate, meaning that we rather get e31, than d31. The ideal variables for the thin film problem are thus T3, S1 and S2. One can show that the constituent equation can be transformed to the following form:

where

We note that the effective thin film coefficient d33,f is always smaller than d33, and that the effective thin film e31,f has a larger value that e31. For measuring e31,f one has provide an experiment with a well known substrate deformation, to put T3=0 (this is the case at 1 atmosphere pressure (=0.1 MPa)), and E3=0 when using a charge amplifier. The controlled deformation is conveniently achieved by a bending experiment. The most simple experiment with a well defined strain is the 4-point bending test [1]. It works also be single point bending [2] and plate flexural bending [3]. The cantilever for bending experiments have a defined long direction along which the main strain is develops (say S1). Then, in a wide range of thickness to width ratios, the strain S2 is then given by the Poisson ratio νsub of the substrate: S2=- νsub S1. It follows that

So besides the curvature, one needs to know also the Poisson ratio of the substrate. In case of cantilevers obtained from (001) silicon wafers, the Poisson ratio amounts to 0.28 when the cantilevers point along [100], and 0.064 when they point along [110]. For measuring d33,f we consider the converse effect:

Applying E3 (voltage V3), and measuring the thickness change Δtp by double side interferometry, we can derive d33,f as Δtp/V3 provided that (1) S1=S2=0 and (2) the substrate does not change its thickness. The reason is that one measures the complete thickness change, the sum of the substrate and of the thin film. Unfortunately, these 2 conditions are normally not met. They would be true in the limiting case of an infinitely stiff substrate. For AlN/Si this is definitely not the case. So the only way to get around this problem is to perform finite element calculations. The elastic properties of the substrate are usually well known, and e31,f can be measured before. Let us call this new method FEM supported interferometry.


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Table 1: Thin film coefficients for AlN, derived from data as obtained at single crystals, epitaxial AlN thin films on sapphire (SAW device characterization), from direct thin film measurements (fat), and from ab-initio studies. Values in italics stand for derived values. The bold numbers are either measured directly (kt2 from TFBARs).

For AlScN thin film measurements one can first test the methods on pure AlN, for which properties are quite well known by now. The first complete determination of AlN properties was carried out at epitaxial AlN thin films on sapphire substrates by Tsubouchi and Mikoshiba [5] already in the early 1980’s. They characterized surface acoustic wave resonators. It does not require much effort in micromachining, but a large effort in characterization and fitting procedures to reproduce impedance curves of SAW resonators. A multitude of different SAW geometries, eventually also different substrates, combined with the simulation of wave propagation is needed to derive all property coefficients. The pioneering work of Tsubouchi and Mikoshiba [5, 12] shows that such work can be realized with very good results. In their work, AlN thin films were deposited by MOCVD at temperatures between 1000 and 1180 °C. Their values remained reference data, are reported in compendia of piezoelectric materials [13], and included in material libraries of finite element modeling programs. For a long time they were without competition by single crystal data. A new trend is to use ab-initio calculations based on density functional theories (DFT). They become increasingly powerful, and tend to meet experimental values more and more precisely. Recently, it became also possible to grow high quality AlN crystals. Their piezoelectric properties are not yet as high as in thin films, but close. Table 1 shows that crystal data, epitaxial film data, and ab-initio calculations are rather underestimating the coupling coefficient kt2. There is tremendous data collection of thickness mode resonators, because they are the heart of a large portion of RF filters used in mobile phones. The coupling coefficient is frequently reported to be around 6.5% for resonators near 2 GHz. Lakin et al [7] reported even a value of 7.0 % obtained with solidly mounted resonators. Electrode material (acoustic impedance) and thickness need to be chosen

optimally for getting the best possible coupling at a given frequency (AlN thickness). With higher frequency, electrodes tend to reduce the coupling as their relative volume in the resonator tends to increase. But even at 8 GHz, a coupling of kt2 = 5.9 % was realized [14]. The difference with respect to the T&M value is most likely due to a too high dielectric constant in the latter data set. A relative ε33S of 9.6 (corresponding to ε33,f = 10.3) would better fit to single crystal and sputtered thin film values, and leads to a kt2 of 6.7 % using otherwise T&M data. For resonator data, d33,f is derived between 3.86 pm/V (kt2 = 6.5 %) and 4.00 pm/V (kt2 = 7.0 %). The true values of AlN are with high precision: d33,f = 4.0 pm/V and e31,f = 1.05 C/m2.

THEORY & PROPERTIES OF AlScN ALLOY THIN FILMS Recently, it was discovered that Al substitution by Sc allows an increase of the piezoelectric response [15, 16]. Apparently, it needs a 3+ ion whose nitride structure exhibits a higher coordination than 4. Sc in AlN spreads the nitrogen tetrahedron to find more space. It is mainly the lattice constant a that increases. The length of c is almost untouched [8]. The Sc ion thus tends to approach the nitrogen base plane, increasing the u-parameter from 0.38 towards 0.5, as shown by ab-initio calculations [10]. Centring the Sc in the base plane would nearly cause a 5-fold coordination. The enlargement of the unit cell volume increases the distance between ions, and leads to a softening of the material. DFT works advance the interpretation that there is a competition of Al3+ and Sc3+ ions about the coordination of nitrogen resulting in a kind of frustrated system [10]. With increasing Sc concentration in the wurtzite phase, the potential wells of the ions become less deep, and thus the ionic displacements in an electric field become larger, leading to larger piezoelectric strains and dielectric responses. For piezoelectric characterization, Akiyama et al. applied a measurement technique that is applied for bulk materials (typically PZT ceramics). The sample was squeezed between two spherically shaped stamps, one serving at the same time a contact for charge collection. The curved shape served to avoid that curved substrates reacted by bending the sample, rather than reducing the thickness (which of course gives large contributions from strains S1 and S2 in eq. 1). When the curvature of the substrate is not changed, the Poisson effect also


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COMPETENCES IN MEMS

causes a lateral extension leading to an effective strain imposed to the thin film as defined by the difference in transverse compliance coefficients s13 ((s) stands for the substrate):

The corresponding transverse piezoelectric contribution must be added to eq. 1. These strains are positive when T3 is negative. As e31,f is negative, and d33,f is positive, the transverse effect gives the same charge sign as the longitudinal effect. Such test set up measures a larger d33,f than really present, the value is indeed even larger than d33. The interesting point is the s13 values of AlScN and Si are very close at 40 % Sc, when considering the predicted s13E of Caro et. al. for Al0.6Sc0.4N. This would mean that the value of 21.1 pm/V published in [16] for this composition would be free of d31 contribution! DFT calculations are predicting an even higher value of 29.3 pm/V [11]. Both are extraordinary high values for nonferroelectric materials, and even more spectacular considering the low dielectric constant! In fig. 3, the so far published piezoelectric coefficients d33,f and e31,f for AlScN thin films are shown. The curves were corrected when there was too large a deviation from the true values for pure AlN. The values were then compared with published DFT results. It is interesting to note that ab-initio calculations rather underestimate piezoelectric properties at larger Sc concentrations. Figure 3: Longitudinal, clamped coefficient d33,f=e33/c33E. The DFT Caro curve is from ref. [11], and the DFT Tasnadi curve from ref. [10]. EPFL data are from[8, 18]. Experimental data were adjusted proportionally when not having close to 4.0 pm/V for d33,f, and close to 1.05 C/m2 for e31,f.

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REFERENCES

1. K. Prume, P. Muralt, C. F., T. Schmitz-Kempen and S. Tiedke, Piezoelectric thin films: evaluation of electrical and electromechanical characteristics for MEMS devices. IEEE Trans. UFFC, 2007. 54: p. 8-14. 2. M.-A. Dubois and P. Muralt, Measurement of the effective transverse piezoelectric coefficient e31,f of AlN and PZT thin films. Sensors and Actuators A, 1999. 77: p. 106-112. 3. J.F. Shepard, P.J. Moses and S. Trolier-Mckinstry, The wafer flexure technique for the determination of the transverse piezoelectric coefficient (d31) of PZT thin films. Sensors and Actuators A, 1998. 71: p. 133-138. 4. A.V. Sotnikov, H. Schmidt, M. Weihnacht, E.P. Smirnova, T.Y. Chemekova and Y.N. Makarov, Elastic and piezoelectric properties of AlN and LiAlO2 single crystals. IEEE Trans. UFFC, 2010. 57(4): p. 808-811. 5. K. Tsubouchi and N. Mikoshiba, Zero-temperature coefficient SAW devices on AlN epitaxial films. IEEE Trans. Sonics and Ultrasonics, 1985. SU-32: p. 634-644. 6. A. Mazzalai, D. Balma, N. Chidambaram, R. Matloub and P. Muralt, Characterization and fatigue of the converse piezoelectric effect in PZT films for MEMS applications. J.MEMS, 2015. 24: p. 831838. 7. K.M. Lakin, J. Belsick, J.F. Mcdonald and K.T. Mccarron. Improved bulk wave resonator coupling coefficient for wide bandwidth filters. in IEEE Ultrasonics symposium. 2001. Atlanta (GA), USA: IEEE. 8. R. Matloub, M. Hadad, A. Mazzalai, N. Chidambaram, G. Moulard, C. Sandu, T. Metzger and P. Muralt, Piezoelectric AlScN thin films: A semiconductor compatible solution for mechanical energy harvesting and sensors. Appl.Phys.Lett., 2013. 102: p. 152903. 9. F. Bernardini, Spontaneous and piezoelectric polarization: Basic Theory vs. Practical Recipes, in Nitride Semiconductor devices, J. Piprek, Editor 2007, Wiley-VCH: Newark, USA. p. 49-68. 10. F. Tasnadi, B. Alling, C. Hรถglund, G. Wingqvist, J. Birch, L. Hultman and A. Abrikosov, Origin of the anomalous piezoelectric response in wurtzite ScAlN alloys. Phys.Rev.Lett., 2010. 104. 11. M.A. Caro, S. Zhang, M. Ylilammi, T. Riekkinen, M. Moram, O. Lopez-Acevedo, J. Molarius and T. Laurila, Piezoelectric coefficients and spontaneous polarization of AlScN. J.Phys.: Condens. Matter, 2015. 27: p. 245901. 12. K. Tsubouchi, K. Sugai and N. Mikoshiba. AlN material constants evaluation and SAW properties of AlN/Al2O3 and AlN/Si. in IEEE Ultrasonics Symposium. 1981. 13. J.G. Gualtieri, J.A. Kosinski and A. Ballato, Piezoelectric materials for acoustic wave applications. IEEE UFFC, 1994. 41: p. 53-59. 14. R. Lanz and P. Muralt, Bandpass filters for 8 GHz using solidly mounted bulk acoustic wave resonators. IEEE Trans. UFFC, 2005. 52: p. 936-946.

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15. M. Akiyama, T. Kamohara, K. Kano, A. Teshigahara, Y. Takeuchi and N. Kawahara, Enhancement of piezoelectric response in scandium aluminum nitride alloy thin films perpared by dual reactive cosputtering. Adv.Mat., 2009. 21: p. 593-596. 16. M. Akiyama, K. Kano and A. Teshigahara, influence of growth temperature and scandium concentration on piezoelectric response of ScAlN alloy thin films. Appl.Phys.Lett., 2009. 95: p. 162107. 17. M. Moreira, J. Bjurstrom, I. Katardjiev and V. Yantchev, Aluminum scandium nitride thin film bulk acoustic resonators for wide band applications. Vacuum, 2011. 86: p. 23-26. 18. R. Matloub, A. Artieda, E. Milyutin and P. Muralt, Electromechanical properties of Al0.9Sc0.1N thin films evaluated at 2.5 GHz film bulk acoustic wave resonators. Appl.Phys.Lett. , 2011. 99.


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Fig. 1 MSQ 200 Multisource

A promising future for AlScN in MEMS Aluminum Nitride (AlN) is a promising material for MEMS applications due to its good piezoelectric performance and superior dielectric properties, e.g. low permittivity and low dielectric losses. Forming AlScN by substituting a fraction of Aluminium with Scandium is a viable way to enhance the materialâ&#x20AC;&#x2122;s properties even further. Dr. Steffen Chemnitz from University of Kiel explains how this enables benefits for sensing, actuating and energy harvesting in numerous MEMS devices and reports results for AlScN film properties achieved to date.


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COMPETENCES IN MEMS

At the same time, the permittivity rises more moderately by a factor of 1.5 and the loss angle remains constant up to the maximal piezoelectric activity. In our experiments, the favorable behavior of the material’s dielectric properties translated into an optimal performance of AlScN based energy harvesting and sensing MEMS at 27% Sc. Here, the sensing FOM has increased by a factor of 1.7 and the harvesting FOM by a factor of 3.2. By varying pressure and Ar/N2 ratio during deposition, we were also able to control film stress over a wide range from strongly tensile to strongly compressive.

PIEZOELECTRIC BEATS ELECTROSTATIC Sensing the position of moving parts within MEMS devices typically requires relatively large “electrostatic sensors” but smaller “piezoelectric sensors” would save space and therefore reduce costs. The same is valid for actuation, where piezoelectric materials can introduce significant forces into MEMS enabling new devices with better actuation performance. Work on AlScN at University of Kiel is currently focused on energy harvesting applications where the main goal is to enable an integrated power supply to support wireless MEMS sensors. For Scandium doped AlN, a significant increase in the respective figures of merit (FOM) could be expected. This is especially true for energy harvesting, where the piezoelectric performance increases according to its FOMEH = (e31,Ɛ2)/ (Ɛ Ɛ0). In sensor applications too, where the FOM describes the limit of detection and can be defined as FOMSA = (e31,Ɛ)/(√ Ɛ Ɛ0 tan Δ), a significant improvement could also be expected, as long as the dielectric loss angle delta is controlled.

Fig. 2: (a) top view of 400 nm thick AlN (left) and Al0.73Sc0.27N (right) films (b) AFM recorded topography of the same Al0.73Sc0.27N sample

Fig. 4: Mean and maximal transversal clamped piezoelectric coefficient e31,f, dielectric constant ε and (b) dielectric loss tangent of Al1−xScxN as a function of Sc content

GETTING THE COMPOSITION RIGHT To test this theory, AlScN films were fabricated on standard 200mm wafers with Sc content of up to 37% on top of a platinum bottom electrode using an Evatec MSQ 200 Multisource installed on CLUSTERLINE® sputtering tool. Precise control of Sc concentration over such a large range was made feasible by the possibility of co-sputtering from two pulsed DC-Cathodes with varying power. At concentrations up to 27% Sc, our XRD measurements showed that films of a constant good quality could be deposited revealing exclusively polar texture (Fig. 2) as well as narrow Rocking-Curve (Fig. 3).

Fig. 3: X-ray diffraction patterns for samples with varying Sc content from x=0 to x=0.37 and (b) corresponding rocking curve

SEM and AFM imaging also confirmed a uniform surface structure [Fig2.]. Above this concentration however, the crystalline quality started to decrease, with barely any polar contribution observed at 37% Sc. Coinciding with these observations, the measured transversal piezoelectric coefficient e31,f peaks at 27% Sc with 3 C/m² [Fig 4], corresponding to a significant increase by a factor of 2.4.

BUT THAT’S NOT THE WHOLE STORY Of course, the deposition and characterization of feasible AlScN layers is only one link of a chain for successful process integration. Issues related to reliability, etching, stress control and compatibility to other processes are also of great importance and our work goes on in collaboration with the Fraunhofer ISIT for better understanding of these topics to provide better AlScN based MEMS devices in future.

“So Is AlScN the solution? - just watch this space to find out!”


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Delivering perfectly tailored magnetic films Senior Scientists R&D, Hartmut Rohrmann and Dr. Claudiu Valentin Falub, talk about the features at their disposal on the LLS EVO II for the process engineering of soft magnetic thin film properties. They present results using Evatec’s new Aligning Magnetic Field Technology with case studies for CoZrTa/Al2O3 and CoFeB/Al2O3 laminated films. The miniaturization and rapid performance improvement of electronic devices for RF communications at high and ultrahigh frequencies from a few MHz up to several GHz has paved the way for micro-magnetic devices such as inductors and transformers based on thin films. Both miniaturization and performance could be further improved by using cores based on soft-magnetic materials. The term “soft-magnetic” refers to the fact that the lowest possible effort is required to switch between magnetized and de-magnetized states. In the absence of an external magnetic field, the magnetization – the vector field that expresses the density of magnetic dipoles – should orient along an easy axis. While the coercivity (Hc, the field to reverse the magnetization along the easy axis) should be as low as possible, the anisotropy field (Hk, the field to reverse the magnetization perpendicular on the easy axis) should be tuned by the process conditions depending on the desired application (i.e. operation frequency) and the choice of soft magnetic material. Thus, by matching the maximum possible magnetization, so called saturation magnetization (4πMs), defined by the magnetic material itself, and the Hk, one is able to adapt to different requirements. The third item is a proper orientation of the easy axis (preferred direction of magnetization).

Such configuration results in both deposition under oblique incidence as well as textured seed and intermediate layers. In addition we have now introduced an aligning magnetic field that is applied during the deposition itself.

THE QUEST FOR THE IDEAL SOFT-MAGNETIC PROPERTIES There’s a number of perquisites to achieve ideal soft-magnetic properties. The choice of a magnetic alloy with low crystalline magnetic anisotropy and magnetostriction, a low film stress and small crystallites of a size below the width of magnetic Bloch walls proves to be essential for reducing the hysteretic loss. While small crystallites result from low deposition temperatures and high rates, the controlled use of reactive gas is also decisive. The alloy composition itself requires a small amount of amorphisation atoms such as B, Zr, Al or Si. We can also use seed magnetic layers to induce a favorable microstructure (e.g. CoFe on NiFe), or intermediate laminating layers (e.g. AlN, Al2O3, SiO2, etc.) to stop the crystallite growth. To influence the anisotropy energy Ku (and anisotropy field Hk), we can control the degree of pair ordering by controlling the angular distribution of the deposited material using temperature, sputter pressure, sputter power and bias.

MAGNETIC ALIGNMENT ON THE LLS

Hard magnetic material

Soft magnetic material

Anisotropies in different crystallographic directions

The LLS EVO II is a well established industrial deposition platform to achieve and tailor magnetic anisotropies using the geometries related to its unique concept in conjunction with a collimator.

While the use of oriented seeds, interface layers and collimators was introduced a while ago, Evatec’s latest feature achieves the required pair ordering through the application of an aligning magnetic field. Since the shadowing effects normally exhibited for deposition with linear collimator are no longer a concern, we can boost the sputter rate of the soft magnetic material by a factor of ~2.5 with respect to the case of a collimator with an aspect ratio of 1:1. The newly developed aligning magnetic field has already proven stable and easy to handle in industrial applications and is a powerful tool for tailoring the magnetic properties during deposition.


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COMPETENCES IN MEMS

CHOOSING THE RIGHT MAGNETIC MATERIALS

HW modification and its respective integration into an LLS EVO (Figure 1):

The soft magnetic material should have high saturization magnetizartion (4πMs) for the high permeability (µ) required to guide the magnetic field efficiently, and a high resisitivity (ρ) to reduce the Eddy current losses. In practice, this is done by laminating the magnetic material with intermediate dielectric interlayers, e.g. Al2O3, AlN, SiO2, Ta2O5, etc. In addition, the material should be compatible with the MEMS (e.g. Cu TSVs) and CMOS technologies (e.g. low deposition temperatures), and exhibit no deterioration upon subsequent annealing steps that might be necessary during device manufacturing. Therefore, magnetic materials of interest are CoZrTa, CoFeB, NiFe and similar amorphous alloys. Amongst these materials CoZrTa and CoFeB are the most promising in view of their high saturation magnetizations of ~1.5 T and ~2 T (the exact values will depend on the exact alloy composition), respectively, and their high electrical resistivity of more than 100 µΩcm.

CASE STUDY NO. 1- CoZrTa/AL2O3 MULTILAYERED FILMS USING THE ALIGNING MAGNETIC FIELD In this study, PM1 module was equipped with a CoZrTa-target, while an Al2O3 target was used in PM5 to deposit the intermediate Al2O3 layers. Around 50 periods of CoZrT(80nm)/Al2O3(2nm) resulted in a multilayer stack of a total thickness of about 4 µm. The magnetic layers were sputtered by a DC process (1 kW sputter power), whereas the Al2O3 interlayers were sputtered by RF plasma (2.5 kW). The applied field during deposition was approximately 100 Gauss, with an angular deviation on 8” wafer of less than ± 0.3º. Typical results achieved including hysteresis curves along the easy and hard axes and distributions of the easy axis and anisotropy field are shown in Figs. 2 and 3. Thus, we obtained a small coercivity field Hc ~ 0.1 - 0.2 Oe, anisotropy field Hk ~16.5 Oe (standard deviation of 3.6%), and a small deviation from the easy axis (< ± 2º).

Figure 2: Typical magnetization curves for the 4 µm thick CoZrTa/Al2O3 soft magnetic multilayer sputtered with the new aligning field (measured by magnetooptic Kerr effect measurements).

Figure 3: Distribution of the easy axis (left) and anisotropy field Hk (right) for a 4 µm thick CoZrTa/Al2O3 multilayer deposited on a 8” SiO2 wafer using the new aligning field. The 8” sputtered wafer was mapped by magneto-optic Kerr effect measurements on a mesh containing 80 points (edge exclusion 30 mm).

CASE STUDY NO. 2- CoFeB/Al2O3 MULTILAYER FILMS USING THE ALIGNING MAGNETIC FIELD In this example, PM1 module was equipped with a CoFeB target to sputter the soft magnetic layers, whereas an Al2O3 target was used in PM5 to deposit the intermediate Al2O3 layers. Around 10 periods of CoFeB(100nm)/Al2O3(4nm) resulted in a multilayer stack of a total thickness of about 1 µm. The process conditions were similar to the CoZrTa/Al2O3 case. Typical hysteresis curves along the easy and hard axes for this soft magnetic material are shown in Fig. 4. Just like for CoZrTa/Al2O3 we obtained a small coercivity field Hc ~ 0.15 - 0.25 Oe, which should lead to very low losses, and for the anisotropy field we got Hk ~26 Oe. Figure 4: Typical magnetization curves for the 1 µm thick CoFeB/Al2O3 soft magnetic multilayer sputtered with the new aligning field (measured by magneto-optic Kerr effect measurements).


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WIRELESS COMMUNICATION

059

Wireless Communication Encompassing the fields of Mobility , Connectivity and Energy Efficiency, Wireless Communication is well on its way to become the future mainstream at the heart of all that we do. HBT devices on GaAs have gained market share over many years but today , the wireless industry with GaN technology and the RF-filters (SAW & BAW) is the strongest growing semiconductor segment by far.

Dr. Reinhard Benz, Head of Strategic Sales and Product Marketing

Evatec plays a major role with evaporation and sputtering in the metallization of III-V devices with advanced lift-off capabilities or co-deposited alloys typically used as heat sink attachments or solder type materials. The biggest success are the RF-filter : SAW, TC-SAW and BAW type filters. The piezoelectric AlN layers deposited in CLUSTERLINE® show excellent film properties including the crystallinity, uniformity and the stress control required for the 8“ production solutions used in FBAR and SMR type wave filters. For SAW technology Evatec’s RADIANCE platform delivers the HD SiO2 processes for temperature compensated devices where the device performance and the stability of the sound velocity depends not only on demanding uniformity, stress control requirements, but just as importantly on the planarization and gap filling.


LAYERS2016

With more than 250 employees focused on applied solid state physics, Fraunhofer IAF is equipped to work at all levels from basic materials research to delivering a fully functioning end device. Dr. Agnė Žukauskaitė and Dr. Vadim Lebedev of Fraunhofer Institute for Applied Solid State Physics IAF give us an insight into their work developing novel technologies in RF- MEMS devices.


COMPETENCES IN WIRELESS COMMUNICATION

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Tomorrowâ&#x20AC;&#x2122;s mobile telecommunications using AlScN


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HIGH FREQUENCY FILTERS BEYOND AlN-BASED BAW DESIGNS Wireless communication is ubiquitous today and will enjoy even more growth in the coming years. The ability to share large quantities of information has lead to an increasing number of standards, for example 3G, 4G, Wi-Fi, GPS, and Bluetooth and according to the big playersâ&#x20AC;&#x2122; roadmaps, the quest for 5G is also now under way. A closer look just at a smartphone reveals several tens of RF-filters to separate the different and very narrow frequency bands from each other. Form factors and low power consumption are major prerequisites for success. Compact micro-electro-mechanical systems (MEMS) are combining established silicon (Si) micromachining technologies with piezoelectric materials such as aluminum nitride (AlN) to produce electroacoustic components for radio frequency filter applications. Despite being

the dominating choice for bulk acoustic wave (BAW) filters, the piezoelectric properties and electromechanical coupling of AlN are limited. Reaching out for higher frequencies (up to 5Â GHz) requires either a change to a new type of structure, its replacement by a new material , or, for the maximum effect we should do both.

ALUMINIUM SCANDIUM NITRIDE AlScN Recent studies show that by alloying wurtzite AlN with cubic ScN we can form a metastable, wurtzite aluminum scandium nitride (AlScN) with superior piezoelectric properties (up to 400% increase in piezoelectric coefficient d33) and better electromechanical coupling kt2. Numerous studies were published to confirm and explain this phenomenon in more detail. At Fraunhofer IAF we see this recent discovery as a potential key to high frequency filters for the next generation of mobile communications.

Figure 1: Examples of different structures with membranes produced at Fraunhofer IAF (a) Top: Schematic drawing of Lamb mode wave resonator, bottom: membrane movement recorded using laser Doppler vibrometry (LDV); (b) Top: piezoelectric microlense, bottom: lense movement recorded with white light interferrometry (WLI).


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COMPETENCES IN WIRELESS COMMUNICATION

LAMB MODE WAVE RESONATORS Surface acoustic wave (SAW) resonators have an advantage in comparison to BAW-filters due to their comb-like interdigital electrodes that make the devices less sensitive to fabrication uncertainties. However, the maximum frequency of operation for SAW devices on the market is limited to 2.5 GHz and the main drawback is incompatibility with Si integrated circuit (IC) technology. To combine the advantages of SAW and BAW we are currently investigating Lamb mode wave resonators (LWR), where a BAW-like membrane forms SAW-like electrodes (Figure 1). The application oriented research on thinmembrane LWR is on the rise, together with rapidly increasing number of reports on new suitable piezoelectric materials and functional devices operating in the lab environment. While the performance of conventional, AlN based LWRs is still limited by the moderate material

constants, the recently reported AlScN-based structures show great potential in overcoming this limitation in the near future. Our main objective for current developments is to confirm that Al1-xScxN layers can improve the RF device performance and reliability. This demands a material with high piezoelectric constants (d33 > 15 pC/N), improved electromechanical coupling (kt2 > 10%), excellent crystal quality, and homogeneous properties over 8” substrates. We are focusing on “market-ready” conditions, cooperating with Evatec in the field of multitarget sputter equipment (Figure 2) and RF-component producers. Current activities are mainly focused on prospective application fields for Al1-xScxN such as RF-electro-acoustic (x>0.25) and piezo MEMS (x>0.4) devices (Figure 1), in order to test the first system prototypes.

Fraunhofer Institute for Applied Solid State Physics IAF, Tullastraße 72, D-79108 Freiburg Dr. Agnė Žukauskaitė | agne.zukauskaite@iaf.fraunhofer.de Dr. Vadim Lebedev | Mail vadim.lebedev@iaf.fraunhofer.de www.iaf.fraunhofer.de

Figure 2: Multisource sputter tool by Evatec: 8” multi-target system used for growth of novel piezoelectric materials at Fraunhofer IAF. Inset (bottom right) – sputter process from two targets for growth of compounds, such as AlScN.


LAYERS2016

Driving up productivity for advanced thin film resistor and backside via metal stacks for Wireless applications A batch processing approach brings many advantages like low temperature processing for compound semiconductor applications but the industry also cant afford to miss out on the advantages of automated wafer handling of cluster platforms with cassette -tocassette operation. Dr. Reinhard Benz, shows how Evatec’s III-V customers can now have the best of both worlds.

BATCH PROCESSING AT LOW TEMPERATURES IMPROVES PRODUCTIVITY In addition to the throughput advantages of batch-type equipment for smaller substrates, there are several good reasons for batch processing in the manufacturing of RF-devices like switches, power amplifiers based on HBT using 4“ and 6“ GaAs wafer or RF-SAW filter. The significant higher productivity achieved is a result of the very moderate temperature regime in a smaller temperature band which allows much faster processes for all type of temperature critical metallization processes like PR for lift-off processes or all wax-bonded type wafers on carriers. A seed layer of typically TiW-Au or TiWCu for backside via is a good example of a wax – bonded thinned GaAs wafer on a a sapphire carrier where the max temperature during procesing needs to stay below 100°C. Fig 1 shows the throughputs achievable for different stack recipes. The seed layer needs to meet

certain sidewall and bottom coverages for a successful plating step. Thanks to the superimposed RF/DC sputtering, the step coverage of typ via with A/R of 1:3 or up to 1:5 are 10% - 15% and can be further increased by using additional RF-bias applied on the chuck.

RADIANCE OFFERS BATCH PROCESSING IN A CLUSTER ARCHITECTURE The RADIANCE (Fig. 2) loads an entire batch on a turntable and processes all the wafers at the same time on actively cooled chucks, with the benefit that the single wafer sees the active back gas cooling most of the time during one loop and the heat load from the sputter source only shortly. These smooth thermal cycles mean that prcocesses below 90°C can be achieved easily while still maintaining maximum deposition rates for the highest throughput. Compared to standard 6“ single wafer cluster type sputtering the throughput of RADIANCE can be up to 200% higher for temperature limited processes.

Similar throughput advantages can also be achieved using RADIANCE for Thin film-Resistors like TaN in RF-devices. In this case we can engineer the process to control stress (±200MPa), TCR (<100ppm/K) and finally tune resistivity uniformity to values typically <1.5% (maxmin) on 6“ wafers according to Fig 3. Key factors for success are the process stability and smooth temperature cycles achieved during batch processing. Fig 3: Sheet resistance uniformity of TaN TFR on 6” wafer

“std. dev” Unif: 0.57% “max min” Unif: ±1.14%


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COMPETENCES IN WIRELESS COMMUNICATION

Fig 1: Low temperature seed layer production throughput on RADIANCE

THROUGHPUT ACCORDING TO STACK DESIGN WTi - film Au - film

1’500Å 3’000Å

1’500Å 3’000Å

1’500Å 1’500Å

Dep. time WTi-Au

37.0

25.5

17.5

Etch time SPM

16.0

16.0

16.0

Run time total (min)

46.3

34.8

26.8

26

35

45

15’600

20’800

27’000

Wafer / hour Wafer / month

RADIANCE DELIVERS MORE FOR COMPOUND SEMICONDUCTOR PROCESSING Beside the productivity benefits of course, there are other reasons why RADIANCE is already now well established at major III-V manufacturers: ƒƒ Handling and processing of 150mm GaAs and 159mm sapphire substrates at the same time without any tool-reconfiguration ƒƒ Pre- and/or post treatment steps like a clean-etch step (ICP) possible in a seperate single wafer process module on the same platform ƒƒ The possibility to use a fully integrated optical thickness monitoring system (GSM) for repeatability accuracy of much better than <1 % for HD-SiO2 using closed loop process control ƒƒ In situ plasma-emission-monitoring (PEM) for increased deposition rate and process stability control in reactive sputter processes operating in the transition regime close to metallic mode ƒƒ Secure handling of temperature sensitive or very brittle substrates e.g. LiNb used for RF-SAW filters.

RADIANCE – READY FOR THE CHALLENGES OF THE FUTURE

Fig 2a. Batch Process Module with up to 5 sources

Fig 2b. Turntable for BPM with water and gas supplies for backside cooling

III-V manufacturing is turning more and more to standards set by the Silicon industry when it comes to production robustness for improving yield and productivity in high volume manufacturing. Evatec’s RADANCE is ready to solve the challenge of securing the tight binning of the device parameters and achieving new throughput levels at the same time.

“RADIANCE delivers new levels of productivity in RF devices”


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067

OPTOELECTRONICS

Optoelectronics

Evatec has enjoyed huge success in Optoelectronics over the last 6-8 years working with the industry & technology leaders in US, EU and in close partnerships with key volume LED manufacturer in Asia. Our equipment & process solutions cover the complete range of LED technologies in production today, all the way from sapphire on 2“ - 6“ to fully automated evaporation & sputter processes for 8“ GaN on Si.

Dr. Reinhard Benz, Head of Strategic Sales and Product Marketing

We deliver sputtering and evaporation equipment used for ITO, metal electrodes, optical reflectors including complex DBR stacks. New additional high performance sputter solutions now mean extended cost effective production solutions for the AlN buffer layer on flat or patterned saphire prior to epi GaN and the SiO/SiN layers required for final packaging. In a hugely competitive market, our focus remains on increased productivity and yield for our customers from new TCOs for higher light utilization and better electrical properties to the capturing of more light by improved reflectors.


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Boosting LED efficiency with high performance current spreading layers and DBR mirror coatings Both the current spreading layer as well as the mirror contribute substantially to the achievement of high efficiencies in LED devices. Dr. Silvia Schwyn Thoeny explains the choice of deposition techniques and the importance of adapting thin film processes to LED chip design.

After the adoption of LED lighting for backlight units in LCD laptop and television screens, the growth of the market for white LEDs is now mainly driven by general illumination, where LEDs are about to replace the incumbent technologies of incandescent and fluorescent light bulbs and tubes. Deployment of LEDs into these applications is triggered by their major contribution to energy saving, longevity and versatility in terms of design flexibility and color tuning. Both the current spreading layer and mirror contribute substantially to the achievement of high efficiencies in LED devices. Transparent conductive indium-tin oxide (ITO) is widely used in III-nitride light emitting diodes (LEDs) serving functions requiring different ITO properties making it essential to optimize material parameters and overall chip design simultaneously.

DEPOSITING THE RIGHT ITO Evatec electron beam evaporation processes for ITO in a BAK evaporator are already proven in mass production for LEDs, but there is also a strong demand to replace this process by magnetron sputter deposition. The main advantages are a reduced batch time, since in sputtering no heat step is required and simplified integration of automatic wafer handling. The big challenge with sputtering however is to avoid crystal damage of the GaN substrate due to the energetic atoms and ions present in the sputtering plasma. Extensive process optimization on Evatecâ&#x20AC;&#x2122;s RADIANCE sputter platform was necessary to identify the most suitable process conditions. In a first step, we were able to establish damage free deposition conditions using research grade LED material in a collaboration project with the institute LASPE at the Swiss Federal Institute of Technology in Lausanne. Comprehensive characterization of those films showed low electrical resistivity, high transparency and a work function in the range of 5.2 eV. Thus, tunnel contacts to p-GaN could be formed with a low barrier height in the range of the standard metals used to form the p-contact. Indeed, the devices,


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COMPETENCES IN OPTOELECTRONICS

THREE REASONS TO CHOOSE ITO FOR CURRENT SPREADING LAYERS 1. ITO serves as a contact to p-GaN, with a work function as high as the best metal contact materials

2. Optical losses caused by reflections of the emitted light at the metal-semiconductor interface can be avoided by substituting the metallic electrode by ITO

which were fabricated using these ITO layers showed operating voltages (Vf) as low as reference devices with e-beam deposited ITO and even comparable to devices with standard metallic p-electrodes.

Fig. 1 DBR mirror with excellent reflection over a wide range of indidence anlges at the LED emission (450nm)

However, numerous customer samplings showed that that there is no ONE best condition for depositing ITO layers. Within the parameter space of damage free coating the ITO needs to be tailored to the specific design and doping of the LED. As a general rule the conductivities of p-GaN and ITO need to match for perfect current spreading. If this is the case, competitive / state of the art low operating voltages and high output power can be obtained. Furthermore, annealing of the LEDs, which will be performed at a later stage in the manufacturing chain, will influence the ITO properties and thus has to be taken into account as well.

3. ITO provides uniform current spreading in an LED die

CHOOSING THE RIGHT HIGH REFLECTANCE MIRRORS The mirror on the backside of the LED is an additional key element for excellent energy efficiency of the LED. Light generated in the active region of an LED is evenly emitted in all directions, hence also to the backside of the device. Without a mirror on the back surface of the device half of the light would be lost. In LED terminology this mirror is referred to as a Distributed Bragg Reflector (DBR). There are different schemes of design for this mirror, spanning from metal to metal-dielectric and dielectric only mirrors. A typical example is seen in Fig1. The complexity of the mirror rises in the order they are mentioned, but so does the performance, i.e. the level of reflectance and the wavelength range for which high reflectance can be obtained. The type of mirror used is specific to the LED design and are defined by the LED manufacturer. In this application Evatec benefits strongly from its long standing expertise in deposition of such optical interference coatings requiring techniques for control of film thicknesses in the nm range with high precision. The BAK Evaporator and both the MSP and RADIANCE sputter platforms can be equipped with optical monitoring technology for precise thickness control of layer thicknesses. The highly dense and shift free layers required are obtained by plasma assist naturally present in sputtering processes and by using the high performance plasma source in evaporation processes. Just like for ITO, the choice of system and technology finally depends on the customerâ&#x20AC;&#x2122;s production environment, the required throughput and the degree of automation of substrate handling.

WORKING IN PARTNERSHIP IS KEY TO SUCCESS In conclusion, samplings are of utmost importance to match the ITO and DBR to the specific LED material. Evatec applications specialists are here to assist customers to identify the optimal conditions. With this approach, we manage to deliver unsurpassed performance and are proud to see our tools for ITO deposition and DBR mirror coatings on the production floor of world leading LED manufacturers.


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Innovation in HBLED production using PVD of Aluminium Nitride Dr. Dominik Jaeger shows how AlN Nanosmooth™ deposition by PVD on flat sapphire (FS) and on patterned sapphire substrates (PSS) prior to epi GaN growth can be a successful alternative to MOCVD of AlN for HB-LED production. Light emitting diodes (LEDs) with a high brightness (HB) require a high light extraction efficiency (LEE) and high internal quantum efficiency (IQE) of the device. Patterned sapphire substrates (PSS) are often used as a substrate for HB-LEDs since PSS improves the LEE and the IQE. Within a HB-LED a stack of highly crystalline layers forms the active region where photons are created and the light is emitted. This stack is called a multi quantum well (MQW) and contains metalorganic vapour phase epitaxy (MOVPE)-GaN layers. In order to obtain a high IQE it is essential to grow defect free GaN-MQWs, since defects in the crystal cause both photon scattering and absorption.

Figure 1: SEM image of a cross section of a patterned sapphire substrate (PSS).

Patterned substrates typically have an array of cones that are separated by a few micrometers (see Figure 1). Light is refracted when passing through an interface. The diffraction depends on the refractive index and the angle of incidence. PSS have both an enhanced surface area and tilted cones, resulting in a change of the angle of incidence, and hence allow higher LEE compared to the flat substrates.

Additionally the patterned structures reduce the threading dislocations density (TDD) in the GaN MOCVD process [Shin2007]. Adding an AlN layer to the PSS allows for a further defect reduction [Lee2014] and wavelength binning [Preble2011]. This results in a 5-15% increase in LED brightness for AlN films on patterned structures compared to plain structures [Preble2011].

GaN GROWTH HABITS ON PSS Different growth types of GaN on PSS are known [Shen2011], e.g. side-wall growth or bottom growth (Figure 2). The growth type depends on the substrate properties (e.g. roughness and pattern geometry), GaN MOCVD process parameters and, if used, on the AlN film properties. In the case of a side-wall growth (Figure 2a) the crystals grow on the cone sides in multiple directions until they touch each other. This results in a high TDD and a rough, hazy GaN surface. This polycrystalline GaN material is not suitable for HB-LEDs. In order to obtain a defect free crystalline GaN structure it is essential that the GaN growth occurs only at the bottom (groove growth, Figure 2b). The combination of a vertical and horizontal GaN MOCVD-growth allows for nearly defect free GaN structures.

CONTROLLING THE GaN GROWTH HABIT WITH AlN PVD PROCESSES Nanosmooth™ AlN films were deposited on PSS using a CLUSTERLINE® equipped with a carbonheater module, allowing for uniform deposition temperatures of up to 900°C. The quality of the AlN film deposited is critical - resulting in either in a side-wall growth (Figure 3) or a purely groove growth (Figure 4) under the same GaN MOCVD conditions.


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COMPETENCES IN OPTOELECTRONICS

Figure 5 (left): Excellent temperature distribution with carbon heater achieved

a)

b)

Figure 2 (above): side view sketch of a thin AlN film (black) on PSS (grey) covered with GaN (orange) with two growth types: a) side-wall growth and b) groove growth. Figure 3 (right-top): top view of GaN growing on the sidewall of the structure of an AlN PSS template. GaN was colored in orange on one cone for a better illustration. Figure 4 (right): top view of GaN purely growing in the grooves of the structure of an AlN PSS template. GaN was colored on the top left side of the image for a better illustration.

Due to the low lattice mismatch between Al2O3 and AlN, growth is epitaxial on c-oriented sapphire surfaces. The AlN lattice is strained due to the epitaxial growth (Koehler stress) and also due to thermal expansion (thermal stress). XRD measurements show that the lattice distance of AlN is influenced by the deposition temperature and the film thickness [Kong2015]. The deposition process has to be fine tuned in such a way that the AlN film deposited at the PSS is highly crystalline in the PSS grooves and at the same time of poor quality at the side-walls of the cones. Modifying the AlN growth process allows us to control growth of the GaN only in the grooves and not on the sides (Figure 4).

CLUSTERLINE® IS READY PVD of AlN on CLUSTERLINE® is an ideal precursor to the subsequent groove growth of GaN by MOVCD essential for the successful manufacture of HBLEDs. The CLUSTERLINE® platform is ready to process 2, 4, 6 and even 8 inch substrates using carriers or direct substrate handling at typical throughputs of up to 432 x 2 inch wafers per hour according platform configuration.


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073

HP OPTICS

High Precision Optics There is a reason why we call the 21st century the century of the photon. Widely used in recent decades, photonics offers an incredible potential for the years to come. The capability to generate, transmit and utilize light or other electromagnetic radiation enables countless applications in Health, Communication, Information, Security, Mobility, and Energy.

Maurus Tschirky, Senior Manager Product Marketing

At the heart of all this is Optics, and in particular optical coatings. Despite being modest in appearance, they are indispensable and to be found everywhere. The very origins of optical coatings go back to the Germany of the 19th century but in 1946, a new hotspot was added to the global landscape. The village of Balzers in the Principality of Liechtenstein became synonymous with competence in coating. Evatec embraces new innovations in traditional freeform optics, but our expertise in microelectronics means we are also well prepared for new challenges. Today’s markets require a convergence of optics and microelectronics, where optical coatings are integrated on silicon wafers. Evatec’s Optical Toolbox offers the means to master these challenges with its Broadband Optical Monitoring, Plasma Emission Control and “in situ” Reoptimisation Algorithms. With our Batch, Cluster or Inline tools and the availability of both evaporation and sputtering, Evatec is well positioned to write new chapters in the story started just across the Rhine in Balzers over 70 years ago.


LAYERS2016

Optical Interference Coatings

Where Semiconductor meets Precision Optics Optical Interference Coatings are the enablers in many of todays mass market applications. Dr. Silvia Schwyn Thoeny explains how the challenge of achieving high precision and high throughput using sputter can now be solved with the latest developments in cathode and control technologies but why offering different handling approaches on tools like MSP and RADIANCE is still essential.


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COMPETENCES IN HP OPTICS

A WORLD FULL OF OPTICAL INTERFERENCE COATINGS (OICS) From the Head Up Displays (HUD) in our cars, to the high resolution cameras and proximity sensors in our smart phones, we live in a world reliant on the cost effective mass production of high precision optical coatings. But whether its for transparent current carriers and mirror coatings on HBLEDs, or the large area AR coatings for satellite communications, the thin film deposition tool architecture including handling and substrate tracking needs to fit the rest of the production line. In some cases this means adopting the batch approach traditional in many optical applications but in others it means delivering optical layer qualities on cluster platform architectures compliant with semiconductor standards.

CATHODE TECHNOLOGIES FOR OICS

COMPETENCE IN OPTICAL SPUTTER IS THE FOUNDATION Whichever platform fits the fab concept, dedicated cathode technologies combined with Evatec’s Advanced Process Control Techniques for optical layers is the starting point for achieving the precision and yield required in volume production.

PLASMA EMISSION MONITORING

BROADBAND IN SITU OPTICAL MONTORING RE-OPTIMISATION Process Start

1. Layer deposition

The reoptimisation loop

2. Check spectrum

3. Recalculate remaining layers or continue without changes

ƒƒHigh uniformity deposition across ƒ 8 inch in sputter down mode ƒƒElimination of shapers for reduced particles and higher rates

ƒƒHigh uniformity vertical sputter deposition ƒƒElimination of shapers for reduced particles and higher rates

ƒƒPerfect film stoichiometry ƒƒHighest deposition rate for reactive sputter processes

ƒƒCorrect layer thicknesses in complex optical stacks ƒƒDirect substrate measurement in reflection

ƒƒAutomatic tuning of the thin film recipe during deposition ƒƒNarrower process tolerances and higher yields

BATCH OR CLUSTER? Where manual handling and batch processing fits the production philosopy or where large substrate handling is required, the MSP batch coater with its drum architecture is the tool of choice- handling individual substrates up to 560X380mm. The system is perfect too where “large area coat and cut” is the preferred route and its flexible tooling systems also make for simple low cost conversion between different substrate sizes and thicknesses on a regular basis. Integrated plasma source technology enables the implementation of hard ( DLC) or antismudge coating processes required to protect the screens on our tablet and

Process End

smart phone displays or the deposition of thicker coatings with good surface quality and controlled stress in some of the most complex optical stack designs. In new wafer level approaches for optoelectronics however, fabs want to coat directly on the silicon wafer rather than on glass. The overall manufacturing process can be simplified and costs driven down by elimination of cleaning, alignment and glass/ wafer bonding steps but processes need to run on “semi” standard equipment like RADIANCE with automated wafer handling and tracking.


LAYERS2016

Fig 2: Production of NIR bandpass filters for 3D Sensing & Gesture Recognition applications Bandpassuniformity uniformity Bandpass

Evatec’s 20 layer design SiO2/aSi

100.00

Normalized thickness [%]

99.80 99.60 99.40 99.20 99.00

Uniformity <±0.25%

98.80 98.60

edge 1 x-axis

98.40 98.20 98.00 0

20

40

60

80

100

120

140

160

180

200

Position on wafer [mm]

Fig. 1 shows the typical characteristics of the MSP with its manual handling approach and the RADIANCE with its cluster architecture. For the next generation of smart devices too incorporating new 3D Sensing & Gesture Recognition technologies the mass production capabilities that automated cassette to cassette tools offer are a must. Thin 8 inch glass substrates have to be handled, coated and flipped without operator intervention. The combination of a cluster architectures with automated and batch processing capability using dedicated high rate sputter sources on RADIANCE sputter cluster offers the layer qualities and repeatabilities required to meet the yield targets for deposition of high performance NIR bandpass filters. Fig. 2 shows the typical uniformity expectations across an 8 inch wafer to be achieved in mass production.

Fig 1:

MSP

RADIANCE

ARCHITECTURE

ƒƒBatch processing ƒƒManual Loading

ƒƒCluster architecture ƒƒCassette to cassette handling

SUBSTRATE CAPABILITIES

ƒƒCarrier system for wafers, glass

ƒƒDirect wafer up to 8inch including auto alignment ƒƒCarriers for minbatches ƒƒEdge grip or full face deposition

SOURCE TECHNOLOGIES

ƒƒUp to 6 DC Sputter ƒƒPlasma source for preclean or PIAD

ƒƒUp to 4 DC, RF, Mixed Sputter sources ƒƒPlasma source for preclean ƒƒMultisource for codeposition

PROCESS CAPABILITIES

ƒƒTCOs, metals, dielectrics

ƒƒTCOs, metals, dielectrics

KEY FEATURES

ƒƒLow temperature processing ƒƒSubstrates up to 560mm x 380mm

ƒƒLow or high temperature processing up to 800ºC ƒƒAuto wafer flip for double sided processes without vacuum break ƒƒIn situ metrology ƒ e.g. stress ƒƒPre and post treatment including vacuum anneal and cool

Gesture recognition technology is coming to our mobile devices soon


COMPETENCES IN HP OPTICS

077

RADIANCE batch module with up to 5 sources

THE MARKET FOR OICS GROWS AND GROWS While we cant be sure if it’s for 3D imaging in our next generation smart phones or for headup display technology in tomorrow’s spectacles, the one thing we can be sure of is that the demand for efficient mass production of high quality optical interference coatings will continue to grow.


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Innovation in small batch manufacturing Optical coating manufacturers face two opposing trends. On one hand, coated optics for consumer products demand highest throughput and the largest area coated in a short time. On the other hand, the need for small batch processing is also growing for special filters, lenses that go into lab applications, rapid prototyping, or for coating small substrates like microscope objective lenses or endoscope optics. Senior Scientist Dr. Stephan Waldner talks about highly flexible, efficient coating solutions for small batch sizes. NEW IDEAS FOR THE BAK EVAPORATOR Today’s precision optics coating tools are usually equipped with two e-guns to rapidly switch between high- and low-index material. This avoids the coating material cooling down and having to melt it again for the next layer. An ion source for plasma ion assisted deposition has also become a standard to obtain excellent layer properties without the need for high temperatures. Furthermore an optical monitor is essential to reproducibly realize optical coatings within tight tolerances. All these components limit the possibility of miniaturizing the coating chamber and often only a small portion of the available area on the calotte is loaded with substrates for small batch size products. In cooperation with a customer Evatec followed a different approach: A BAK761 box coater was equipped with a dome and a special moveable mask. This mask covers up to 7/8 of the dome and therefore exposes only a part of the substrates to the coating process. When this process is finished, the mask is moved automatically to a different position such that another part of the substrates is coated in the next process run. Furthermore the dome holds flip tooling segments which allows for double-sided coating processes. In this way, a sequence of up to 8 batches of different double-sided coating processes can be run without venting the coating chamber. This eliminates the time needed for venting, pump-down, handling and – depending on the process – also heating and cool-down. For coatings with only a few


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COMPETENCES IN HP OPTICS

layers like anti-reflective coatings this time-saving is considerable.

Fig. 1

RADIANCE SPM OPTICS The second tool targeted at small batch size production is the RADIANCE SPM Optics sputter tool. It is equipped with 2 or 3 sputter sources, a load lock, direct broadband optical monitoring in reflectance or transmittance mode as well as plasma emission monitoring (PEM). This PEM ensures that reactive sputtering is performed with very low absorption and at high deposition rates at the same time. The rotating substrate holder allows placement of a 200mm carrier, which can be flexibly designed to hold a broad variety of substrate geometries.

Fig. 2

Pumpdown / heating

N-BK7 glass Frontside AR

Flip

N-BK7 glass Move Backside AR mask

N-SF5 glass Frontside AR

Flip

N-SF5 glass Backside AR

Fig. 3

Colldown / vent

The basic version of the SPM is equipped with a manually operated load-lock. Still, the chambers loading slot is the same as on the larger RADIANCE Batch Process Module (BPM) chambers. This means that the SPM can also easily be combined with an automatic robot and cassette handling system, allowing for scheduling a series of process runs. This makes it possible to run the tool around the clock without the presence of an operator. This compact sputter tool was exhibited and running at the Laser – World of Photonics 2015 fair in Munich, producing Nb2O5/SiO2 coatings with excellent reproducibility even under the conditions of a crowded exhibition hall.

GSM1101 BROADBAND OPTICAL MONITORING IS KEY A key component for both small batch systems is the broadband optical monitor GSM1101. While light source, spectrometer, and electronics are integrated in a rack-mounted unit, fiber optic cables bring the light to and from the coating chamber. This allows for flexible and space-saving integration in different chamber geometries.

Fig. 4

The Advanced endpoint detection algorithms, the seamless integration with the coating controller and the optional in situ reoptimization of the coating design allow for a fast setup of new coating recipes as well as a safe and reproducible switching between existing recipes without any test runs.

“Small batch processing can be efficient too” Fig. 1: A BAK761 evaporator equipped with flip tooling and a moveable mask. Up to 8 double-sided coating processes can be run without venting the chamber.

Fig. 2: With the flip tooling and movable mask, different coatings can be deposited in a sequence without intermediate venting of the chamber. The example process flow shows front-and backside coatings on two different glass types.

Fig. 3: Transmission measurement of three coating runs of a 31 layer green filter, deposited on the RADIANCE SPM Optic

Fig. 4: The GSM1101 broadband optical monitor: light source, spectrometer and electronics are integrated in a compact unit. Optical fibers connect the GSM with the coating chamber which yields maximum flexibility.


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