Esquema elétrico LA 9902 P by Diego Andrade

Compal Confidential G400S/G500S UMA M/В Schematics Document Intel Ivy Bridge Processor with DDRIII + Panther Point PCH

LA-9902P 2013-05-06 REV:1.0

C o m p a l E le c tro n ic s , In c.

C o m p a l S e c re t D ata 2011/06/15

Issued Date

D e c ip h e re d Date

2012/07/11

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C

Title

SCHEMATIC M/В LA-9902 |sOust. n Document Number " 4019N1 W ednesdav.Mav08.2013

__________________________ 1_______________________________ Ū___________________________ _ L _

ISheet

*ev в 52

Voltage Rails

BOARD ID Table +5VS +3VS + 1 . 5 VS + V 1 . 05S_VCCP +V C C _C O R E +V G A _C O R E +VCC_G FXCO RE_AXG + 1 . 8VS

Board ID 0 1 2 3 4 5 6 7

PCB Revision 1.0 0.3 0.2 0.1

-- — __ __ SIGNAL STATE -- ----Full

SI (Power On

Suspend,)

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

+VALW

+VS ON

Clock ON

HIGH

LOW

HIGH

LOW

HIGH

OFF

(S u s p e n d t o R A M )

LOW

(Suspend

LOW

HIGH

OFF

( S o f t OFF )

LOW

OFF

to D i s k )

Board !D table for AD channel

+ 0 .7 5 V S + 1 . 0 5 VS

Vcc Ra B o a r d ID

3.3V 100K +/-

Vu3 BID

12K +/-

15K +/-

20K

+/-

m -*-n

0 V 0.347 V 0.423 V 0.541 V

_b i d

0 V 0.354 V 0.430 V 0.550 V

max V V V V

a d _b i d

0.300 0.360 0.438 0.559

EC 0x00 OxOC OxlD 0x27

AD -

OxOB OxlC 0x26 0x30

MP PVT DVT EVT

Address

инею

EC SM Bus2 address

Device Sm art B attery

USB 2.0 Port

X EC SM Busi address

Device 0001 01IX b

Address

Therm al Sensor

UHCI1

1001 lOOxb

EHCIl U S B 3 .0

PCH SW1 Bus address Address

DDRDIMM0

1010 OOOXb

DDRDIMM2

lOIOOIOXb

UHCI4 EHCI2

NV-GPU SM Bus address Address

Internal thermal sensor

1001 I l l X b (0x9E)

S M B_EC _C K1 S M B J C .D A l S M B_EC _C K2 S M B_EC _D A2

KB9012 +3VALW KB9012 +3VALW

SM BCLK SM B DATA

PC H +3VALW

S M L0C LK S M L0D A TA S M L1C LK SM L I DATA

PC H +3VALW

VGA

ВАТТ

KB9012

S O D IM M

W LAN

T h e rm a l S ensor

+3VALW

VGA

PC H + 3 V A L W + 3 VS4

G A

0 1 2 3 4 5 6 7 8 9 10 11 12 13

3 External USB Port USB Port (Left Side)osB3.o

USB Port (Left SidepsB3 о Touch Screen USB Camera

U SB /B (R ig h t Side U SB 2.0)

Mini Card(WLAN) Card Reader

PCH

f3VS

UHCI5 UHCI6

Device

SOURCE

UHCI2 UHCI3

Device

BOM Structure Table

USB Port Table

BTO Item BOM Structure 45 LEVEL 45@ Connector МЕ0 140 For VILG2 (14") For VILG1 (15") 150 HDMI HDMI0 Camera CMOS0 LAN LDO Mode LDO0 LAN Switch mode SWR0 81620 10/100 LAN(AR8162L) 81720 10/100 LAN(QCA8172) Green clock(DIS sku) GCLK3O40 Green clock(UMA sku) GCLK2440 Green elk support GCLK@ No Green elk support NOGCLK6 Touch Screen SKU TS@ Optimus SKU OPT0 UMA SKU UMA0 PCH(NM70 sku) NM7O0 PCH(HM70 sku) HM7O0 PCH(HM76 sku) HM7 6@ V R A M (1000MHz) 1OOOM0 V R A M (900MHz) 900M@ Unpop @

Compal Electronics, Inc. Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN ■ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC M/В LA-990:! Document Number

4019N1

Wednesday, May 08. 2013

[Sheet

+V1.05S_VCCP

JCPU1A

<16> <16> <16> <16>

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

B28 B26 A24 B23

<16> <16> <16> <16>

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

<16> <16> <16> <16>

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

<16> <16> <16> <16> <16> <16> <16> <16>

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

<16> <16> <16> <16> <16> <16> <16> <16>

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 <16> <16>

G21 E22 F21 D21 G22 D22 F20 C21

A21 H19 E19 F18 B21 C20 D18 E17 A22 G19 E20 G18 B20 C19 D19 F17 J18 J17

FDI_FSYNC0 FDI_FSYNC1 FDI_INT

H20

FDI_LSYNC0 FDI_LSYNC1

J19 H17

<16> <16> <16>

DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3]

FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] FDI0_FSYNC FDI1_FSYNC FDI_INT FDI0_LSYNC FDI1_LSYNC

R7 24.9_0402_1%

PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO

DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3]

DMI

B27 B25 A25 B24

eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms

EDP_COMP eDP_HPD

A18 A17 B16 C15 D15 C17 F16 C16 G15 C18 E16 D16 F15

eDP_COMPIO eDP_ICOMPO eDP_HPD# eDP_AUX eDP_AUX# eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3]

eDP

eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3]

PCI EXPRESS* - GRAPHICS

+V1.05S_VCCP

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

Intel(R) FDI

<16> <16> <16> <16>

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

J22 J21 H22

PEG_COMP

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with max length = 500 mils - typical impedance = 14.5 mohms

PEG Static Lane Reversal - CFG2 is for the 16x

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

1: Normal Operation; Lane # socket pin map definition

CFG2

definition matches

0:Lane Reversed

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25 B

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

TYCO_2013620-2_IVY BRIDGE ME@

Compal Secret Data

Security Classification 2011/06/15

Issued Date

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

4019N1

Wednesday, May 08, 2013

Sheet 1

Rev B of

JCPU1B D

SKTOCC#

+V1.05S_VCCP H_CATERR#

R9 62_0402_5%

<32,37,44>

R15 56_0402_5% 1 2

H_PROCHOT#

<19>

AN33

H_PECI

<32>

AL33

H_PROCHOT#_R

AL32

AN32

H_THRMTRIP#

CATERR#

THERMAL

T48

PECI

PROCHOT#

THERMTRIP#

BCLK BCLK#

DPLL_REF_CLK DPLL_REF_CLK#

SM_DRAMRST#

UNCOREPWRGOOD

SM_DRAMPWROK

100P_0402_50V8J

R29 1 2 PM_DRAM_PWRGD_R 130_0402_5%

R27 10K_0402_5%

C549

PM_SYNC

BUF_CPU_RST#

AR33

RESET#

ESD

3/20 Add (ESD request)

R12 R13

H_DRAMRST#

AK1 A5 A4

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

1 1K_0402_5% 1 1K_0402_5%

+V1.05S_VCCP

H_DRAMRST#

<7>

2 R16 2 R17 2 R18

1 140_0402_1% 1 25.5_0402_1% 1 200_0402_1%

DDR3 Compensation Signals

TCK TMS TRST#

JTAG & BPM

AP33

H_CPUPWRGD 2

<19>

AM34

H_PM_SYNC

PWR MANAGEMENT

<16>

2 2

A16 A15

+V1.05S_VCCP SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PRDY# PREQ# C

CLK_CPU_DMI <15> CLK_CPU_DMI# <15>

TDI TDO

DBR# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

AP29 AP27

XDP_PRDY# XDP_PREQ#

AR26 AR27 AP30

XDP_TCK XDP_TMS XDP_TRST#

AR28 AP26

XDP_TDI XDP_TDO

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7

RP13

1 2 3 4 C

51_0804_8P4R_5% @

T20 PAD

AL35 XDP_DBRESET# AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32

8 7 6 5

XDP_TRST# XDP_TDI XDP_TMS XDP_TCK

T18 PAD T19 PAD

R28

1 1K_0402_5%

+3VS

PROC_SELECT#

A28 A27

T21 T22 T23 T24 T25 T26 T27 T28

PAD PAD PAD PAD PAD PAD PAD PAD

AN34

CLOCKS

C26

H_SNB_IVB#

DDR3 MISC

<19>

MISC

C45 0.047U_0402_16V7K

ESD

TYCO_2013620-2_IVY BRIDGE

+3VALW

ME@

C852 0.1U_0402_16V4Z

+3VS

Buffered reset to CPU +1.5V_CPU_VDDQ C853 0.1U_0402_16V4Z

+3VS B

+3VALW

R30 200_0402_5%

PM_SYS_PWRGD_BUF

R32 75_0402_5%

74AHC1G09GW_TSSOP5 BUF_CPU_RST#

R34 43_0402_1% 1 2

U2 BUFO_CPU_RST#

1 2

3V PCH_PLTRST#

PCH_PLTRST#

<18>

SN74LVC1G07DCKR_SC70-5

PM_DRAM_PWRGD

+3VS <16>

1 R161 2 10K_0402_5%

+V1.05S_VCCP

Compal Secret Data

Security Classification Issued Date

2011/06/15

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev B

4019N1

Date:

Wednesday, May 08, 2013

Sheet 1

JCPU1C

JCPU1D

DDR_A_D[0..63]

<12> <12> <12>

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

<12> <12> <12>

DDR_A_CAS# DDR_A_RAS# DDR_A_WE#

AE10 AF10 V6

AE8 AD9 AF9

SA_CLK[0] SA_CLK#[0] SA_CKE[0]

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_CLK[1] SA_CLK#[1] SA_CKE[1]

RSVD_TP[1] RSVD_TP[2] RSVD_TP[3]

RSVD_TP[4] RSVD_TP[5] RSVD_TP[6]

SA_CS#[0] SA_CS#[1] RSVD_TP[7] RSVD_TP[8]

DDR SYSTEM MEMORY A

C5 D5 D3 D2 D6 C6 C2 C3 F10 F8 G10 G9 F9 F7 G8 G7 K4 K5 K1 J1 J5 J4 J2 K2 M8 N10 N8 N7 M10 M9 N9 M7 AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8 AP11 AN11 AL12 AM12 AM11 AL11 AP12 AN12 AJ14 AH14 AL15 AK15 AL14 AK14 AJ15 AH15

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

SA_ODT[0] SA_ODT[1] RSVD_TP[9] RSVD_TP[10]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

TYCO_2013620-2_IVY BRIDGE ME@

AB6 AA6 V9

DDR_B_D[0..63]

M_CLK_DDR0 <12> M_CLK_DDR#0 <12> DDR_CKE0_DIMMA <12>

AA5 AB5 V10

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

M_CLK_DDR1 <12> M_CLK_DDR#1 <12> DDR_CKE1_DIMMA <12>

AB4 AA4 W9

AB3 AA3 W10

AK3 AL3 AG1 AH1

DDR_CS0_DIMMA# DDR_CS1_DIMMA#

AH3 AG3 AG2 AH2

M_ODT0 M_ODT1

C4 G6 J3 M6 AL6 AM8 AR12 AM15

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

D4 F6 K3 N6 AL5 AM9 AR11 AM14

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

<12> <12>

DDR_A_DQS#[0..7]

<12>

DDR_A_DQS[0..7]

DDR_A_MA[0..15]

<12>

<13> <13> <13>

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

<13> <13> <13>

DDR_B_CAS# DDR_B_RAS# DDR_B_WE#

C9 A7 D10 C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2 J7 J8 K10 K9 J9 J10 K8 K7 M5 N4 N2 N1 M4 N5 M2 M1 AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9 AJ11 AT8 AT9 AH11 AR8 AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15

AA9 AA7 R6

AA10 AB8 AB9

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_CLK[0] SB_CLK#[0] SB_CKE[0]

SB_CLK[1] SB_CLK#[1] SB_CKE[1]

RSVD_TP[11] RSVD_TP[12] RSVD_TP[13]

RSVD_TP[14] RSVD_TP[15] RSVD_TP[16]

SB_CS#[0] SB_CS#[1] RSVD_TP[17] RSVD_TP[18]

DDR SYSTEM MEMORY B

<13>

<12>

SB_ODT[0] SB_ODT[1] RSVD_TP[19] RSVD_TP[20]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

AE2 AD2 R9

M_CLK_DDR2 <13> M_CLK_DDR#2 <13> DDR_CKE2_DIMMB <13>

AE1 AD1 R10

M_CLK_DDR3 <13> M_CLK_DDR#3 <13> DDR_CKE3_DIMMB <13>

AB2 AA2 T9

AA1 AB1 T10

AD3 AE3 AD6 AE6

<13> <13>

DDR_CS2_DIMMB# DDR_CS3_DIMMB#

AE4 AD4 AD5 AE5

M_ODT2 M_ODT3

D7 F3 K6 N3 AN5 AP9 AK12 AP15

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

C7 G3 J6 M3 AN6 AP8 AK11 AP14

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

<13> <13>

DDR_B_DQS#[0..7]

<13> C

DDR_B_DQS[0..7]

DDR_B_MA[0..15]

<13>

TYCO_2013620-2_IVY BRIDGE +1.5V 1

ME@

R38 1K_0402_5% 2

DDR3_DRAMRST#

<12,13>

Q2 LBSS138LT1G_SOT-23-3

R39 4.99K_0402_1%

DDR3_DRAMRST#_R

H_DRAMRST#

<6>

R37 1K_0402_5%

<10,15>

DRAMRST_CNTRL_PCH

R48

DRAMRST_CNTRL_PCH_R

0_0402_5% 1

@ C35 0.047U 16V K X7R 0402

Eiffel used 0.01u Module design used 0.047u

Compal Secret Data

Security Classification Issued Date

2011/06/15

2012/07/11

Deciphered Date

Title

Rev B

4019N1

Date:

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3

Wednesday, May 08, 2013

Sheet 1

CFG Straps for Processor

Interl request AH26 short GND check on EVT phase VCC_DIE_SENSE VSS_DIE_SENSE

RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 RSVD33 RSVD34 RSVD35

VCC_AXG_VAL_SENSE VSS_AXG_VAL_SENSE VCC_VAL_SENSE VSS_VAL_SENSE

AJ31 AH31 AJ33 AH33 AJ26

Need PWR add new circuit on 1.05V(refer CRB)

F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29 J20 B18

J15

VAXG_VAL_SENSE VSSAXG_VAL_SENSE VCC_VAL_SENSE VSS_VAL_SENSE RSVD5

RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23

T13

1: Normal Operation; Lane # socket pin map definition

CFG2

L7 AG7 AE7 AK2

definition matches

0:Lane Reversed CFG4

R42 1K_0402_1%

AT26 AM33 AJ27

T8 J16 H16 G16

CFG4

1 : Disabled; No Physical Display Port attached to Embedded Display Port 0 : Enabled; An external Display Port device is connected to the Embedded Display Port

RESERVED

PAD PAD PAD PAD

PAD

Display Port Presence Strap RSVD37 RSVD38 RSVD39 RSVD40

T14 T15 T16 T17

AH27 AH26

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17]

CFG

CFG4

AK28 AK29 AL26 AL27 AK26 AL29 AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29

PEG Static Lane Reversal - CFG2 is for the 16x

JCPU1E

RSVD24 RSVD25

RSVD27

RSVD_NCTF1 RSVD_NCTF2 RSVD_NCTF3 RSVD_NCTF4 RSVD_NCTF5

RSVD_NCTF6 RSVD_NCTF7 RSVD_NCTF8 RSVD_NCTF9 RSVD_NCTF10

RSVD51 RSVD52

BCLK_ITP BCLK_ITP#

RSVD_NCTF11 RSVD_NCTF12 RSVD_NCTF13

KEY

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

AN35 AM35

CFG[6:5]

AT2 AT1 AR1

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

TYCO_2013620-2_IVY BRIDGE ME@

PEG DEFER TRAINING

CFG7

1: (Default) PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training

Compal Secret Data

Security Classification Issued Date

2011/06/15

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev B

4019N1

Date:

Wednesday, May 08, 2013

Sheet 1

JCPU1F

POWER

8.5A

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24 VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39 VCCIO40

AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12

E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

J23

+V1.05S_VCCP

SVID

R46 75_0402_5%

VIDALERT# VIDSCLK VIDSOUT

AJ29 AJ30 AJ28

H_CPU_SVIDALRT#

R50

1 R47

2 43_0402_5%

1 130_0402_5%

VR_SVID_CLK series-resistors close to VR VR_SVID_ALRT# <44> VR_SVID_CLK <44> VR_SVID_DAT <44>

+V1.05S_VCCP

0.1uF on power side B

VCC_SENCE 100ohm +-1% pull-up to VCC near processor

AJ35 AJ34

VCCSENSE VSSSENSE

<44> <44>

VCC_SENSE VSS_SENSE

R51 100_0402_1% 2

Trace Impedance =27-33 ohm Trace Length Matc < 25 mils

+VCC_CORE

VCCIO_SENSE VSS_SENSE_VCCIO

B10 A10

VSSIO_SENSE_L

VCCIO_SENSE

1 R74 2 10_0402_1%

R74 & R79 put together VSSIO_SENSE_L

<43>

R54 100_0402_1%

<43> 2

SENSE LINES

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100

CORE SUPPLY

AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26

PEG AND DDR

QC=94A DC=53A

+V1.05S_VCCP

+VCC_CORE

+V1.05S_VCCP R79 2 1 10_0402_1%

VSS_SENCE 100ohm +-1% pull-down to GND near processor Compal Secret Data

Security Classification

TYCO_2013620-2_IVY BRIDGE

Issued Date

ME@

2011/06/15

Deciphered Date

2012/07/11

Title

SCHEMATIC M/B LA-9902

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev B

4019N1

Date:

Wednesday, May 08, 2013

Sheet 1

+1.5V

+1.5V_CPU_VDDQ

+VREF_DQ_DIMMA +VREF_DQ_DIMMB

3 D

DRAMRST_CNTRL_PCH

<15,7>

+V_DDR_REFA_R +V_DDR_REFB_R

DRAMRST_CNTRL_PCH 2 G

Q9 LBSS138LT1G_SOT-23-3

R56 82K_0402_5%

AP4800 Id=9.6A

U3 DMN3030LSS-13_SOP8L-8 8 1 7 2 6 3 5

+VSB

Q6 LBSS138LT1G_SOT-23-3 2 G

SENSE LINES

+V_SM_VREF should have 20 mil trace width

+V_SM_VREF_CNT

AL1

R67 1K_0402_1%

2 SM_VREF

1 SA_DIMM_VREFDQ SB_DIMM_VREFDQ

B4 D1

C98 0.1U_0402_10V6K

+V_DDR_REFA_R +V_DDR_REFB_R

R78 1K_0402_1%

VREF

+1.5V_CPU_VDDQ

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

C127 330U_2.5V_M @

1 +

C123 330U_D2_2V_Y

1/16 Change symbol & value from SF000002Z00 to SGA20331E10

1/25 Follow FM-James's comments(Co-lay with C123)

+VCCSA

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8

SA RAIL 1.8V RAIL

C122 10U_0603_6.3V6M

GRAPHICS

+1.5V_CPU_VDDQ

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

C120 10U_0603_6.3V6M

VCCPLL1 VCCPLL2 VCCPLL3

<44>

C119 10U_0603_6.3V6M

B6 A6 A2

VSS_AXG_SENSE R626 10_0402_1%

VCCSA_SENSE

VCCSA_VID[0] VCCSA_VID[1]

VCCIO_SEL

M27 +VCCSA M26 L26 J26 J25 J24 H26 H25

+ C128 @ 330U_D2_2.5VY_R9M

H23

C22 C24

C126 10U_0603_6.3V6M

C132 1U_0402_6.3V6K

C130 10U_0603_6.3V6M

+1.8VS_VCCPLL

AK35 AK34

<44>

C117 10U_0603_6.3V6M

0_0805_5% 2

VAXG_SENSE VSSAXG_SENSE

VCC_AXG_SENSE

C125 10U_0603_6.3V6M

1.5A

+1.8VS R69 1

VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54

POWER

C124 10U_0603_6.3V6M

AT24 AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17 AL24 AL23 AL21 AL20 AL18 AL17 AK24 AK23 AK21 AK20 AK18 AK17 AJ24 AJ23 AJ21 AJ20 AJ18 AJ17 AH24 AH23 AH21 AH20 AH18 AH17

C97 0.047U_0603_25V7K

R616 10_0402_1%

+VCC_GFXCORE_AXG JCPU1G

+VCC_GFXCORE_AXG

Q4 2N7002_SOT23

M3 Circuit (Processor Generated SO-DIMM VREF_DQ) 1

DDR3 -1.5V RAILS

2 G

SUSP

R885 R02 1 2 15K_0402_1%

MISC

1 <36>

RUN_ON_CPU1.5VS3 D

+VCCSA_SENSE

H_VCCSA_VID0 H_VCCSA_VID1

<42>

<42> <42>

A19

TYCO_2013620-2_IVY BRIDGE ME@

IVY Bridge drives VCCIO_SEL low VCCP_PWRCTRL:0 Sandy Bridge is NC for A19 VCCP_PWRCTRL:1

Compal Secret Data

Security Classification Issued Date

2011/06/15

2012/07/11

Deciphered Date

Title

SCHEMATIC M/B LA-9902

Rev B

4019N1

Date:

Wednesday, May 08, 2013

Sheet 1

JCPU1H AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10 AT7 AT4 AT3 AR25 AR22 AR19 AR16 AR13 AR10 AR7 AR4 AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10 AP7 AP4 AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10 AN7 AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10 AM7 AM4 AM3 AM2 AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10 AL7 AL4 AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10 AK7 AK4 AJ25

JCPU1I

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 P9 P8 P6 P5 P3 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34 L33 L30 L27 L9 L8 L6 L5 L4 L3 L2 L1 K35 K32 K29 K26 J34 J31 H33 H30 H27 H24 H21 H18 H15 H13 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29

VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233

VSS

VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

TYCO_2013620-2_IVY BRIDGE ME@

Compal Secret Data

Security Classification Issued Date

2011/06/15

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

Rev B

4019N1

Date:

Wednesday, May 08, 2013

Sheet 1

+VREF_DQ_DIMMA

+1.5V

C133 0.1U_0402_10V6K

DDR_A_D0 DDR_A_D1

DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D9 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25

DDR_A_D26 DDR_A_D27

<7> <7>

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 M_CLK_DDR0 M_CLK_DDR#0

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_BS0

DDR_A_MA10 DDR_A_BS0

<7> <7>

DDR_A_WE# DDR_A_CAS#

<7>

DDR_CS1_DIMMA#

DDR_A_MA13 DDR_CS1_DIMMA#

<7> <7> <7>

R136 1

0_0402_5%

C156 0.1U_0402_10V6K

205

1K_0804_8P4R_1%

DDR_A_D14 DDR_A_D15

+1.5V

DDR_A_D20 DDR_A_D21 +VREF_CA DDR_A_D22 DDR_A_D23

+VREF_CB

DDR_A_D28 DDR_A_D29

8 7 6 5

RP16

1 2 3 4

1K_0804_8P4R_1%

DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

DDR_CKE1_DIMMA

<7>

DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 M_CLK_DDR1 M_CLK_DDR#1 DDR_A_BS1 DDR_A_RAS#

OSCAN (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)

M_CLK_DDR1 <7> M_CLK_DDR#1 <7> DDR_A_BS1 <7> <7> DDR_A_RAS#

DDR_CS0_DIMMA# M_ODT0 M_ODT1

DDR_CS0_DIMMA# M_ODT0 <7>

(0.1uF_402_10V)*4

<7>

M_ODT1

(10uF_0603_6.3V)*8

Layout Note: Place near DIMM

+VREF_CA +1.5V +VREF_CA

DDR_A_D36 DDR_A_D37

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47

C148 0.1U_0402_10V6K

+3VS

<13,7>

1 2 3 4

1 +

C149 @ 220U_6.3V_M

VDDQ(1.5V) = 6*0603 10uf (PER CONNECTOR)

Layout Note: Place near DIMM

VTT(0.75V) = 3*0805 10uf

DDR_A_D54 DDR_A_D55

4*0402 1uf +0.75VS

VREF =

DDR_A_D60 DDR_A_D61

1*0402 0.1uf

DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 SMB_DATA_S3 SMB_CLK_S3 +0.75VS

1*0402 2.2uf

VDDSPD (3.3V)= 1*0402 0.1uf

1*0402 2.2uf

SMB_DATA_S3 <13,15,26> SMB_CLK_S3 <13,15,26>

2 A

0. 65A@0. 75V

206

LCN_DAN06-K4806-0103 ME@

Compal Secret Data

Security Classification Issued Date

2011/06/15

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

Date:

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)

DDR_A_D52 DDR_A_D53

C152 1U_0402_6.3V6K

+VREF_DQ_DIMMB DDR3_DRAMRST#

RP15

C150 1U_0402_6.3V6K

DDR_A_D58 DDR_A_D59

+VREF_DQ_DIMMA

DDR3_DRAMRST#

8 7 6 5

C147 0.1U_0402_10V6K

+3V_DIMM

DDR_A_D56 DDR_A_D57

DDR_A_D12 DDR_A_D13

C146 0.1U_0402_10V6K

DDR_A_D50 DDR_A_D51

+1.5V

DDR_A_D6 DDR_A_D7

C145 0.1U_0402_10V6K

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_MA[0..15]

DDR_A_DQS#0 DDR_A_DQS0

C144 10U_0603_6.3V6M

DDR_A_D48 DDR_A_D49

DDR_A_DQS#[0..7]

<7>

C143 10U_0603_6.3V6M

DDR_A_D42 DDR_A_D43

DDR_A_D4 DDR_A_D5

DDR_A_DQS[0..7]

<7>

C142 10U_0603_6.3V6M

DDR_A_D40 DDR_A_D41

CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

C141 10U_0603_6.3V6M

DDR_A_D34 DDR_A_D35

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26

C140 10U_0603_6.3V6M

VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25

DDR_A_D[0..63]

<7>

C139 10U_0603_6.3V6M

DDR_A_DQS#4 DDR_A_DQS4

73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

JDIMM1

<7>

C135 0.1U_0402_10V6K

DDR_A_D32 DDR_A_D33

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

+1.5V

3A@1. 5V

DDR3 SO-DIMM A +VREF_DQ_DIMMA

4019N1

Wednesday, May 08, 2013

Sheet 1

Rev B

+VREF_DQ_DIMMB

3A@1. 5V +1.5V +VREF_DQ_DIMMB

DDR_B_D2 DDR_B_D3

C157

0.1U_0402_10V6K

DDR_B_D0 DDR_B_D1

DDR_B_D8 DDR_B_D9 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D10 DDR_B_D11 DDR_B_D16 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 DDR_B_D24 DDR_B_D25

DDR_B_D26 DDR_B_D27

<7> <7>

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 M_CLK_DDR2 M_CLK_DDR#2

M_CLK_DDR2 M_CLK_DDR#2

DDR_B_BS0

DDR_B_MA10 DDR_B_BS0

<7> <7>

DDR_B_WE# DDR_B_CAS#

<7>

DDR_CS3_DIMMB#

DDR_B_MA13 DDR_CS3_DIMMB#

<7> <7> <7>

DDR_B_D30 DDR_B_D31

DDR_CKE3_DIMMB

DDR_B_MA15 DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 M_CLK_DDR3 M_CLK_DDR#3 DDR_B_BS1 DDR_B_RAS# DDR_CS2_DIMMB# M_ODT2 M_ODT3

M_CLK_DDR3 <7> M_CLK_DDR#3 <7>

DDR_CS2_DIMMB# M_ODT2 <7> M_ODT3

(10uF_0603_6.3V)*8

Layout Note: Place near DIMM

DDR_B_BS1 <7> <7> DDR_B_RAS#

(0.1uF_402_10V)*4

<7>

+VREF_CB +1.5V

DDR_B_D38 DDR_B_D39

DDR_B_D44 DDR_B_D45 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53

DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7

0. 65A@0. 75V

6*0603 10uf (PER CONNECTOR)

Layout Note: Place near DIMM

VTT(0.75V) = 3*0805 10uf

4*0402 1uf +0.75VS

1*0402 0.1uf

1*0402 2.2uf

VDDSPD (3.3V)= 1*0402 0.1uf

1*0402 2.2uf

SMB_DATA_S3 <12,15,26> SMB_CLK_S3 <12,15,26> +0.75VS

LCN_DAN06-K4406-0103 ME@

Compal Secret Data

Security Classification 2011/06/15

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)

Issued Date

VDDQ(1.5V) =

DDR_B_D62 DDR_B_D63 SMB_DATA_S3 SMB_CLK_S3

C172 0.1U_0402_10V6K

DDR_B_D36 DDR_B_D37

+VREF_CB C171 0.1U_0402_10V6K

DDR_B_DQS#3 DDR_B_DQS3

C170 0.1U_0402_10V6K

206

DDR_B_D28 DDR_B_D29

C169 0.1U_0402_10V6K

205

<7>

DDR_B_D22 DDR_B_D23

C168

+3VS

2 10K_0402_5%

DDR_CKE3_DIMMB

DDR_B_D20 DDR_B_D21

10U_0603_6.3V6M

C178 0.1U_0402_10V6K

1 R97

<12,7>

C167

+3V_DIMM

DDR3_DRAMRST#

DDR_B_D14 DDR_B_D15

10U_0603_6.3V6M

DDR3_DRAMRST#

C176 1U_0402_6.3V6K

DDR_B_D58 DDR_B_D59

DDR_B_D12 DDR_B_D13

C174 1U_0402_6.3V6K

DDR_B_D56 DDR_B_D57

DDR_B_D6 DDR_B_D7

C166

DDR_B_D50 DDR_B_D51

DDR_B_MA[0..15]

DDR_B_DQS#0 DDR_B_DQS0

10U_0603_6.3V6M

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_DQS#[0..7]

<7>

C165

DDR_B_D48 DDR_B_D49

DDR_B_D4 DDR_B_D5

DDR_B_DQS[0..7]

<7>

10U_0603_6.3V6M

DDR_B_D42 DDR_B_D43

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

C164

DDR_B_D40 DDR_B_D41

VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26

10U_0603_6.3V6M

DDR_B_D34 DDR_B_D35

VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25

DDR_B_D[0..63]

<7>

10U_0603_6.3V6M

JDIMM2

<7>

C163

DDR_B_DQS#4 DDR_B_DQS4

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

C159 0.1U_0402_10V6K

DDR_B_D32 DDR_B_D33

+1.5V

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

Document Number

4019N1

Wednesday, May 08, 2013

Sheet 1

Rev B

PCH_RTCX1

W=20mils

+RTCVCC

+RTCBATT

R98

2 10M_0402_5%

PCH_RTCX2

NOGCLK@ Y1 1 2

R99 1K_0402_5% 1 2 1

C180 12P_0402_50V8J NOGCLK@

C179 1U_0603_10V4Z

NOGCLK@

32.768KHZ_12.5PF_CM31532768DZFT 1

C181 12P_0402_50V8J NOGCLK@

2 D

2 R187 1 0_0402_5% @

CMOS

2 1K_0402_5%

HDA_SPKR

HIGH= Enable ( No Reboot ) LOW= Disable (Default)

<31>

+3V_PCH

<31>

R106 2

HDA_SPKR

@ 1 1K_0402_5%

PCH_INTVRMEN

C17

HDA_BIT_CLK

N34

HDA_SYNC

L34

HDA_SPKR

T10

HDA_RST#

K34

C34 A34

<32> 2

1 1K_0402_5%

C36

HDA_SYNC

N32

33_0804_8P4R_5%

HDA_RST# ME_FLASH

R878 1M_0402_5% 1

HDA_SDOUT_AUDIO

HDA_SYNC_R

T35

PAD

T36

PAD

T37

PAD

1 2 3 4

PAD

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

HDA_RST_AUDIO#

8 7 6 5

T41

PCH_JTAG_TCK

@ Q10 LBSS138LT1G_SOT-23-3 1 HDA_SYNC SPI_CLK_PCH_R

<31>

HDA_SYNC_AUDIO

HDA_BIT_CLK

<31>

For EMI RP12

A36

ME_FLASH

This signal has a weak internal pull-down On Die PLL VR is supplied by 1.5V when smapled high(For mobile only) 1.8V when sampled low(For Desktop only) Needs to be pulled High for Chief River platfrom

HDA_BITCLK_AUDIO

E34 G34

R175

0_0402_5%

check with vender

FWH4 / LFRAME#

SRTCRST#

INTVRMEN

LDRQ0# LDRQ1# / GPIO23 SERIRQ

HDA_BCLK HDA_SYNC SPKR HDA_RST# HDA_SDIN0

HDA_SDIN3

SATA1RXN SATA1RXP SATA1TXN SATA1TXP SATA2RXN SATA2RXP SATA2TXN SATA2TXP

HDA_SDIN1 HDA_SDIN2

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

HDA_SDO HDA_DOCK_EN# / GPIO33 HDA_DOCK_RST# / GPIO13

SATA3RXN SATA3RXP SATA3TXN SATA3TXP SATA4RXN SATA4RXP SATA4TXN SATA4TXP

JTAG_TCK

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

JTAG_TMS

SATAICOMPO

JTAG_TDI JTAG_TDO

SATAICOMPI SATA3RCOMPO SATA3COMPI

SPI_SB_CS0#

Y14

SPI_SB_CS1#

SPI_SI

SPI_SO_R

Del Q10 check with codec VDDIO using 3VALW

RTCRST#

INTRUDER#

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LPC

K22

HDA_SDIN0

+5VS

<31>

G22

SM_INTRUDER#

Low = Disabled (Default) High = Enabled [Flash Descriptor Security Overide]

R108

PCH_SRTCRST#

ME_FLASH

+3V_PCH

<31>

D20

RTCX2

SATA 6G

R105 1

PCH_RTCRST#

RTCX1

SATA

+3VS

C20

RTC

PCH_RTCX2

IHDA

C182 1U_0603_10V4Z

(INTVRMEN should always be pull high.)

A20

JTAG

INTVRMEN H：Integrated VRM enable L：Integrated VRM disable

CLRP3 SHORT PADS

C183 1U_0603_10V4Z 1 2 R103 20K_0402_5% 1 2 R100 20K_0402_5%

GCLK_32K

<34>

U4A PCH_RTCX1

SPI_CLK

SATA3RBIAS

C38 A38 B37 C37

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

D36

LPC_FRAME#

SPI_CS1# SPI_MOSI SPI_MISO

SATALED# SATA0GP / GPIO21 SATA1GP / GPIO19

R124 33_0402_5% @

AM3 AM1 AP7 AP5

SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 SATA_ITX_C_DRX_N0 SATA_ITX_C_DRX_P0

SATA_DTX_C_IRX_N0 <30> SATA_DTX_C_IRX_P0 <30> SATA_ITX_C_DRX_N0 <30> SATA_ITX_C_DRX_P0 <30>

SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 SATA_ITX_C_DRX_N2 SATA_ITX_C_DRX_P2

SATA_DTX_C_IRX_N2 <30> SATA_DTX_C_IRX_P2 <30> SATA_ITX_C_DRX_N2 <30> SATA_ITX_C_DRX_P2 <30>

SERIRQ

<32>

AD7 AD5 AH5 AH4 AB8 AB10 AF3 AF1

<32> <32> <32> <32>

Y3 Y1 AB3 AB1 R111 37.4_0402_1% 1 2

+V1.05S_VCCP

SATA_COMP

R113 49.9_0402_1% 1 2

+V1.05S_VCCP

SATA3_COMP

AB12 AB13 AH1

8 7 6 5

EC_SPI_SO EC_SPI_SI EC_SPI_CLK EC_SPI_CS#

+3V_ROM

SPI_SB_CS1# 1 2 SPI_SO1 @ SPI_SO_R SPI_WP#1 R188 0_0402_5%

BBS_BIT0_R

For EMI

GPIO19 has internal Pull UP

R266 1

2 SPI_WP#1 3.3K_0402_5%

R221 1

2SPI_HOLD#1 3.3K_0402_5% 2 SPI_WP# 3.3K_0402_5%

R127 1 R129 1

2SPI_HOLD# 3.3K_0402_5%

+3VS

PCH_GPIO16

SPI_SO_L SPI_SI_R SPI_CLK_PCH_0 SPI_SB_CS0#

2 R115 750_0402_1%

SATALED#

HM70@

<19>

Near U5 1 2 3 4

8M B SPI ROM FOR M E & Non- share ROM .

1 2 3 4

+3V_ROM

R124;c190 close to U4.T3 pin

RP27

RBIAS_SATA3

V14 P1

EC_SPI_SO EC_SPI_SI EC_SPI_CLK EC_SPI_CS#

0_0804_8P4R_5% @

Y11 Y10

ODD

11/30 Add(Share ROM)

Y7 Y5 AD3 AD1

For EMI

HDD

AM10 AM8 AP11 AP10

SA00005MQ80 S IC BD82HM70 SJTNV C1 BGA 989P PCH C38!

C190 22P_0402_50V8J @

<32>

SERIRQ

DPDG1.1

LPC_FRAME#

EC and Mini card debug port

<32> <32> <32> <32>

E36 K36

PANTHER-POINT_FCBGA989 HM76@

SPI_CLK_PCH_R

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

SPI_CS0#

SPI

PCH_INTVRMEN

SM_INTRUDER#

2 330K_0402_5%

2 1M_0402_5%

R102 1

R101 1

+RTCVCC

CLRP2 SHORT PADS

+RTCVCC

GCLK_32K

BBS_BIT0_R SATALED# PCH_GPIO16 SERIRQ

8 7 6 5

RP17

8 7 6 5

0_0402_5% SPI_HOLD#1 R198 2 SPI_CLK_PCH_R SPI_CLK_PCH_1 1 @ 1 2 SPI_SI @ SPI_SI1 R196 0_0402_5% 64M W25Q64FVSSIQ SOIC 8P @ For EMI CS# SO WP# GND

VCC HOLD# SCLK SI

U6 Rersver 4M+2M Solution +3V_ROM

1 2 3 4

SPI_SB_CS0# 1 2 SPI_SO_L SPI_SO_R @ R131 0_0402_5% SPI_WP#

For EMI

1 2 3 4

8 7 6 5

0_0402_5% SPI_HOLD# R135 2 SPI_CLK_PCH_R SPI_CLK_PCH_0 1 @ 1 2 SPI_SI @ SPI_SI_R R133 64M W25Q64FVSSIQ SOIC 8P 0_0402_5% CS# SO WP# GND

VCC HOLD# SCLK SI

For EMI

10K_0804_8P4R_5%

Compal Secret Data

Security Classification Issued Date

2011/06/15

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev B

4019N1

Date:

Wednesday, May 08, 2013

Sheet 1

U4B

BF36 BE36 AY34 BB34 BG37 BH37 AY36 BB36 BJ38 BG38 AU36 AV36 BG40 BJ40 AY40 BB40 BE38 BC38 AW38 AY38

LAN C

<27> <27> <27>

WLAN

R153 1 R154 1

CLK_PCIE_LAN# CLK_PCIE_LAN CLKREQ_LAN#

<26> <26>

CLK_PCIE_WLAN1# CLK_PCIE_WLAN1

<26>

CLKREQ_WLAN#

+3V_PCH

R152

R156 1 R165 1

+3VS

R158 2

@ @

2 2

0_0402_5% 0_0402_5%

For EMI

CLK_PCIE_LAN#_R CLK_PCIE_LAN_R

1 10K_0402_5% @ @

2 2

0_0402_5% 0_0402_5%

For EMI

Y40 Y39

CLK_PCIE_WLAN1#_R AB49 CLK_PCIE_WLAN1_R AB47 M1

1 10K_0402_5%

AA48 AA47 V10 Y37 Y36 A8 Y43 Y45 L12 V45 V46 L14

PERN3 PERP3 PETN3 PETP3

PERN6 PERP6 PETN6 PETP6

SML0CLK SML0DATA

PCH_SMBDATA

+3VS

A12 DRAMRST_CNTRL_PCH C8

PCH_SML0CLK

G12

PCH_SML0DATA

C13

PCH_HOT#

E14

SML1CLK

M16

SML1DATA

DRAMRST_CNTRL_PCH 2 R139 1 1K_0402_5% 2 R140

PERN4 PERP4 PETN4 PETP4 PERN5 PERP5 PETN5 PETP5

SML0ALERT# / GPIO60

SML1ALERT# / PCHHOT# / GPIO74 SML1CLK / GPIO58 SML1DATA / GPIO75

PERN8 PERP8 PETN8 PETP8

CL_CLK1 CL_DATA1 CL_RST1#

SMB_DATA_S3

1 10K_0402_5%

Q61A 2N7002DW-T/R7_SOT363-6 6 1 EC_SMB_CK2

+3V_PCH

EC_SMB_CK2

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

<29,32>

VGA EC thermal sensor

+3VS

EC_SMB_DA2

<29,32>

2N7002DW-T/R7_SOT363-6 Q61B

+3V_PCH

T11

<12,13,26>

+3V_PCH

P10

R143 10K_0402_5%

R544 2.2K_0402_5% PCH_SML0CLK

PEG_A_CLKRQ# / GPIO47

CLKOUT_PCIE0N CLKOUT_PCIE0P

CLKOUT_PCIE1N CLKOUT_PCIE1P

2N7002DW-T/R7_SOT363-6 Q60B

PERN7 PERP7 PETN7 PETP7

PCIECLKRQ0# / GPIO73

<10,7>

<12,13,26>

DIMM1 DIMM2 MINI CARD

SMBDATA

SMB_CLK_S3

+3V_PCH

BG36 BJ36 AV34 AU34

PERN2 PERP2 PETN2 PETP2

1 10K_0402_5%

BE34 BF34 BB32 AY32

PCH_SMBCLK

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

E12 PCH_GPIO11 R134 2 H14

2 0.1U_0402_10V7K 2 0.1U_0402_10V7K

SMBCLK

1 1

SMBALERT# / GPIO11

C194 C195

PERN1 PERP1 PETN1 PETP1

BG34 BJ34 AV32 AU32

SMBUS

PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

Link

2 0.1U_0402_10V7K 2 0.1U_0402_10V7K

Controller

1 1

CLOCKS

<26> PCIE_PRX_DTX_N2 <26> PCIE_PRX_DTX_P2 <26> PCIE_PTX_C_DRX_N2 <26> PCIE_PTX_C_DRX_P2

WLAN

C192 C193

PCI-E*

<27> PCIE_PRX_DTX_N1 <27> PCIE_PRX_DTX_P1 <27> PCIE_PTX_C_DRX_N1 <27> PCIE_PTX_C_DRX_P1

LAN

Q60A 2N7002DW-T/R7_SOT363-6 6 1 SMB_CLK_S3

M10

R545 2.2K_0402_5% 1

PCH_SML0DATA

AB37 AB38

+3V_PCH CLKOUT_DMI_N CLKOUT_DMI_P

PCIECLKRQ1# / GPIO18

CLKOUT_DP_N CLKOUT_DP_P

CLKOUT_PCIE2N CLKOUT_PCIE2P

CLKIN_DMI_N CLKIN_DMI_P

PCIECLKRQ2# / GPIO20 CLKOUT_PCIE3N CLKOUT_PCIE3P

CLKIN_GND1_N CLKIN_GND1_P

PCIECLKRQ3# / GPIO25

CLKIN_DOT_96N CLKIN_DOT_96P

CLKOUT_PCIE4N CLKOUT_PCIE4P

CLKIN_SATA_N CLKIN_SATA_P

PCIECLKRQ4# / GPIO26 CLKOUT_PCIE5N CLKOUT_PCIE5P

REFCLK14IN

PCIECLKRQ5# / GPIO44

CLKIN_PCILOOPBACK

AV22 AU22

CLK_CPU_DMI# CLK_CPU_DMI

CLK_CPU_DMI# <6> CLK_CPU_DMI <6>

+3VS

AM12 AM13 1 2 3 4

RP8

10K_0804_8P4R_5% 8 7 6 5

BF18 BE18

CLK_BUF_CPU_DMI# CLK_BUF_CPU_DMI

BJ30 BG30

CLKIN_DMI2# CLKIN_DMI2

G24 E24

CLK_BUF_DREF_96M# CLK_BUF_DREF_96M

R162 1 R163 1

2 2

10K_0402_5% 10K_0402_5%

AK7 AK5

CLK_BUF_PCIE_SATA# R164 1 CLK_BUF_PCIE_SATA R166 1

2 2

10K_0402_5% 10K_0402_5%

K45

CLK_BUF_ICH_14M

R167 1

10K_0402_5%

H45

CLK_PCI_LPBACK

V47 V49

XTAL25_IN XTAL25_OUT

Y47

XCLK_RCOMP

CLK_PCI_LPBACK

8 7 6 5

SML1DATA EC_SMB_DA2 SML1CLK EC_SMB_CK2

RP23

1 2 3 4

2.2K_0804_8P4R_5% +3V_PCH +3VS 8 7 6 5

PCH_SMBCLK SMB_CLK_S3 PCH_SMBDATA SMB_DATA_S3

RP24

1 2 3 4

2.2K_0804_8P4R_5%

<18>

E6 V40 V42 T13 V38 V37 K12 AK14 PCIE_CLK_8N AK13 PCIE_CLK_8P

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

XTAL25_IN XTAL25_OUT

PEG_B_CLKRQ# / GPIO56 XCLK_RCOMP

CLKOUT_PCIE6N CLKOUT_PCIE6P

CLKOUT_PCIE7N CLKOUT_PCIE7P PCIECLKRQ7# / GPIO46 CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

0_0402_5% 2 R171 90.9_0402_1% 1 2

1 R796 GCLK_PCH_25MHZ

GCLK_PCH_25MHZ

<34>

+V1.05S_VCCP

For EMI B Phaes change to GCLK@ XTAL25_IN

PCIECLKRQ6# / GPIO45

FLEX CLOCKS

AB42 AB40

CLKOUTFLEX0 / GPIO64 CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67

K43 F47

H47

K49

PCH_GPIO67

<19> C196 12P_0402_50V8J NOGCLK@

BIOS Request SKU ID

PANTHER-POINT_FCBGA989

NOGCLK@ 1 2 R169 1M_0402_5%

XTAL25_OUT

27M_SSC

OSC NC

NC OSC

4 1

Y2 1 25MHZ_10PF_7V25000014 NOGCLK@

C197 12P_0402_50V8J NOGCLK@

HM76@

Compal Secret Data

Security Classification Issued Date

2011/06/15

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev B

4019N1

Date:

Wednesday, May 08, 2013

Sheet 1

+RTCVCC DSWODVREN

R179

1 330K_0402_5%

U4C

<5> <5> <5> <5>

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

BE24 BC20 BJ18 BJ20

<5> <5> <5> <5>

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

AW24 AW20 BB18 AV18

<5> <5> <5> <5>

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

AY24 AY20 AY18 AU18

SYS_PWROK

C854 0.1U_0402_16V4Z

1 +3VS

3/20 Add (ESD request)

+V1.05S_VCCP 1 R177 1 R178

BJ24 2 DMI_IRCOMP 49.9_0402_1% 2 RBIAS_CPY 750_0402_1%

BG25 BH21

DMI0RXN DMI1RXN DMI2RXN DMI3RXN

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

DMI0RXP DMI1RXP DMI2RXP DMI3RXP DMI0TXN DMI1TXN DMI2TXN DMI3TXN DMI0TXP DMI1TXP DMI2TXP DMI3TXP

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

U15 MC74VHC1G08DFT2G SC70 5P @

3 2

PCH_PWROK 2

VGATE

<32,44>

<5> <5> <5> <5>

BC24 BE20 BG18 BG20

FDI_INT

DMI_ZCOMP

FDI_FSYNC0

DMI_IRCOMP

FDI_FSYNC1

DMI2RBIAS

FDI_LSYNC0

4mil width and place within 500mil of the PCH

<19> <32> <32>

<6>

SYS_RST#

SYS_PWROK

SYS_RST# SYS_PWROK

K3 P12 L22

PCH_PWROK

PM_DRAM_PWRGD <32>

DSWVRMEN C12

PCH_PWROK

L10

PM_DRAM_PWRGD

B13 C21

EC_RSMRST#

System Power Management

SUSACK# is only used on platform that support the Deep Sx state.

FDI_LSYNC1

SUSACK# SYS_RESET# SYS_PWROK PWROK APWROK DRAMPWROK RSMRST#

+3V_PCH SUSWARN# 2

R192 1 300_0402_5%

R194

1 10K_0402_5%

SUSWARN#

R197

1 10K_0402_5%

EC_RSMRST#

PM_DRAM_PWRGD <32> <32,37,39>

ACIN

K16 E20

PBTN_OUT# D29 1

AC_PRESENT_R

CH751H-40PT_SOD323-2

H20 E10

RI#

A10

DPWROK WAKE# CLKRUN# / GPIO32 SUS_STAT# / GPIO61 SUSCLK / GPIO62 SLP_S5# / GPIO63 SLP_S4#

SUSWARN#/SUSPWRDNACK/GPIO30 PWRBTN#

SLP_S3# SLP_A#

ACPRESENT / GPIO31 BATLOW# / GPIO72

SLP_SUS# PMSYNCH

RI#

SLP_LAN# / GPIO29

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

<5> <5> <5> <5> <5> <5> <5> <5>

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

<5> <5> <5> <5> <5> <5> <5> <5>

AW16

FDI_INT

AV12

FDI_FSYNC0

BC10

FDI_FSYNC1

AV14

FDI_LSYNC0

BB10

FDI_LSYNC1

A18

DSWODVREN

E22

EC_RSMRST#

FDI_INT

<5>

FDI_FSYNC1

<5>

FDI_LSYNC0

<5>

FDI_LSYNC1

<5>

Note:This signal must be always pulled-up to VccRTC.

PCIE_WAKE# PM_CLKRUN#

SUS_STAT#

<26> 2

R299 10K_0402_5% 1

T38 PAD

N14

SUSCLK

D10 H4 F4 G10

<5>

FDI_FSYNC0

B9 N3

DSWODVREN - On Die DSW VR Enable H：Enable L：Disable

<32>

PM_SLP_S5#

<32>

PM_SLP_S4#

<32>

PM_SLP_S3#

<32> B

Can be left NC when IAMT is not support on the platfrom

G16 AP14 K14

H_PM_SYNC

<6>

Can be left NC if no use integrated LAN.

PANTHER-POINT_FCBGA989

HM76@ +3V_PCH R309

2 200K_0402_5%

AC_PRESENT_R

+3V_PCH

8 7 6 5

RP25

1 2 3 4

PCIE_WAKE# RI# EC_SMI#

EC_SMI#

<19,32>

10K_0804_8P4R_5%

Compal Secret Data

Security Classification Issued Date

2011/06/15

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev B

4019N1

Date:

Wednesday, May 08, 2013

Sheet 1

100K_0402_1%

J47 M45

<32> ENBKL <23> PCH_ENVDD <23>

P45

PCH_PWM

<23> EDID_CLK <23> EDID_DATA +3VS 2.37K_0402_1% RP14

1 2 3 4

EDID_DATA EDID_CLK CTRL_DATA CTRL_CLK

2.2K_0804_8P4R_5%

8 7 6 5

RP20

1 2 3 4

2 R206

EDID_CLK EDID_DATA

T40 K47

CTRL_CLK CTRL_DATA

T45 P39

LVDS_IBG

AE48 AE47

<23> <23>

AK39 AK40

LVDS_ACLK# LVDS_ACLK

<23> <23> <23>

LVDS_A0# LVDS_A1# LVDS_A2#

AN48 AM47 AK47 AJ48

<23> <23> <23>

LVDS_A0 LVDS_A1 LVDS_A2

AN47 AM49 AK49 AJ47 AF40 AF39

DAC_BLU DAC_GRN DAC_RED

AH45 AH47 AF49 AF45

150_0804_8P4R_1%

Max = 800 mils

AH43 AH49 AF47 AF43

<24> <24> <24> <24> <24>

CRT_DDC_CLK CRT_DDC_DATA

<24> <24>

CRT_HSYNC CRT_VSYNC

DAC_BLU DAC_GRN DAC_RED

N48 P49 T49

CRT_DDC_CLK CRT_DDC_DATA

T39 M40 M47 M49

R524 2.2K_0402_5%

CRT_IREF T43 T42

R211 1K_0402_1%

R559 2.2K_0402_5% 2

DAC_BLU DAC_GRN DAC_RED

+3VS

AF37 AF36

SDVO_TVCLKINN SDVO_TVCLKINP

L_BKLTCTL

SDVO_STALLN SDVO_STALLP

L_DDC_CLK L_DDC_DATA

SDVO_INTN SDVO_INTP

L_CTRL_CLK L_CTRL_DATA LVD_IBG LVD_VBG

SDVO_CTRLCLK SDVO_CTRLDATA

LVD_VREFH LVD_VREFL LVDSA_CLK# LVDSA_CLK LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3

DDPB_AUXN DDPB_AUXP DDPB_HPD

LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 LVDSB_CLK# LVDSB_CLK LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

CRT_BLUE CRT_GREEN CRT_RED CRT_DDC_CLK CRT_DDC_DATA

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P DDPC_CTRLCLK DDPC_CTRLDATA DDPC_AUXN DDPC_AUXP DDPC_HPD DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P DDPD_CTRLCLK DDPD_CTRLDATA DDPD_AUXN DDPD_AUXP DDPD_HPD DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

CRT_HSYNC CRT_VSYNC DAC_IREF CRT_IRTN

AP43 AP45 AM42 AM40 AP39 AP40

P38 HDMICLK_NB M39 HDMIDAT_NB AT49 AT47 AT40

HDMICLK_NB HDMIDAT_NB

TMDS_B_HPD#

AV42 TMDS_B_DATA2#_PCHHDMI@ AV40 TMDS_B_DATA2_PCH HDMI@ AV45 TMDS_B_DATA1#_PCHHDMI@ AV46 TMDS_B_DATA1_PCH HDMI@ AU48 TMDS_B_DATA0#_PCHHDMI@ AU47 TMDS_B_DATA0_PCH HDMI@ AV47 TMDS_B_CLK#_PCH HDMI@ AV49 TMDS_B_CLK_PCH HDMI@ P46 P42

C200 C201 C202 C203 C204 C205 C206 C207

<25> <25>

<25> 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

HDMI_TX2-_CK <25> HDMI_TX2+_CK <25> HDMI_TX1-_CK <25> HDMI_TX1+_CK <25> HDMI_TX0-_CK <25> HDMI_TX0+_CK <25> HDMI_CLK-_CK <25> HDMI_CLK+_CK <25>

HDMI D2 HDMI

HDMI D1 HDMI D0

HDMI CLK

CAP move on Conn, side

AP47 AP49 AT38 AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49 M43 M36

AT45 AT43 BH41 BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

PANTHER-POINT_FCBGA989 HM76@

CRT_DDC_CLK CRT_DDC_DATA

L_BKLTEN L_VDD_EN

Digital Display Interface

ENBKL

LVDS

CRT

8 7 6 5

U4D

R438 D

Compal Secret Data

Security Classification Issued Date

2011/06/15

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

Document Number

4019N1

Wednesday, May 08, 2013

Sheet 1

Rev B of

10 9 8 7 6

PCH_GPIO2 DGPU_PWR_EN PCH_GPIO4 PCH_GPIO3

U4E BG26 BJ26 BH25 BJ16 BG16 AH38 AH37 AK43 AK45 C18 N30 H3 AH12 AM4 AM5 Y13 K24 L24 AB46 AB45

8.2K_1206_10P8R_5% D

+3VS RP7

1 2 3 4

DGPU_HOLD_RST# PCH_WL_OFF# PCH_GPIO5 NVDD_PWR_EN

8.2K_0804_8P4R_5%

Pull-up resistors are not required on these signals

R292

2 8.2K_0402_5%

PCH_GPIO51

R557

2 8.2K_0402_5%

PCH_GPIO53 B21 M20 AY16 BG46

Boot BIOS Strap GNT1#/ GPIO51 SATA1GP/ GPIO19 Internal PH

GPIO51

GPIO19

Bit11

Bit10

Boot BIOS Destination

Reserved

PCI

SPI

<35> <35>

USB3_RX1_N USB3_RX2_N

<35> <35>

USB3_RX1_P USB3_RX2_P

<35> <35>

USB3_TX1_N USB3_TX2_N

<35> <35>

USB3_TX1_P USB3_TX2_P

USB3_RX1_N BE28 USB3_RX2_N BC30 BE32 BJ32 USB3_RX1_P BC28 USB3_RX2_P BE30 BF32 BG32 USB3_TX1_N AV26 USB3_TX2_N BB26 AU28 AY30 USB3_TX1_P AU26 USB3_TX2_P AY26 AV28 AW30

(Default)

PCH_WL_OFF#

GPIO55 1

2 1K_0402_5%

A16 swap overide Strap/Top-Block Swap Override jumper Low=A16 swap override/Top-Block PCI_GNT3# Swap Override enabled High=Default *

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

K40 K38 H38 G38

DGPU_HOLD_RST# NVDD_PWR_EN

C46 C44 E40

PCH_GPIO51 PCH_GPIO53 PCH_WL_OFF#

D47 E42 F46

PCH_GPIO2 PCH_GPIO3 PCH_GPIO4 PCH_GPIO5

G42 G40 C42 D44

PCI_PME#

K10

DGPU_PWR_EN

<26>

R215

RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22

TP21 TP22 TP23 TP24

RSVD23 RSVD24 RSVD25 RSVD26 RSVD27

USB3Rn1 USB3Rn2 USB3Rn3 USB3Rn4 USB3Rp1 USB3Rp2 USB3Rp3 USB3Rp4 USB3Tn1 USB3Tn2 USB3Tn3 USB3Tn4 USB3Tp1 USB3Tp2 USB3Tp3 USB3Tp4

RSVD28 RSVD29

T39 <6>

PCH_PLTRST#

For EMI

22_0402_5% 1 22_0402_5% 1

<15> CLK_PCI_LPBACK <32> CLK_PCI_EC

PAD

2 R219 2 R220

CLK_PCI_LPBACK_R H49 H43 CLK_PCI_EC_R J48 K42 H40

AY7 AV7 AU3 BG4 AT10 BC8 D

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6 AV5 AV10 AT8 AY5 BA2 AT12 BF3

USB DEBUG=PORT1 AND PORT9 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

LPC

<32>

PCH_WL_OFF#

TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

PIRQA# PIRQB# PIRQC# PIRQD# REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54

USB

8 7 6 5

RSVD1 RSVD2 RSVD3 RSVD4

PCI

+3VS

RSVD

RP1 1 2 3 4 5

PCI_PIRQA# PCI_PIRQD# PCI_PIRQC# PCI_PIRQB#

+3VS

GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5

USBRBIAS# USBRBIAS

PME# PLTRST#

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3

C33

USBRBIAS

<35> <35> <35> <35> <35> <35> <23> <23>

LEFT USB LEFT USB

(USB 3.0)

Touch Screen USB Camera

HM76 not support USB2.0 for port 6-7 HM70 not support USB2.0 for port 4-7 &12 &13 NM70 not support USB2.0 for port 4-7 &12 &13 USB20_N9 USB20_P9 USB20_N10 USB20_P10 USB20_N11 USB20_P11

USB20_N9 <33> USB20_P9 <33> USB20_N10 <26> USB20_P10 <26> USB20_N11 <33> USB20_P11 <33>

USB2.0 WLAN

1 R218 2 22.6_0402_1%

USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7#

For LEFT USB3.0 Port USB_OC0#

<35>

USB_OC4#

<33>

For RIGHT USB2.0 Port USB_OC0# USB_OC1# USB_OC2# USB_OC3#

PANTHER-POINT_FCBGA989 HM76@

+3V_PCH

R222

1 2 0_0402_5% @

USB_OC4# USB_OC5# USB_OC6# USB_OC7# A

Compal Secret Data

Security Classification Issued Date

R223 100K_0402_5%

10 9 8 7 6

PCH_PLTRST#

PLT_RST#

+3V_PCH

RP18 1 2 3 4 5

10K_1206_10P8R_5%

2011/06/15

Deciphered Date

2012/07/11

Title

SCHEMATIC M/B LA-9902

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

<26,27,32>

CARD READER

Within 500 mils

B33 A14 K20 B17 C16 L16 A16 D14 C14

USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3

Date:

4019N1

Wednesday, May 08, 2013

Sheet 1

Rev B of

HM70

HM76

1 2

Reserved

R703 HM70@ PCH_GPIO70

N14M-GE 1000MHz

N14M-GE 900MH

R704 1000M@ PCH_GPIO71

R705 HM76@ 10K_0402_5%

R706 900M@ 10K_0402_5%

R707 @ 10K_0402_5%

R702 @ PCH_GPIO69

NM70

10K_0402_5%

+3VS

PCH_GPIO71 Function

Function

PCH_GPIO70

+3VS

10K_0402_5%

PCH_GPIO69

+3VS

10K_0402_5%

U4F

R240

EC_SMI#

C10

2 10K_0402_5%

PAD <26>

PCH_GPIO27

INTEL_BT_OFF#

+3VS

INTEL_BT_OFF# 1 R242

ODD_EN

2 10K_0402_5% 2 10K_0402_5%

<26>

R241

T67

PCH_BT_ON#

<30>

+3V_PCH

GPIO36, 37 When Unused as GPIO or SATA*GP +3VSto ground. Use 8.2K-10K pull-down

2 1K_0402_5%

PCH_GPIO16

+3VS

EC_SMI#

R230 1

+3V_PCH EC_LID_OUT# <14>

R245

<16,32>

PCH_GPIO27 (Have internal Pull-High) High: VCCVRM VR Enable Low: VCCVRM VR Disable

E38

2 1K_0402_5% PCH_GPIO28

<32>

EC_SCI#

R250 @ 10K_0402_5% 2

R244 @ 10K_0402_5%

PCH_GPIO36

DGPU_PWROK

D40

PCH_BT_ON#

ODD_EN

PCH_GPIO27

E16

PCH_GPIO28

P8 K1

PCH_GPIO35

PCH_GPIO36

PCH_GPIO37

PCH_GPIO38

N2 M3

V13 V3

R547 10K_0402_5% @

TACH3 / GPIO7

TACH7 / GPIO71

A45 A46

+3VS

BIOS Request SKU ID

8 7 6 5

RP10

1 2 3 4

PCH_GPIO39 SYS_RST# PCH_BT_ON# PCH_GPIO35

SYS_RST#

10K_0804_8P4R_5%

BD49 BE1 BE49

PCH_GPIO38 PCH_GPIO67

BF1

<15>

BF49

1 2

10K_0402_5%

2 1

R708 OPT@ A

BD1

R246 UMA@ 10K_0402_5%

PCH_GPIO67

<16>

B47

R711 UMA@

10K_0402_5%

+3VS

R298 OPT@ 10K_0402_5%

PCH_GPIO70

+3VS

A40

PCH_GPIO71

R236 10K_0402_5%

GPIO15

A20GATE PECI

SATA4GP / GPIO16 TACH0 / GPIO17 SCLOCK / GPIO22

RCIN#

GPIO24 GPIO27 GPIO28

PROCPWRGD THRMTRIP# INIT3_3V# DF_TVS TS_VSS1

STP_PCI# / GPIO34

TS_VSS2

GPIO35

TS_VSS3

SATA2GP / GPIO36

TS_VSS4

SATA3GP / GPIO37 SLOAD / GPIO38

NC_1

VSS_NCTF_15

SATA5GP / GPIO49 / TEMP_ALERT#

VSS_NCTF_16

GPIO57

VSS_NCTF_17

VSS_NCTF_1

VSS_NCTF_19

VSS_NCTF_2

VSS_NCTF_20

VSS_NCTF_3

VSS_NCTF_21

VSS_NCTF_5

KBRST#

AY11

VSS_NCTF_22 VSS_NCTF_23

VSS_NCTF_6

VSS_NCTF_24

VSS_NCTF_7

VSS_NCTF_25

VSS_NCTF_8

VSS_NCTF_26

VSS_NCTF_9

VSS_NCTF_27

VSS_NCTF_10

VSS_NCTF_28

VSS_NCTF_11

VSS_NCTF_29

VSS_NCTF_12

VSS_NCTF_30

VSS_NCTF_13

VSS_NCTF_31

VSS_NCTF_14

VSS_NCTF_32

+3VS

<32>

AY10 T14 AY1 AH8

KBRST#

<32>

H_CPUPWRGD PCH_THRMTRIP#_R 1 R239

R226

2 10K_0402_5%

<6>

2 H_THRMTRIP# 390_0402_5%

H_THRMTRIP#

<6>

INIT3_3V

This signal has weak internal PU,can't pull low +1.8VS

AK11 AH10

DMI Termination Voltage

AK10

NV_CLE

P37

Set to Vcc when HIGH

BG2

Weak internal PU,Do not pull low

BG48

R216 2.2K_0402_5%

Set to Vss when LOW

NV_CLE

SDATAOUT1 / GPIO48

VSS_NCTF_4

GATEA20

AU16

SDATAOUT0 / GPIO39

NCTF

A44

PCH_GPIO69

C41

LAN_PHY_PWR_CTRL / GPIO12

VSS_NCTF_18 A4

B41

GPIO8

R881 10K_0402_5% @

PCH_GPIO16

PCH_GPIO39

PCH_GPIO37

EC_LID_OUT#

TACH6 / GPIO70

H：On-Die voltage regulator enable L：On-Die PLL Voltage Regulator disable

EC_SCI#

TACH2 / GPIO6

C40

<32>

TACH5 / GPIO69

H36

On-Die PLL Voltage Regulator This signal has a weak internal pull up

TACH4 / GPIO68

TACH1 / GPIO1

GPIO28

BMBUSY# / GPIO0

CPU/MISC

A42

GPIO

1 R217 1K_0402_5%

H_SNB_IVB#

<6>

CLOSE TO THE BRANCHING POINT

BH3 BH47 BJ4 BJ44

BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49

PANTHER-POINT_FCBGA989

PCH_GPIO38

PCH_GPIO67

Function

Optimus

Reserved

DIS

UMA

HM76@

Compal Secret Data

Security Classification Issued Date

2011/06/15

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

Rev B

4019N1

Date:

Wednesday, May 08, 2013

Sheet 1

AN19

T29

BJ22

+VCCAPLLEXP

PAD

This pin can be left as no connect in On-Die VR enabled mode (default).

AN16 AN17 AN21 AN26 AN27

Near AN16

+V1.05S_VCCP

AP21 AP23

C225 1U_0402_6.3V6K

C224 1U_0402_6.3V6K

C223 1U_0402_6.3V6K

C222 1U_0402_6.3V6K

C221 10U_0603_6.3V6M

AP24 AP26 AT24 AN33 AN34

+3VS

BH29 1

C227 0.1U_0402_10V7K

This pin can be left as no connect in On-Die VR enabled mode (default).

T30 +V1.05S_VCCP PAD

AP16 +1.05VS_VCCAPLL_FDI

BG6 AP17

+V1.05S_VCCP

AU20

CRT

VSSADAC

LVDS

VCCTX_LVDS[1] VCCTX_LVDS[2]

60mA VCCTX_LVDS[3] VCCTX_LVDS[4]

VCCIO[28]

U48

L1 2

+VCCADAC 1

U47 2

VCCIO[15] VCCIO[16] VCCIO[17]

VCC3_3[6]

C214 0.1U_0402_10V7K

C215 10U_0603_6.3V6M 2@ +3VS

C229 10U_0603_6.3V6M 2@

3.3_0603_1% 1

Voltage Rail

C231 22U_0805_6.3V6M

AK37 +1.8VS L2 0.1UH_MLF1608DR10KT_10%_1608 2 1

AM37 AM38

+VCCTX_LVDS 1

AP36 AP37

C216 0.01U_0402_25V7K

0.1uH inductor, 200mA

1 C217 0.01U_0402_25V7K

C218 22U_0805_6.3V6M

+3VS

V33

VCC3_3[7]

V34

C219 0.1U_0402_10V7K

+1.5VS VCCVRM[3]

AT16

VCCIO[22] VCCIO[23] VCCIO[24]

VCCDMI[1]

AT20

Near AB36 20mA VCCCLKDMI

VCCDFTERM[1]

190mA VCCDFTERM[2]

VCC3_3[3]

VCCVRM[2] VccAFDIPLL

VCCDMI[2]

VCCDFTERM[3] VCCDFTERM[4]

20mA VCCSPI

1 C226 1U_0402_6.3V6K

VCCIO[26]

+V1.05S_VCCP

AB36

VCCIO[25]

VCCIO[27]

+V1.05S_VCCP

Near AT20

VCCIO[20] VCCIO[21]

1.05

0.001

V5REF

0.001

V5REF_Sus

0.001

Vcc3_3

3.3

0.228

VccADAC

3.3

0.001

VccADPLLA

1.05

0.075

VccADPLLB

1.05

0.075

VccCore

1.05

1.3

VccDMI

1.05

0.042

VccIO

1.05

3.709

VccASW

1.05

0.903

VccSPI

3.3

0.01

VccDSW

3.3

0.001

VccDFTERM

1.8

0.002

VccRTC

3.3

6 uA

3.3

0.065

VCCIO[18]

3711mA

S0 Iccmax Current (A)

Voltage

V_PROC_IO

AK36

VCCAPLLEXP

VCCIO[19]

1 C213 0.01U_0402_25V7K

Near V33

+1.5VS

VCCADAC

VSSALVDS

HVCMOS

+V1.05S_VCCP

PCH Power Rail Table Refer to CPU EDS R1.5

+3VS

1mA VCCALVDS

DMI

VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4] VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] VCCCORE[16] VCCCORE[17]

L1 Change to 1 ohm P/N S RES 1/10W 1 +-1% 0603

1mA

DFT / SPI

C212 1U_0402_6.3V6K

C211 1U_0402_6.3V6K

C210 1U_0402_6.3V6K

C209 10U_0603_6.3V6M

AA23 AC23 AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26 AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31

1300mA

VCC CORE

Near AA23

POWER

U4G

FDI

+V1.05S_VCCP

VCCIO

C220 1U_0402_6.3V6K

VccSus3_3

AG16 +1.8VS

AG17

Near AG16

AJ16 1 AJ17

C228 0.1U_0402_10V7K

+3V_ROM

Near V1

VccSusHDA

3.3 / 1.5

0.01

VccVRM

1.8 / 1.5

0.167

VccCLKDMI

1.05

0.075

VccSSC

1.05

0.095

VccDIFFCLKN

1.05

0.055

VccALVDS

3.3

0.001

VccTX_LVDS

1.8

0.04

PANTHER-POINT_FCBGA989

C230 1U_0402_6.3V6K

HM76@

11/30 Add(Share ROM) +3VALW

+3VS

+3V_ROM 1 R413 2 0_0402_5% NOSROM@

+5VALW

@ Q21 AO3413_SOT23

VCCVRM==>1.5V FOR MOBILE VCCVRM==>1.8V FOR DESKTOP

@ R418 100K_0402_5%

VCCVRM = 160mA detal waiting for newest spec PCH_PWR_EN

Q22

@ R40 1 2 0_0402_5%

C237 .1U_0402_16V7K @

Issued Date

Compal Secret Data

Security Classification 2011/06/15

2012/07/11

Deciphered Date

1 R419 2 0_0402_5% @

PCH_PWR_EN_R 1

2 G 2N7002H_SOT23-3 @

Title

C252 .1U_0402_16V7K

<32>

12/20 Place @ first

Intel recommand stuff R265 and unstuff R266

C243 .1U_0402_16V7K

@ A

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev B

4019N1

Date:

Wednesday, May 08, 2013

Sheet 1

Have internal VRM +3VS

+V1.05S_VCCP

R268 @ 0_0603_5% 2 1

+VCCACLK

AL24

@ C239 1U_0402_6.3V6K

AA19

+V1.05S_VCCP

Near AA19

AA21

AA26

C242 22U_0805_6.3V6M

C241 22U_0805_6.3V6M

AA27 AA29 AA31 AC26

AC27

C246 1U_0402_6.3V6K

C245 1U_0402_6.3V6K

C244 1U_0402_6.3V6K

1 +V1.05S_VCCP

AC29 AC31 AD29 AD31 W21

W24 1

@ 2

W26

C253 1U_0402_6.3V6K

C251 1U_0402_6.3V6K

W23

+1.05VS_VCCA_A_DPL C250 220U_B2_2.5VM_R35

L6 1 2 10UH_LB2012T100MR_20% 1

W29 W31 W33 +VCCRTCEXT

C258 0.1U_0402_10V7K

+1.5VS

N16 Y49

Near AF17

+V1.05S_VCCP 1

+1.05VS_VCCA_A_DPL +1.05VS_VCCA_A_DPL

C256 1U_0402_6.3V6K

Near AF33

+V1.05S_VCCP

BD47 BF47 AF17 AF33 AF34 AG34

Near AG33

+V1.05S_VCCP

AG33

C259 1U_0402_6.3V6K

C262 1U_0402_6.3V6K

V16

+VCCSST 1

C263 0.1U_0402_10V7K

T32

PAD

+1.05VM_VCCSUS

+V1.05S_VCCP

DCPSUS[3]

A22

VCCSUS3_3[10]

VCCASW[1] VCCASW[2]

VCCIO[34]

1010mA

1mA V5REF_SUS

VCCASW[3] VCCASW[4] VCCASW[5] VCCASW[6] VCCASW[7] VCCASW[8] VCCASW[9] VCCASW[10] VCCASW[11] VCCASW[12] VCCASW[13] VCCASW[14] VCCASW[15]

DCPSUS[4] VCCSUS3_3[1]

T24

V23 2

V24 P24

+3V_PCH

1mA V5REF VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCC3_3[1] VCC3_3[8] VCC3_3[4]

VCCASW[19]

VCC3_3[2]

VCCASW[20]

VCCIO[5]

DCPRTC

VCCIO[12]

VCCVRM[4]

VCCIO[13]

VCCADPLLB

80mA

VCCIO[6] VCCAPLLSATA VCCVRM[1]

VCCIO[7] VCCDIFFCLKN[1] 55mA VCCDIFFCLKN[2] VCCDIFFCLKN[3]

VCCIO[2] VCCIO[3]

95mA

VCCIO[4]

+PCH_V5REF_SUS

AN23

+VCCA_USBSUS

V_PROC_IO 1mA

VCCRTC

D1 CH751H-40PT_SOD323-2

P34

VCCASW[23] VCCASW[21]

C240 0.1U_0603_25V7K

T33 PAD

AN24

+3V_PCH

+PCH_V5REF_RUN

N20 N22

P20

+3VS C

R279 100_0402_1%

1 C247 1U_0402_6.3V

D2 CH751H-40PT_SOD323-2

+3VS

+PCH_V5REF_RUN 1

P22 1 AA16 W16

C249 0.1U_0402_10V7K

C248 1U_0603_10V6K

+3VS

T34 1

C254 0.1U_0402_10V7K

AJ2

+V1.05S_VCCP

1 AF13

C255 2 0.1U_0402_10V7K

AH13

AH14

C257 1U_0402_6.3V6K

AF14 AK1

+VCCSATAPLL

T34 PAD

+1.5VS

On-Die PLL Voltage Regulator

H：On-Die PLL voltage regulator enable

AF11

+V1.05S_VCCP

AC16 AC17

AD17

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA

C261 1U_0402_6.3V6K

+V1.05S_VCCP

VCCASW[22]

+PCH_V5REF_SUS

DCPSST DCPSUS[1] DCPSUS[2]

R275 100_0402_1%

+V1.05S_VCCP

+3VS

80mA

+3V_PCH

1 M26

VCCASW[18]

VCCSSC

C238 0.1U_0402_10V7K

T26

VCCASW[17]

VCCADPLLA

+5VALW

+5VS

VCCASW[16]

+RTCVCC

C269 0.1U_0402_10V7K

C266 0.1U_0402_10V7K

C265 4.7U_0603_6.3V6K

T17 V19

BJ8

Near BJ8

VCCSUS3_3[9]

VCCSUS3_3[6]

AA24 1

VCCSUS3_3[8]

VCCIO[14]

+3V_PCH

T23

+VCCSUS1

VCCAPLLDMI2

T29

AL29

BH23

T27

+VCCAPLL_CPY_PCH

PAD

119mA VCCSUS3_3[7]

P28

C233 1U_0402_6.3V6K

T31 +V1.05S_VCCP

VCCIO[33]

+3V_PCH 1

JUMP_43X118

P26

C236 0.1U_0402_10V7K

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA

VCCIO[32]

VCC3_3[5]

H：On-Die PLL voltage regulator enable

DCPSUSBYP

PJ1 2

N26

On-Die PLL Voltage Regulator

T38

+3VS

VCCIO[31]

USB

C235 0.1U_0402_10V7K

V12

VCCIO[30]

PCI/GPIO/LPC

+PCH_VCCDSW

VCCIO[29]

3mA

SATA

VCCACLK VCCDSW3_3

+3VALW

+V1.05S_VCCP

MISC

T16

T21 V21 T19 +3V_PCH

HDA

C234 0.1U_0402_10V7K

Clock and Miscellaneous

POWER

U4J AD49

CPU

C232 1U_0402_6.3V6K

2 D

Near T16

RTC

+3V_PCH 1

Near T38

10mA VCCSUSHDA

P32 1

PANTHER-POINT_FCBGA989 HM76@

C271 0.1U_0402_16V4Z

Compal Secret Data

Security Classification Issued Date

2011/06/15

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4019N1

Date:

Wednesday, May 08, 2013

Sheet 1

Rev B

U4I

H5 AA17 AA2 AA3 AA33 AA34 AB11 AB14 AB39 AB4 AB43 AB5 AB7 AC19 AC2 AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39 AD4 AD40 AD42 AD43 AD45 AD46 AD8 AE2 AE3 AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38 AF4 AF42 AF46 AF5 AF7 AF8 AG19 AG2 AG31 AG48 AH11 AH3 AH36 AH39 AH40 AH42 AH46 AH7 AJ19 AJ21 AJ24 AJ33 AJ34 AK12 AK3

AY4 AY42 AY46 AY8 B11 B15 B19 B23 B27 B31 B35 B39 B7 F45 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38 BB4 BB46 BC14 BC18 BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46 BD5 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BD3 BF30 BF38 BF40 BF8 BG17 BG21 BG33 BG44 BG8 BH11 BH15 BH17 BH19 H10 BH27 BH31 BH33 BH35 BH39 BH43 BH7 D3 D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42 D8 E18 E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34 F3

U4H VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79]

VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158]

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

PANTHER-POINT_FCBGA989 HM76@

VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258]

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352]

PANTHER-POINT_FCBGA989 HM76@

Compal Secret Data

Security Classification Issued Date

2011/06/15

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC M/B LA-9902 Rev B

4019N1

Date:

Wednesday, May 08, 2013

Sheet 1

LCD POWER CIRCUIT

CMOS Camera

+3VS

W=60mils

(20 MIL)

+LCDVDD_CONN

C4 1500P_0402_50V7K

APL3512ABI-TRG_SOT23-5

<32>

2 <17>

R435CMOS@ 150K_0402_5%

CMOS@ C518 0.1U_0402_16V4Z R02

C519 @ 10U_0603_6.3V6M

4.7V

CMOS_ON#

R296 for CMOS shake issue reserve

PCH_ENVDD

(20 MIL)

GND

+3VS_CMOS

CMOS@ Q83 PMV65XP_SOT23-3~D

+LCDVDD_CONN S

VOUT

VIN

U72

4.7U_0603_6.3V6K

W=60mils

C516

+3VS

C520 CMOS@ 0.1U_0402_16V4Z

VGA LCD/PANEL BD. Conn.

12/12 Mount C539/C541 of 680pF,Chanage R813 to 220 ohm bead.(For EMI request)

C541 680P_0402_50V7K

C539 680P_0402_50V7K

R716 10K_0402_5%

BKOFF#

<32>

B+ R813 FBMA-L11-201209-221LMA30T_0805 1 2

+LEDVDD

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

BKOFF# <17> <17>

For EMI <18> <18>

USB20_P3 USB20_N3

2 2

USB20_P3 USB20_N3

LVDS_ACLK LVDS_ACLK#

<17> <17>

R688 1 0_0402_5% R684 1 0_0402_5%

<17> <17>

USB20_P3_R USB20_N3_R

LVDS_A2 LVDS_A2# EDID_DATA EDID_CLK +3VS

USB20_P3

USB20_N3

L58 @

USB20_P3_R

USB20_N3_R

JLVDS1

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

GNDGND

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

PCH_PWM

<17>

USB20_N3_R USB20_P3_R

LVDS_A1 <17> LVDS_A1# <17> LVDS_A0 <17> LVDS_A0# <17>

(60 MIL)

+LCDVDD_CONN +3VS +3VS_CMOS

ACES_87142-3041-BS ME@

WCM-2012-900T_4P

Compal Secret Data

Security Classification Issued Date

2011/06/15

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

Date:

4019N1

Wednesday, May 08, 2013

Sheet

Rev B

<17>

DAC_BLU

8 7 6 5

RP22

1 2 3 4

DAC_BLU DAC_GRN DAC_RED

150_0804_8P4R_1%

For EMI

GREEN

10P_0402_50V8J C527

DAC_GRN

RED

10P_0402_50V8J C526

<17>

FCM1608CF-121T03 0603 1 2 L30 FCM1608CF-121T03 0603 1 2 L31 FCM1608CF-121T03 0603 1 2 L32

10P_0402_50V8J C525

DAC_RED

10P_0402_50V8J C524

<17>

10P_0402_50V8J C523

10P_0402_50V8J C522

BLUE 1 +5V_DISPLAY

@ PAD

T66

6 11 1 7 12 2 8 13 3 9 14 4 10 15 5

NC11 RED CRT_DDC_DAT_CONN GREEN JVGA_HS_R BLUE

JVGA_VS_R CRT_DDC_CLK_CONN

16 17

C531 0.1U_0402_16V4Z @

U10

2 7

C537 0.1U_0402_16V4Z

<17>

CRT_DDC_DATA

<17>

CRT_DDC_CLK

BYP

VCC_VIDEO

VIDEO1

VCC_DDC

VIDEO2

DDC_IN1

VIDEO3

DDC_IN2

DDC_OUT1

SYNC_IN1

DDC_OUT2

1 C6

2 0.22U_0402_10V6K

RED

GREEN

BLUE

CRT_DDC_DAT_CONN

+5V_DISPLAY

R31 4.7K_0402_5%

R33 4.7K_0402_5% 2

VCC_SYNC

<17> <17>

CRT_VSYNC CRT_HSYNC

11 13 15 6

SYNC_IN2 GND

SYNC_OUT1 SYNC_OUT2

CRT_DDC_CLK_CONN

JVGA_VS

1 R411

2 JVGA_VS_R 0_0402_5%

JVGA_HS

1 R412

2 JVGA_HS_R 0_0402_5%

TPD7S019-15DBQR_SSOP16 @

C412 10P_0402_50V8J

10P_0402_50V8J C411

+3VS

G G

SUYIN_070546FR015S251ZR ME@

+5VS

C529 0.1U_0402_16V4Z

JCRT1

Compal Secret Data

Security Classification 2011/06/15

Issued Date

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

Date:

4019N1

Wednesday, May 08, 2013

Sheet E

Rev B

For EMI HDMI_CLK+_CK

<17>

HDMI_CLK-_CK

HDMI_CLK+_CONN

HDMI_CLK-_CONN

<17>

HDMI_TX0-_CK

HDMI_TX0+_CONN

HDMI_TX0-_CONN

<17>

TMDS_B_HPD#

1 D

HDMI_TX0+_CK

HDMI_TX1+_CK

<17>

HDMI_TX1-_CK

HDMI@

0.1U_0402_16V4Z 2

AP2330W-7_SC59-3

ZZZ3

HDMI_TX1+_CONN

HDMI_TX1-_CONN

RO0000003HM R488 20K_0402_5% HDMI@

HDMI_TX2+_CK

<17>

HDMI_TX2-_CK

L38

HDMI@

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

HDMI_DET +5V_DISPLAY

WCM-2012HS-900T

<17>

HDMI_TX2+_CONN

HDMI_TX2-_CONN

HDMIDAT_R HDMICLK_R HDMI_CLK-_CONN HDMI_CLK+_CONN HDMI_TX0-_CONN

WCM-2012HS-900T

HDMI_TX0+_CONN HDMI_TX1-_CONN

+3VS

HDMI_TX1+_CONN HDMI_TX2-_CONN HDMI_TX2+_CONN

8 7 6 5

RP21

1 2 3 4

HDMIDAT_NB HDMIDAT_R HDMICLK_NB HDMICLK_R

<17>

HDMICLK_NB

<17>

HDMIDAT_NB

HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+

20 21 22 23

For LAN CHASSIS1_GND

CONCR_099ATAC19NBLCNF ME@

Q63A HDMI@ 2N7002DW-T/R7_SOT363-6

JHDMI1

HDMICLK_R

+5V_DISPLAY

+3VS

45@

HDMI Logo

<17>

L37

1 C543

WCM-2012HS-900T

W=40mils

IN GND

Q93 HDMI@ 2N7002H_SOT23-3

HDMI_TX0+_CK

HDMI@

<17>

L36

1 C544 0.1U_0402_16V4Z

R485 1M_0402_5% HDMI@

WCM-2012HS-900T

OUT 1

+3VS

HDMI_CLK+_CK

HDMI@

U73 +5VS

<17>

L35

+5V_DISPLAY

2.2K_0804_8P4R_5% HDMI@

RP19

HDMIDAT_R

HDMI_CLK-_CONN HDMI_CLK+_CONN HDMI_TX1-_CONN HDMI_TX1+_CONN

Q63B HDMI@ 2N7002DW-T/R7_SOT363-6

1 2 3 4 5

10 9 8 7 6

HDMI_TX0-_CONN HDMI_TX0+_CONN HDMI_TX2+_CONN HDMI_TX2-_CONN

680_1206_10P8R_5%

ESD

HDMI@

HDMI_CLK-_CONN

9 10

2 2

HDMICLK_R

HDMI_CLK+_CONN

4 4

HDMI_DET

HDMI_TX1-_CONN

5 5

HDMI_TX1+_CONN

HDMICLK_R

HDMI_DET

D28 1 1

HDMI_CLK-_CONN

HDMI_TX0-_CONN 9 10

2 2

HDMI_CLK+_CONN

HDMI_TX0+_CONN 8

4 4

HDMI_TX1-_CONN

5 5

HDMI_TX1+_CONN

D33 1 1

HDMI_TX0-_CONN

2 2

HDMI_TX0+_CONN

HDMI_TX2-_CONN 7

4 4

HDMI_TX2-_CONN

HDMI_TX2+_CONN 6

5 5

HDMI_TX2+_CONN

3 3

YSCLAMP0524P_SLP2510P8-10-9

+3VS D

HDMIDAT_R

9 10

2 G Q95 HDMI@ 2N7002H_SOT23-3

D32 1 1

HDMIDAT_R

YSCLAMP0524P_SLP2510P8-10-9

Compal Secret Data

Security Classification Issued Date

2011/06/15

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc. Document Number

SCHEMATIC M/B LA-9902

4019N1

Date: Wednesday, May 08, 2013

Sheet 1

Rev B

Mini-Express Card for WLAN/WiMAX(Half) 1

+3VS

+3VS_WLAN

80mil J6

+1.5VS

JUMP_43X79 <16> <19>

PCH_BT_ON#

1 R508 2 @ 0_0402_5%

PCIE_WAKE# <15>

PCIE_WAKE#_WLAN

CLKREQ_WLAN#

<15> CLK_PCIE_WLAN1# <15> CLK_PCIE_WLAN1

<15> <15>

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2

<15> <15>

PCIE_PTX_C_DRX_N2 PCIE_PTX_C_DRX_P2 +3VS_WLAN

<19>

INTEL_BT_OFF#

1 1

EC_TX EC_RX R801

100_0402_1% R505 2 2 EC_RX_R R506 100_0402_1% 1 1K_0402_5%

For EC to detect debug card insert.

R507 100K_0402_5%

JWLN1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 GND1

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 GND2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

PCH_WL_OFF# <18> PLT_RST# <18,27,32>

+3VS_WLAN 1 R501 1 R502

2 @ 0_0402_5% 2 @ 0_0402_5% USB20_N10 USB20_P10

SMB_CLK_S3 <12,13,15> SMB_DATA_S3 <12,13,15>

<18> <18>

LOTES_AAA-PCI-046-K01 ME@

<32> <32>

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

Reserve for SW mini-pcie debug card. Series resistors closed to KBC side.

Security Classification Issued Date

2011/06/15

Compal Secret Data Deciphered Date

2012/07/11

Title

Date:

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

Document Number

4019N1

Wednesday, May 08, 2013

Sheet E

Rev B 52

+3V_LAN +LX

Close together

1 2

10K_0402_5% 1

@ CL7 0.1U_0402_16V7K

QL1 LP2301ALT1G-SOT23-3 @

Note: Place Close to LAN chip LL1 DCR< 0.15 ohm Rate current > 1A

CL6

CL5

10U SWR@ SWR@ SWR@

LL3

SWR@

FBMA-L11160808601LMA10T_2P FBMA-L11160808601LMA10T_2P 1 2 1 2 +1.1_AVDDL +LX_R

+1.1_AVDDL_L

4.7U_0603_6.3V6K

RL3 @

LAN_PWR_ON#

10U_0603_6.3V6M CL3

JUMP_43X79 D

LL2

LL1 SWR@ 1 2 +LX 4.7UH_SIA4012-4R7M_20%

+LX_R

1U_0402_6.3V4Z

CL2

0.1U_0402_16V4Z

CL1 1000P_0402_50V7K

CL4

+3VALW

J12

<32>

0.1U_0402_16V4Z

For LAN & Green CLK

Place close to Pin34

Close to Pin40

Vendor recommand reseve the PU resistor close LAN chip 2 4.7K_0402_5%

UL1

PCIE_PRX_C_DTX_P1 30

<15> <15>

PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_P1

<32>

LAN_WAKE# +3V_LAN

RL7

RL9

0_0402_5%

PCIE_WAKE#_R

<15>

RL11 1

WAKE# SMCLK SMDATA

VDD33 LX

XTLO XTLI

CLKREQ_LAN#

RBIAS

NC TESTMODE

7 8

LAN_XTALO LAN_XTALI

2 4.7K_0402_5%

PERST#

28 27

Vendor recommand reseve the PU resistor close LAN chip +3V_LAN

REFCLK_N REFCLK_P

25 26

2 4.7K_0402_5%

TRXN0 TRXP0 TRXN1 TRXP1 TRXN2 TRXP2 TRXN3 TRXP3

RX_P

32 33 PLT_RST#

AR8151/AR8161

RX_N

<15> CLK_PCIE_LAN# <15> CLK_PCIE_LAN

Atheros

TX_P

VDDCT/ISOLAN

CLKREQ#

DVDDL/PPS DVDDL_REG/DVDDL

13 19 31 34 6

Near Pin13

Near Pin19

Near Pin31

CL20

Near Pin6

0.1U_0402_16V4Z

1U_0402_6.3V4Z CL21

CL19

CL18

0.1U_0402_16V4Z

CL17

0.1U_0402_16V4Z

+1.1_AVDDL +1.1_AVDDL +1.1_AVDDL +1.1_AVDDL_L +1.1_AVDDL

GCLK_LAN_25MHZ

MDI0MDI0+ MDI1MDI1+

LAN_RBIAS

+3V_LAN

+LX

+1.7_VDDCT

24 37

+LX_R

CL8

RL12 if use LDO modue

MDI0- <28> MDI0+ <28> MDI1- <28> MDI1+ <28>

1 RL8

+3V_LAN

2 2.37K_0402_1%

Place Close to PIN1

+LX RL10 1

30K_0402_5% 2

+3V_LAN

don't @ (could be B C cost done)

+2.7_AVDDH AVDDH/AVDD33 AVDDH AVDDH_REG

16 22 9

+3V_LAN +2.7_AVDDH +2.7_AVDDH

For EMI B Phaes change to GCLK@ @

Place Close to PIN1

GND

RL13 1

Place close to Pin16

12 11 15 14 18 17 21 20

AR8162-BL3A-R_QFN40_5X5 8162@

<34>

AVDDL AVDDL AVDDL AVDDL AVDDL_REG/AVDDL

CL16 10U_0603_6.3V6M

2 0.1U_0402_16V7K

10K_0402_5% RL12 2 LDO@ 1 mount

CL15 10U_0603_6.3V6M

CL11 1

38 39 23

CL14 1U_0402_6.3V4Z

PCIE_PRX_DTX_P1

LED_0 LED_1 LED_2

CL13 0.1U_0402_16V4Z

<15>

TX_N

CL12 1000P_0402_50V7K 1 2

PCIE_PRX_C_DTX_N1 29

Near Pin9

CL24

2 0.1U_0402_16V7K

0.1U_0402_16V4Z

1U_0402_6.3V4Z

CL9

0.1U_0402_16V4Z CL23

PCIE_PRX_DTX_N1

CL22

<15>

Switch mode regulator(SWR) mode

0 Linear regulator (LDO) mode

1U_0402_6.3V4Z

UL1

Place Close to Chip

Description

Configure signal

LED[1] Regulator select

CL10

QCA8172-BL3A-R

0.1U_0402_16V4Z

PLT_RST#

Near Pin22

2 0_0402_5%

1U_0402_6.3V4Z

<18,26,32>

+3V_LAN

8172@

CL25

0.1U_0402_16V4Z CL26

RL4

+3V_LAN

Near Pin37

value shoud be discuss ORB 5P A

4 1 CL28 15P_0402_50V8J NOGCLK@

YL1 NC OSC

OSC NC

CL27 5P_0402_50V8C @ LAN_XTALI 3

LAN_XTALO

1 25MHZ_10PF_7V25000014

CL29 15P_0402_50V8J NOGCLK@ NOGCLK@

Compal Secret Data

Security Classification Issued Date

2011/06/15

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

4019N1

Sheet 1

Rev B

ESD

Place Close to TL1

@ DL1 AZC099-04S.R7G_SOT23-6 1 I/O1 I/O3

MDI1+

Reserve gas tube for EMI go rural solution

MDI0+

DL1 1'S PN:SC300001G00 2'S PN:SC300002E00

MDI0-

GND

VDD

I/O2

I/O4

For EMI

MDI11

RL14

CL30 1 2

75_0805_5%

For EMI C

12/12 Change BOM Structure of CL31 from @ to mount(EMI request)

TL1

CL31 0.01U_0402_16V7K

<27> <27>

MDI0+ MDI0-

<27> <27>

MDI1+ MDI1-

MDI0+ MDI0-

MDI1+ MDI1-

1 2 3 4 5 6 7 8

TD+ TDCT NC NC CT RD+ RD-

TX+ TXCT NC NC CT RX+ RX-

16 15 14 13 12 11 10 9

CHASSIS1_GND

10P_0603_50V

DLL1 BS4200N-C-LV_SMB-F2 GAS@

MDO0+ MDO0MCT

Place Close to TL1

MCT MDO1+ MDO1-

For EMI

MHPC_NS681612A

CL63 1

2 0.1U_0603_50V7K

CHASSIS1_GND JLAN1

MCT

MDO1-

MCT

MDO1+

MDO0-

MDO0+

PR4PR4+

PR2PR3PR3+ PR2+ PR1PR1+ SHLD1 SHLD2 PS_HPKR0125-08A1A0R ME@

10 9

CHASSIS1_GND

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/06/15

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Document Number

SCHEMATIC M/B LA-9902

4019N1

Wednesday, May 08, 2013

Sheet 1

Rev B

2 Channel

SMSC thermal sensor placed near VRAM +3VS

1 1 C587 2200P_0402_50V7K @

REMOTE1+

REMOTE1-

+3VS

1 R335

U9 VDD

4.7K_0402_5%

SCLK

D+

SDATA

D-

ALERT#

THERM#

GND

EC_SMB_CK2

EC_SMB_DA2

EC_SMB_CK2

<15,32>

EC_SMB_DA2

<15,32>

6 5

EMC1402-2-ACZL-TR MSOP 8P

Address is 1001100xb

REMOTE1,2+/-: Trace width/space:10/10 mil Trace length:<8"

H6 H_3P8

H7 H_3P8

FD1

FD2

FD3

FD4

H5 H_3P8

H4 H_3P3

H2 H_3P3

CPU

H1 H_3P3

FAN1 Conn

VGA

MINI WLAN

+5VS

H19 H_2P8

H20 H_2P8

H22 H_2P8

H23 H_2P8

H16 H_3P0X4P0N

ACES_85205-04001 ME@

H24 H_3P0N

H25 H_3P0N

H15 H_2P8

H14 H_2P8

C591 10U_0603_6.3V6M

1 2 3 4 G5 G6

<32> EC_TACH EC_FAN_PWM

11/20 Change symbol of JFAN1 to SP020008X00

JFAN1

0_0603_5% <32>

1 2 3 4 5 6

R581 2

SP020008X00

M/B 橢圓孔 Compal Secret Data

Security Classification Issued Date

2011/06/15

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

4019N1

Date: Wednesday, May 08, 2013

M/B 圓孔

Sheet 1

Rev B 29

SATA HDD Conn. Near Connector <14> <14>

0.01U_0402_25V7K 2 0.01U_0402_25V7K 2

SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_N0

SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0

<14> SATA_DTX_C_IRX_N0 <14> SATA_DTX_C_IRX_P0

C596 1 C597 1

+3VS

1 C184 1 C185

SATA_ITX_DRX_P0 SATA_ITX_DRX_N0

2 0.01U_0402_25V7K 2 0.01U_0402_25V7K

SATA_DTX_IRX_N0 SATA_DTX_IRX_P0

R551 0_0805_5% 1 2 @

+5VS

+5VS_HDD

Near HDD 1

@ C598 1000P_0402_50V7K

GND RX+ RXGND TXTX+ GND

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

+3VS_HDD

R550 0_0805_5% 1 2

JHDD1

1 2 3 4 5 6 7

26 25

boss boss

24 23

GND GND

LCN_ASF98-2231S10-0002 ME@

1 C599 0.1U_0402_16V4Z

3.3V 3.3V 3.3V GND GND GND 5V 5V 5V GND Rsv GND 12V 12V 12V

C602 10U_0603_6.3V6M

ODD Power Control

1/16 Change footprint of JHDD1 from SANTA_191501-1_22P to LCN_ASF98-2231S10-0002_22P (DC010005W00 toDC010009C00)

1 +5VALW

1 2

R675 100K_0402_5% 2 @ @

GND

<14> <14>

SATA_ITX_C_DRX_P2 SATA_ITX_C_DRX_N2

SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2

<14> SATA_DTX_C_IRX_N2 <14> SATA_DTX_C_IRX_P2

1 1

OUT

1 2

Q99 PMV65XP_SOT23-3~D @

ODD_EN

<19>

SATA ODD FFC Conn.

Near Connector

R552 @ 10K_0402_5%

FOR 15"

+5V_ODD

JUMP_43X79

+5VS

R568 10K_0402_5% @

15@ 15@

C605 1 C606 1

R403 1 R404 1

15@ 15@

C608 10U_0603_6.3V6M <32>

C607 0.01U_0402_25V7K

ODD_DA# +3VS

2 0.01U_0402_25V7K 2 0.01U_0402_25V7K 2 0_0402_5% 2 0_0402_5%

1 R710

1 2 3 4 5 6 7 8 9 10

SATA_ITX_DRX_P2_15 SATA_ITX_DRX_N2_15 SATA_DTX_IRX_N2_15 SATA_DTX_IRX_P2_15 2 ODD_DETECT# +5V_ODD 0_0402_5%

ODD_DA# 1 R555 2 10K_0402_5%

1 2 3 4 5 6 7 8 9 10

GND GND

11 12

ACES_88058-100N ME@

Q100 DTC124EKAT146_SC59-3 @

JODD2

SP010016C00

11/20 Change symbol of JODD2 to SP010016C00

Co-lay

FOR 14"

SATA ODD Conn. Near Connector

JODD1

SATA_ITX_C_DRX_P2 14@C616 1 SATA_ITX_C_DRX_N2 14@C615 1

2 0.01U_0402_25V7K 2 0.01U_0402_25V7K

SATA_ITX_DRX_P2_14 SATA_ITX_DRX_N2_14

SATA_DTX_C_IRX_N2 14@C614 1 SATA_DTX_C_IRX_P2 14@C613 1

2 0.01U_0402_25V7K 2 0.01U_0402_25V7K

SATA_DTX_IRX_N2_14 SATA_DTX_IRX_P2_14

ODD_DETECT# +5V_ODD ODD_DA#

1 2 3 4 5 6 7 8 9 10 11 12 13

GND A+ AGND BB+ GND DP +5V +5V MD GND GND

GND GND GND GND

14 15 16 17

SANTA_202801-1 ME@

Compal Secret Data

Security Classification 2011/06/15

Issued Date

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

Date:

4019N1

Wednesday, May 08, 2013 G

Sheet

of H

Rev B 52

CX20757 High Definition Audio Codec SoC With Integrated Class-D Stereo Amplifier. An integrated 5 V to 3.3 V Low-dropout voltage regulator (LDO). An integrated 3.3 V to 1.8V Low-dropout voltage regulator (LDO).

RA5 RA6

JSENSE +VREF_1V65

RA7 RA8

2 5.11K_0402_1% 10K_0402_1%

1 1

2 20K_0402_1% 2 39.2K_0402_1%

For Universal jack

CA3 vendor suggest change to 2.2U

For no Speaker Hum Noise feature

Sense resistors must be connected same power that is used for VAUX_3.3

CA9

2 33_0402_5%

5 8 6 4

EC_MUTE#

2 0.1U_0402_16V7K

CA65 1

2 0.1U_0402_16V7K

CA66 1

2 0.1U_0402_16V7K

Internal analog MIC

Internal SPEAKER

MIC_IN

36 37

SPK_L2+ SPK_L1-

12 14

SPK_R2+ SPK_R1-

17 15

0.1U_0402_16V4Z

CA3

PORTB_L_LINE PORTB_R_LINE

PORTD_A_MIC PORTD_B_MIC DMIC_DAT/GPIO1 HGNDA DMIC_CLK / MUSIC_REQ/GPIO0 HGNDB MUSIC_REQ/GPIO0/PORTC_L_MIC GPIO1/PORTC_R_MIC

PORTA_L PORTA_R

For Layout

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K CA23

0.1U_0402_16V4Z CA22

CA20 2

13 16 11

0.1U_0402_16V4Z CA21

CA18

0.1U_0402_16V4Z

Please bypass caps very close to device.

JSENSE

34 35

For EMI

+MICBIASB +MICBIASC

32 33

MICB_L MICB_R

30 31 25 26

APPLE_MIC NOKIA_MIC HGNDA HGNDB

22 23

HP_L HP_R

APPLE_MIC NOKIA_MIC HP_L HP_R

Universal Jack External MIC

RA16 RA12 RA13 RA14

1 1 1 1

RIGHT+ RIGHT-

21 19 20

1 CA29

2 1U_0603_10V4Z

CX20751-11Z_QFN40

12/12 Change BOM Structure of CA64~CA66 from @ to mount(EMI request)

2 2 2 2

CA28 1 CA27 1

100_0402_1% 100_0402_1% 15_0402_5% 15_0402_5%

2 2.2U_0402_6.3V6M 2 2.2U_0402_6.3V6M

HGNDB HGNDA HPOUT_L HPOUT_R

HGNDB <33> HGNDA <33> HPOUT_L <33> HPOUT_R <33>

For Universal jack

LEFT+ LEFTAVEE FLY_P FLY_N

HGNDA, HGNDB 80mils

Headphone

GND

CA64 1

JSENSE MICBIASB MICBIASC

PC_BEEP SPKR_MUTE#

1 40

For EMI

LPWR_5.0 RPWR_5.0 CLASS-D_REF

BIT_CLK SYNC SDATA_IN SDATA_OUT

10 39

PC_BEEP <32>

RESET#

For Layout

CA30

HDA_BITCLK_AUDIO HDA_SYNC_AUDIO HDA_SDIN0_R HDA_SDOUT_AUDIO

2.2U_0603_6.3V4Z

HDA_BITCLK_AUDIO

HDA_RST_AUDIO#

+5VS

CA35

HDA_RST_AUDIO#

RA9

UA1

33_0402_5%

CA26

4.7U_0603_6.3V6K CA19

CA24

0.1U_0402_16V4Z

@ 1 RA21

+5VS

10 mils

0.1U_0402_16V4Z

<14>

HDA_SYNC_AUDIO <14> HDA_SDIN0 HDA_SDOUT_AUDIO

AVDD_3.3 pinis output of internal LDO. NOT connect to external supply.

+LDO_1.8V

27 28 24

AVDD_3.3 AVDD_5V AVDD_HP

22P_0402_50V8J

<14>

<33>

PLUG_IN

Layout Note:Path from +5VS to LPWR_5.0 RPWR_5.0 must be very low resistance (<0.01 ohms)

VREF_1.65V

@ CA7

<14>

3 7 2 18

For EMI <14>

FILT_1.8 VDD_IO VDDO_3.3 DVDD_3.3

PLUG_IN

Don't support LINE_IN function RA7 could be @

+VDDIO_HDA

0.1U_0402_16V4Z

2 0_0402_5%

4.7U_0603_6.3V6K CA25

+3VS

0.1U_0402_16V4Z

2 0_0402_5%

CA17

4.7U_0603_6.3V6K

+3V_PCH

RA4

CA16

+3VS

RA3 @

CA15

Should be same supply rail as used for PCH HDA bus controller section

0.1U_0402_16V4Z

CA8

1U_0603_10V4Z

+3VS

2.2U_0603_6.3V4Z CA4

0.1U_0402_16V4Z

CA1

2 0_0402_5%

CA10

0.1U_0402_16V4Z

1U_0603_10V4Z

RA10

CA6

+3V_PCH

+3V_AVDD_HP 4.7U_0603_6.3V6K

2 0_0402_5%

CA5

0.1U_0402_16V4Z

+3VLP

1U_0603_10V4Z CA2

+LDO_OUT_3.3V RA11

+3VS

mount RA6 on the Jack Sense circuit to configure Port-C for mono MIC.

MICB_L

RA17 1

2 100_0402_1%

MICB_R

RA18 1

2 100_0402_1%

RA20 1

2 3K_0402_5%

RA19 1

2 3K_0402_5%

+MICBIASB

CA36 1 2 2.2U_0402_6.3V6M CA46 1 2 2.2U_0402_6.3V6M

HP_L HP_R

follow vendor suggest & reserver default design

PC_BEEP

SPK_R1SPK_R2+ SPK_L1SPK_L2+

Place colose to Codec chip

2 FBMA-L11-160808-121LMT_0603 2 FBMA-L11-160808-121LMT_0603 2 FBMA-L11-160808-121LMT_0603 2 FBMA-L11-160808-121LMT_0603

For EMI

1 2

WM-64PCY_2P MIC@

EXT_MIC GNDA 1

CA41

1U_0603_10V4Z 2

ESD

SPK_R1-_CONN

MIC_IN

SPK_R2+_CONN

4 3 2 1

ME@ ACES_88231-04001

DA3 I/O4

I/O2

VDD

GND

I/O3

I/O1

SPK_L2+_CONN

2 A

SPK_L1-_CONN

Compal Secret Data

Security Classification 2011/06/15

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

4019N1

GND2 GND1

AZC099-04S.R7G_SOT23-6

Issued Date

JSPK1

SP02000H700

+5VS

CA44 0.1U_0402_16V4Z

CA42 0.1U_0402_16V4Z

MIC1

RA23 2.2K_0402_5%

4 3 2 1

SPK_R1-_CONN SPK_R2+_CONN SPK_L1-_CONN SPK_L2+_CONN

1 1 1 1

For EMI

+MICBIASC

RA22 10K_0402_5% @

LA1 LA2 LA3 LA4

6 5

1000P_0402_50V7K

1 2 33_0402_5%

wide 40MIL

1000P_0402_50V7K CA43

HDA_SPKR

RA492

1000P_0402_50V7K CA40

<14>

1 2 CA37 0.1U_0402_16V4Z 1 2 CA45 0.1U_0402_16V4Z

BEEP#

ICH Beep

<32>

11/20 Change symbol of JSPK1 to SP02000H700

CA38

EC Beep

LA2 0_0603_5% @ LA4 0_0603_5% @

1000P_0402_50V7K CA39

PC Beep

LA1 0_0603_5% @ LA3 0_0603_5% @

Date: Wednesday, May 08, 2013

Sheet

Rev B 52

100P_0402_50V8J

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17

KSO[0..17]

ESD

KSI[0..7]

+3V_EC

1 1

R600 R604

2 EC_SMB_CK1 2.2K_0402_5% 2 EC_SMB_DA1 2.2K_0402_5%

<38,39> <38,39> <15,29> <15,29>

+3VALW

R606

<16> PM_SLP_S3# <16> PM_SLP_S5# <16,19> EC_SMI# <23> CMOS_ON#

EC_TACH 10K_0402_5%

PCH_PWROK

<33>

SUSCLK

<18>

DGPU_PWR_EN

<16>

1 @ R608 10K_0402_5%

<33> NOVO# NUM_LED#

<16>

R740 100K_0402_5% @

<30> ODD_DA# <37> ADP_ID_CLOSE <29> EC_TACH <27> LAN_WAKE# <26> EC_TX <26> EC_RX

R605

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

LAN_WAKE# 10K_0402_5%

+3VS

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

C93 20P_0402_50V8 @

EC_SMI#

ODD_DA# ADP_ID_CLOSE EC_TACH LAN_WAKE# EC_TX EC_RX PCH_PWROK NOVO# NUM_LED#

DGPU_PWR_EN

55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 77 78 79 80

6 14 15 16 17 18 19 25 28 29 30 31 32 34 36

122 123

67 EC_VDD/AVCC

SPI Device Interface SPI Flash ROM

GPIO Bus

GPIO

SPIDI/GPIO5B SPIDO/GPIO5C SPICLK/GPIO58 SPICS#/GPIO5A

ENBKL/GPIO40 PECI_KB930/GPIO41 FSTCHG/GPIO50 BATT_CHG_LED#/GPIO52 CAPS_LED#/GPIO53 PWR_LED#/GPIO54 BATT_LOW_LED#/GPIO55 SYSON/GPIO56 VR_ON/GPIO57 PM_SLP_S4#/GPIO59

EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04 PROCHOT_IN/GPXIOA05 H_PROCHOT#_EC/GPXIOA06 VCOUT0_PH/GPXIOA07 GPO BKOFF#/GPXIOA08 PBTN_OUT#/GPXIOA09 PCH_APWROK/GPXIOA10 SA_PGOOD/GPXIOA11 AC_IN/GPXIOD01 EC_ON/GPXIOD02 ON/OFF/GPXIOD03 GPI LID_SW#/GPXIOD04 SUSP#/GPXIOD05 GPXIOD06 PECI_KB9012/GPXIOD07

PN : SA00004OB20

ADP_65 BEEP# EC_FAN_PWM ACOFF

63 64 65 66 75 76

BATT_TEMP GPU_IMON ADP_I ADP_ID BRDID

68 70 71 72

ADP_90

ADP_65 <38> BEEP# <31> EC_FAN_PWM ACOFF <39>

15K +/- 1% 20K +/- 1%

V V V

typ

V V V

max EC V 0x00 V 0x0C V 0x1D V 0x27

VAD_BID 0.300 0.360 0.438 0.559

AD - 0x0B - 0x1C - 0x26 - 0x30

MP PVT DVT EVT

+3VALW

<29>

2 EC_MUTE#/GPIO4A USB_EN#/GPIO4B CAP_INT#/GPIO4C EAPD/GPIO4D TP_CLK/GPIO4E TP_DATA/GPIO4F

CPU1.5V_S3_GATE/GPXIOA00 WOL_EN/GPXIOA01 HDA_SDO/GPXIOA02 VCIN0_PH/GPXIOD00

PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 GPIO0A GPIO0B GPIO0C GPIO0D EC_INVT_PWM/GPIO11 FAN_SPEED1/GPIO14 EC_PME#/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 PCH_PWROK/GPIO18 SUSP_LED#/GPIO19 NUM_LED#/GPIO1A

XCLKI/GPIO5D XCLKO/GPIO5E

V18R

83 84 85 86 87 88

ENBKL

USB_ON# ADP_135 SYS_PWROK_R TP_CLK TP_DATA

119 120 126 128

EC_SPI_SO EC_SPI_SI EC_SPI_CLK EC_SPI_CS#

R594

USB_ON# 1

<38>

1 R593

R695

@ R695 12K_0402_1%

10K_0402_5%

HM70@ 27K_0402_1%

10K_0402_5% EC_MUTE# <31> USB_ON# <33,35> ADP_135 <38> SYS_PWROK <16>

0_0402_5%

TP_CLK <33> TP_DATA <33>

+5VS TP_CLK R603 1 TP_DATA R598 1

<35>

EC_TS_ON#

ME_FLASH

2 4.7K_0402_5% 2 4.7K_0402_5%

ME_FLASH <14> NTC_V <38>

10/26 Add(Reserve for SPI ROM Interface share)

EC_SPI_SO <14> EC_SPI_SI <14> EC_SPI_CLK <14> EC_SPI_CS# <14>

BATT_CHG_LED# CAPS_LED#

1 C663 1 C664

3/20 Add (ESD request) IMVP_IMON <44> VGATE <16,44> LAN_PWR_ON# <27> BATT_CHG_LED# <33>

CAPS_LED# <33> PWR_LED# <33> BATT_LOW_LED# <33> SYSON <41> VR_ON <44> PM_SLP_S4# <16>

BATT_LOW_LED# SYSON

BATT_TEMP ACIN

VGATE

2 100P_0402_50V8J 2 100P_0402_50V8J

1 R522 2 4.7K_0402_5% @

+5VS

2 C851 0.1U_0402_16V4Z

H_PROCHOT# EC_RSMRST# <16> EC_LID_OUT# <19>

EC_LID_OUT# Turbo_V

R738 1

MAINPWON_R BKOFF# PBTN_OUT# PCH_PWR_EN

110 112 114 115 116 117 118

LID_SW# SUSP# NUVOTON_VTT PECI_KB9012

124

+V18R

KB9012QF A4 LQFP 128P_14X14

BRDID

<17>

ADP_90

R417 1

R694 100K_0402_1%

+5VALW

<37>

+3VALW

EC_TS_ON#

100 101 102 103 104 105 106 107 108

ADP_ID

EC_MUTE#

97 98 99 109

73 74 89 90 91 92 93 95 121 127

BATT_TEMP <37,38> GPU_IMON <44>

<38,39>

ADP_I

BATT_TEMP/GPIO38 GPIO39 ADP_I/GPIO3A GPIO3B GPIO42 IMON/GPIO43 DAC_BRIG/GPIO3C EN_DFAN1/GPIO3D IREF/GPIO3E CHGVADJ/GPIO3F

PS2 Interface

21 23 26 27

12K +/- 1%

V AD_BID 0 V 0.354 0.430 0.550

min

9 22 33 96 111 125

AD Input

DA Output

EC_SMB_CK1/GPIO44 EC_SMB_DA1/GPIO45 SM EC_SMB_CK2/GPIO46 EC_SMB_DA2/GPIO47

GPIO0F BEEP#/GPIO10 GPIO12 ACOFF/GPIO13

PWM Output

CLK_PCI_EC PCIRST#/GPIO05 EC_RST# EC_SCII#/GPIO0E GPIO1D

KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49

U31

VAD_BID 0 V 0.347 0.423 0.541

BKOFF# <23> PBTN_OUT# <16> PCH_PWR_EN <20> SA_PGOOD <42>

Turbo_V <38> PROCHOT <38> MAINPWON <40>

0_0402_5%

PROCHOT

2 G Q37 2N7002H_SOT23-3

<37,44,6>

C493 47P_0402_50V8J

+3VALW

ACIN EC_ON

EC_RST# EC_SCI# BATT_LEN#

0 1 2 3

EC_SCI# BATT_LEN#

GATEA20/GPIO00 KBRST#/GPIO01 SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC & MISC LPC_AD0

R695 0

Board ID

ACIN <16,37,39> EC_ON <40> ON/OFF <33> LID_SW# <33> SUSP# <36,41,43>

R669

2 43_0402_1%

H_PECI

LID_SW#

<6>

1 R618 2 100K_0402_5%

NUVOTON_VTT

R410 1

+V1.05S_VCCP

0_0402_5%

2 EMC Request SYSON

S IC KB9012QF A3 LQFP 128P KB CONTROLLER

0.1U_0402_10V6K C492

<19> <38>

+EC_VCCA

3.3V 100K +/- 1%

C667

C47

Vcc R694

4.7U_0603_6.3V6K

C661 0.1U_0402_16V4Z

<33>

CLK_PCI_EC

PLT_RST#

<33>

<18>

12 13 37 20 38

AGND/AGND

10_0402_5%

LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

1 2 3 4 5 7 8 10

ECAGND

<19> GATEA20 <19> KBRST# <14> SERIRQ <14> LPC_FRAME# <14> LPC_AD3 <14> LPC_AD2 <14> LPC_AD1 <14> LPC_AD0

C535 100P_0402_50V8J @

EC_VDD/VCC EC_VDD/VCC EC_VDD/VCC EC_VDD/VCC EC_VDD0 EC_VDD/VCC

11 24 35 94 113

2 1 2 1 @ C660 22P_0402_50V8J @ R589 <18,26,27> 2 47K_0402_5%

GND/GND GND/GND GND/GND GND/GND GND0

ECAGND

1 R590

@ 0_0603_5%

C658 1000P_0402_50V7K

C657 1000P_0402_50V7K

C654 0.1U_0402_16V4Z

C653 0.1U_0402_16V4Z

+EC_VCCA

1 C656 0.1U_0402_16V4Z 2 ECAGND 1 2 L45 FBM-11-160808-601-T_0603

+3V_EC

L44 FBM-11-160808-601-T_0603 1 2

+3V_EC

+3VLP

R416

+3V_EC

R304 2 1 0_0603_5% @

+3VALW

Compal Secret Data

Security Classification Issued Date

2011/06/15

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

4019N1

Wednesday, May 08, 2013

Sheet

Rev B

Key Board Conn.

+3VLP

1 R414 2 0_0402_5%

KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15 KB1 KB2 KB_LED_PWR

+3VALW 2

+3VLP

ON/OFF

+3VS

D26 1

NOVO_BTN# 1

NOVO#

ON/OFF

DAN202UT106_SC70-3

<32>

R745 300_0402_5% 15@

R744 300_0402_5% 2

ON/OFF

NOVO#

R642 100K_0402_5% R701 100K_0402_5%

<32>

CAPS_LED#

<32>

NUM_LED#

KSI[0..7]

KSO[0..17]

For 15"

R415 100K_0402_5% @

<32>

KSI[0..7]

PWR Button For Debug

KB_LED_PWR_2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

KSO[0..17]

For 14"

JKB1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

GND GND

KSO16 KB_LED_PWR KSO17 CAPS_LED#

31 32

R747 R746 R748 R749

15@ 14@ 15@ 14@

1 1 1 1

2 2 2 2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15 KB1 KB2

0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%

ACES_88514-3001 ME@

<32> <32>

JKB2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 GND2 GND1

27 28

ACES_88514-02601-071 ME@

SP010011A00

11/20 Change symbol of JKB1 to SP010011A00

IO/B Conn.

For EMI

<18> +5VALW

<32,35>

USB20_N9

USB20_P9

+USB_VCCB

USB_ON#

GND VOUT VIN VOUT VIN VOUT EN FLG

L66 4

USB20_N9_R

USB20_P9_R

WCM-2012-900T_4P

8 7 6 5

R869 2

+USB_VCCB

1 0_0402_5%

@ R503 10_0402_5%

1 2 3 4

U36

+3VS

1 0_0402_5%

<18>

R868 2

USB_OC4#

<18>

@ C701 1.2P_0402_50V8C

G547I2P81U_MSOP8

@ R504 10_0402_5%

C714 220U_6.3V_M

Ext. USB2.0

@ C702 1.2P_0402_50V8C

<18> <18>

W=80mils

14 13 12 11 10 9 8 7 6 5 4 3 2 1

USB20_N11 USB20_P11

USB20_N9_R USB20_P9_R

+USB_VCCB 1 1 + C715 470P_0402_50V7K 2 2

HPOUT_L HPOUT_R HGNDA HGNDB PLUG_IN

<31> HPOUT_L <31> HPOUT_R <31> HGNDA <31> HGNDB <31> PLUG_IN

6.3Î¦ * 5.9 SF000001500

JIO1 14 G2 13 G1 12 11 10 9 8 7 6 5 4 3 2 1

16 15

ACES_85202-1405N ME@

11/30 Change U36 symbol & PN from SA00003XM00 to SA00003TV00

LED

TP Switch & TP Conn.

PWR/B Conn.

+5VS

LED1 14@ <32>

5 6

5 6 TP_3

TP_2

<32>

ME@ ACES_88058-060N

BATT_CHG_LED#

TP_2

D24

2 R765 1 300_0402_5%

VCC

CLK

DAT

GND

R GND

+3VALW

LID_SW# PWR_LED# BATT_LOW_LED# BATT_CHG_LED#

1 2 3 4 5 6 7 8

ESD +3VALW

JLED1 1 2 3 4 5 6

<32>

12/4 Change symbol of JLED1 to SP010010T00

Issued Date

11/30 Change PN of U40 from SA000031C00 to SA00005LN00

SP010010T00

Compal Secret Data

Security Classification 2011/06/15

LID_SW#

OUTPUT

2 C550 14@ 10P_0402_50V8J 1

GND GND ACES_88058-060N ME@

For 15"

GND GND

SP010010T00

Lid SW(For 14")

1 2 3 4 5 6

11/20 Change symbol of JPWRB1 to SP010010T00

+3VALW

14@ 19-213A-T1D-CP2Q2HY-3T_WHITE

14"

JPWRB1

ACES_88058-060N ME@

L30ESD24VC3-2 3P C/A SOT-23

11/20 Change symbol of JTP1 to SP010010T00

7 8

+3VALW

TP_1

3 2 R764 1 470_0402_5%

LED5 14@

15"

SW7 15@ SMT1-05_4P

BATT_LOW_LED#

14@ 19-217-S2C-FM2P1VY-3T_ORANGE

SP010010T00 1

BATT_LOW_LED#

VDD

NOVO_BTN# ON/OFF

LED2 14@ <32>

6 5 4 3 2 1

LED/B Conn.

SW5 14@ SMT1-05_4P

SW6 15@ SMT1-05_4P

GND GND

SW4 14@ SMT1-05_4P

5 6

JTP1

1 2 3 4 5 6

+3VALW

14@ 19-213A-T1D-CP2Q2HY-3T_WHITE

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

1 14@ C551 0.1U_0402_16V4Z 2

GND

2 R619 1 14@ TP_1 0_0402_5%

2 R623 1 300_0402_5%

TP_3

15@ 2 R627 1 0_0402_5%

0.1U_0402_10V6K C491

TP_CLK TP_DATA

0.1U_0402_10V6K C490

<32> <32>

6 5 4 3 2 1

PWR_LED#

8 7 TP_CLK TP_DATA TP_3 TP_2 TP_1

PWR_LED#

14@ U40 S-5712ACDL2-M3T1U_SOT23-3

Compal Electronics, Inc.

SCHEMATIC M/B LA-9902 Document Number

Rev B

4019N1

Wednesday, May 08, 2013

Sheet

For UMA U71

Every power trace need: W=20mils

GCLK244@

SLG3NB244VTR_TQFN16_2X3

For GreenCLK generate CLK: Mount: All parts in this page except Swing Level RES (Marked "*") NA: PD108, Y1,R98,C180,C181, Y2,R169,C196,C197, Y6,C968,C969

+CHGRTC_R +RTCBATT

1 +3VLP

1 1

Y8 NC OSC

OSC NC

2 32kHz

VDDIO_27M

3 1 16

27MHz

VDDIO_25M_A

25MHz_A

VDDIO_25M_B

25MHz_B

XTAL_IN XTAL_OUT

SLG3NB304VTR_TQFN16_2X3 GCLK@ CG9 15P_0402_50V8J

VDD

GCLK@ 25MHZ_10PF_7V25000014

GREENCLK_XTALI GREENCLK_XTALO

VDD_RTC_OUT

For EMI

+V3.3A

GCLK@ CG8 15P_0402_50V8J

VBAT

PCH_GCLK

CG4 2.2U_0402_6.3V6M 2 GCLK@

U71 10

@ 2 1 +3VS_GCLK CG1 0.1U_0402_16V7K

For DIS

GND4

CG3 GCLK@ 22U_0805_6.3V6M

RG1

GCLK_LAN_25MHZ_R RG3

GCLK_PCH_25MHZ_R RG4

GCLK_32K_R

GCLK@

2 0_0402_5%

GCLK_32K

PCH_32.768K

<14>

12 GCLK@ GCLK@

2 0_0402_5% GCLK_LAN_25MHZ 2 0_0402_5% GCLK_PCH_25MHZ

GCLK_LAN_25MHZ

<27>

GCLK_PCH_25MHZ

<15>

Close to GCLK

LAN PCH_25M

0.1U_0402_16V7K

1 0.1U_0402_16V7K

@ 1 CG2 0.1U_0402_16V7K

1 2 @ CG7

RG11 0_0402_5% GCLK@ @ CG5

+GCLK_VBAT

GCLK@ RG8 2 1 0_0402_5%

RG10 @ 0_0402_5%

GND1 GND2 GND3

+3V_LAN

4 7 13

+3V_LAN

+V1.05S_VCCP

RG12 390_0402_5% GCLK@

GCLK304@

Reserved for Swing Level adjustment ( Close GCLK side ) *1

RG7 * 1

GCLK_LAN_25MHZ RG6 GCLK_PCH_25MHZ

2 0_0402_5% 2 0_0402_5%

For EMI

Compal Secret Data

Security Classification Issued Date

2011/06/15

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc. Document Number

4019N1

SCHEMATIC M/B LA-9902

Wednesday, May 08, 2013

Rev B

Sheet E

Touch Screen +3VS

+3VS_TS

1 TS@

EC_TS_ON#

<18> USB20_N2 <18> USB20_P2

Q156 PMV65XP_SOT23-3 @

1 C669 0.1U_0402_16V7K

1 2 3 4 5 6 7 8

<32>

R798 @ 100K_0402_5% 1 2

+3VS_TS

0_0402_5%

2 @

C668 TS@

EC_TS_ON#

0.1U_0402_16V7K

R799

R726 1

TS@ 2 0_0402_5% TS_RST#

JTS1 D

1 2 3 4 5 6 GND GND ACES_50208-00601-P01 ME@

SP010013W10

11/20 Change symbol of JTS1 to SP010013W10

USB3.0 2A/Active Low

ESD

+5VALW

<32,33>

+USB3_VCCA

1 2 3 4

USB_ON#

U35

GND VOUT VIN VOUT VIN VOUT EN FLG

W=80mils

8 7 6 5

U3RXDN1 9 10

USB_OC0#

<18>

G547I2P81U_MSOP8

D27 1 1U3RXDN1

U3RXDN2 9 10

1 + C736 220U_6.3V_M SF000002Y00 2

2 2U3RXDP1

U3RXDP2 8

2 2U3RXDP2

U3TXDN1 7

4 4U3TXDN1

U3TXDN2 7

4 4U3TXDN2

U3TXDP1 6

5 5U3TXDP1

U3TXDP2 6

5 5U3TXDP2

470P_0402_50V7K @

For EMI

YSCLAMP0524P_SLP2510P8-10-9

Intel_PCH_USB2.0

U2DN1

3 3

1 C735

D22

D30 1 1U3RXDN2

3 3

11/30 Change U35 symbol & PN from SA00003XM00 to SA00003TV00

U3RXDP1 8

D31

I/O2

I/O4

GND

VDD

I/O1

I/O3

U2DP2

+5VALW

U2DP1

AZC099-04S.R7G_SOT23-6

I/O2

I/O4

GND

VDD

I/O1

I/O3

+5VALW

U2DN2

AZC099-04S.R7G_SOT23-6

YSCLAMP0524P_SLP2510P8-10-9

For EMI

Intel_PCH_USB2.0

WCM-2012-900T_4P <18>

USB20_N0

<18>

USB20_P0

L51

USB2@

WCM-2012-900T_4P

U2DN1

U2DP1

<18>

USB20_N1

<18>

USB20_P1

1 4

4 USB2@ 3 L55

U2DN2

U2DP2

U3RXDN2

U3RXDP2

Left Ext.USB Conn. 1

Left Ext.USB Conn. 2

Intel_PCH_USB3.0 WCM-2012-900T_4P <18>

USB3_RX1_N

<18>

USB3_RX1_P

1 4

L50

<18>

USB3_TX1_N

<18>

USB3_TX1_P

1 1

C849 .1U_0402_16V7K 2 U3TXDN1_L USB3@

2 U3TXDP1_L USB3@ C847 .1U_0402_16V7K

USB3@

+USB3_VCCA

U3RXDN1

U3RXDP1

W=80mils U3TXDP1 U3TXDN1 U2DP1 U2DN1 U3RXDP1

WCM-2012-900T_4P

1 4

1 4 L49

USB3@

2 3

U3TXDN1 U3TXDP1

Intel_PCH_USB3.0

U3RXDN1

9 1 8 3 7 2 6 4 5

<18>

USB3_RX2_N

<18>

USB3_RX2_P

WCM-2012-900T_4P

JUSB1

SSTX+ VBUS SSTXD+ GND_D DSSRX+ GND SSRX-

GND1 GND2 GND3 GND4

4 USB3@ 3 L54

+USB3_VCCA

W=80mils U3TXDP2 U3TXDN2 U2DP2

10 11 12 13

OCTEK_USB-09EAAB ME@

<18>

USB3_TX2_N

<18>

USB3_TX2_P

1 1

U2DN2 U3RXDP2

C850 .1U_0402_16V7K 2 U3TXDN2_L USB3@

WCM-2012-900T_4P

2 U3TXDP2_L USB3@ C848 .1U_0402_16V7K

4 USB3@ 3 L53

U3TXDN2

U3TXDP2

U3RXDN2

9 1 8 3 7 2 6 4 5

JUSB2

SSTX+ VBUS SSTXD+ GND_D DSSRX+ GND SSRX-

GND1 GND2 GND3 GND4

10 11 12 13

OCTEK_USB-09EAAB ME@

Place TX AC coupling Cap (C843~C850). Close to connector

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/06/15

Deciphered Date

2012/07/11

Title

SCHEMATIC M/B LA-9902

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev B

4019N1

Date:

Wednesday, May 08, 2013 1

Sheet

+5VALW to +5VS

1 R647 470K_0402_1%

82K_0402_5% Q110 2N7002_SOT23

100U_1206_6.3V6M 1

15VS_GATE_R

C737 100U_1206_6.3V6M @

2 G

SUSP

C726 0.01U_0402_25V7K

Q111 2N7002_SOT23 3

2 1

5VS_GATE2 R649

2 G 3

@ C725 1U_0603_10V4Z

+3VALW

R646 150K_0402_5%

SUSP

+VSB

C724

C723

@ C722 1U_0603_10V4Z

4.7U_0603_6.3V6K

+3VS

U39 DMN3030LSS-13_SOP8L-8 8 1 7 2 6 3 5 4

4.7U_0603_6.3V6K

DMN3030LSS-13_SOP8L-8 8 1 7 2 6 3 5

+3VALW

C721

+3VALW to +3VS

+5VS

C720

4.7U_0603_6.3V6K

U38

4.7U_0603_6.3V6K

+5VALW

C727 0.01U_0402_25V7K

C738 @

C739 100U_1206_6.3V6M @

1/28 Add 2

+1.5VS

C718

C717

1 2

@ C719 1U_0603_10V4Z

+3VALW 1

2 SUSP G Q115 2N7002_SOT23

R658 22_0603_5%

Q8 PMV65XP_SOT23-3~D S

4.7U_0603_6.3V6K

+1.5V

4.7U_0603_6.3V6K

+0.75VS

+1.5V to +1.5VS

For Intel S3 Power Reduction.

+3VLP

Q112

@ R653 100K_0402_5%

C729 0.1U_0402_10V7K

OUT

Q117 DTC124EKAT146_SC59-3

SUSP

R652 220K_0402_5% <10>

SUSP# 2 G 2N7002_SOT23

+RTCVCC 3

100K_0402_5% R648 R651 2 1 1.5VS_GATE @ 0_0402_5%

GND

SUSP#

<32,41,43>

R795 @ 100K_0402_5%

Compal Secret Data

Security Classification Issued Date

2011/06/15

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc.

Date:

4019N1

SCHEMATIC M/B LA-9902

Wednesday, May 08, 2013

Rev B

Sheet E

PR102 750_0402_1%

PR112

100K_0402_5%

+CHGRTC

<32>

1 2

+3VLP

+CHGRTC_R C

PR101 1K_0603_5% 1 2

JRTC1 @ 1 2 1 3 2 4 GND GND

JRTC2 @ 1 2 1 3 2 4 GND GND

ACES_50271-0020N-001

RTC Battery

ACES_50271-0020N-001 +5VS

@ PC106 2 1

2 PR108

10K_0402_1%

1 2 PR109 1

+ -

5 ACIN

<16,32,39>

PU101B AS393MTR-E1 SO 8P OP 4

2 PR105 1

0.022U_0402_16V7K

1.5M_0402_5%

PD104

1N4148WS-7-F_SOD323-2 2 1

PR107 1

2N7002KDW-2N_SOT363-6 4 3

H_PROCHOT#

PQ101B

BATT_TEMP <32,38>

+5VS

3 2

100K_0402_1%

0.022U_0402_16V7K

PC107 100P_0402_50V8J 2 1

O 4

PR104 1

1.5M_0402_5%

@ PC105 2 1

@ PU101A AS393MTR-E1 SO 8P OP

+3VALW

PR106 1

6 1

1N4148WS-7-F_SOD323-2 PD105 2 1

PQ101A 2N7002KDW-2N_SOT363-6

H_PROCHOT#

<32,44,6>

47K_0402_1%

+RTCBATT

PR103 1K_0603_5% 1 2

ADP_ID

A/D

ADP_ID_CLOSE

47K_0402_1%

PD101 S SCH DIO BAS40CW SOT-323 2 1 3

PQ102B L2N7002DW1T1G_SC88-6 4 3

PR111 100K_0402_5% 1 2 1

VIN

EMI@ PC104 1000P_0402_50V7K

1 2

PQ102A L2N7002DW1T1G_SC88-6 6 1 1

+3VALW

PC109 680P_0603_50V7K

1 2

FBCA-K5B-302540-L1-T_2P

PF101 7A_24VDC_429007.WRML

ACES_88299-0510 CONN@

EMI@ PC103 100P_0402_50V8J

EMI@ PL101 1 2

APDIN1

PC108 0.1U_0402_16V7K

APDIN

ADP_ID AC Adapter 90W 65W R(K ohm) open 10 ADP_ID(V) 3.3 1.65 Detection voltage >2.64 1.32~1.98

VIN 1 2 3 4 5

EMI@ PC102 100P_0402_50V8J

1 2 3 4 5

EMI@ PC101 1000P_0402_50V7K

JDCIN1

Compal Secret Data

Security Classification Issued Date

2011/06/15

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

VILG1/G2 MB LA9902P Schematic

Wednesday, May 08, 2013

Sheet

Rev B

1 2 3 4 5 6 7 8 9

EMI@ PL201 FBCA-K5B-302540-L1-T_2P 1 2

BATT+

90W(DIS) : 6.65K 100W active 90W recovery 65W(UMA): 1.65K 70W active 65W recovery

PH201 under CPU botten side : CPU thermal protection at 93 +-3 degree C Recovery at 56 +-3 degree C

+3VALW

A/D

+EC_VCCA <32,39> PROCHOT 1

<32>

ADP_I

NTC_V

Turbo_V

PH201 100K_0402_1%_TSM0B104F4251RZ

SHDN#

BYP

G9191-330T1U_SOT23-5

@ PC213 4.7U_0402_6.3V6M 2 1

OUT

GND

PR974 5.9K_0402_1%

2 1 3

2 G

PQ207 2N7002KW_SOT323-3

PQ206B

PR973 9.31K_0402_1%

2 3 4

6 1

1 3

ECAGND D

<32>

ADP_65

ECAGND

<32>

ADP_90

ADP_135

ECAGND

4 S

BATT_LEN#

@ PQ208 2N7002KW_SOT323-3

<32> D

2 G

1 2 PR220 100K_0402_1%

1 1

<32> ECAGND

PJ202 @ JUMP_43X39 1 2 1 2

+VSB

+3VLP

2 G

PQ205 2N7002KW_SOT323-3

+3V_LDO

Compal Secret Data

Security Classification

PC211 1U_0402_16V6K @

@ PU202

PU201B AS393MTR-E1 SO 8P OP

@ PC209 0.068U_0402_16V7K~N 1 2 @ PR208 1.5M_0402_5% 1 2

+5VALW @ PC212 22U_0603_6.3V6M 2 1

1 6

O G

8 5

@ PC210 100P_0402_50V8J 2 1

@ PR203 75K_0402_1%

@ PR212 47K_0402_1%

@ PR215 100K_0402_1%

+3V_LDO

VMB

1.5M_0402_5%

PR222 10K_0402_1%

B+

PR205 PC207 100P_0402_50V8J

PQ202B L2N7002DW1T1G_SC88-6

2 PR213 100K_0402_1%

PD201 1N4148WS-7-F_SOD323-2

PU201A AS393MTR-E1 SO 8P OP

@ PD202 1N4148WS-7-F_SOD323-2

BATT_TEMP

2 B

PC208 0.068U_0402_16V7K~N

1 <32,37,38>

<39>

PQ202A L2N7002DW1T1G_SC88-6

PR210 47K_0402_1%

2 BATT_OUT

2N7002KDW-2N_SOT363-6

2 100K_0402_1%

6 1

0.01U_0402_25V7K

PR202 75K_0402_1%

100K_0402_1%

PR211

PC202

PR214

2N7002KDW-2N_SOT363-6

+3VALW 2

PQ206A

PR972 25.5K_0402_1%

<32>

2 1 PR226 12.7K_0402_1%

BATT_TEMP <32,37,38>

20120314 Change to +EC_VCCA from +3VLP

<32,39>

+3VLP

<32,39>

EC_SMB_DA1

PR221 6.65K_0402_1%

EC_SMB_CK1

EMI@ PC203 0.01U_0402_25V7K

PR975 10K_0402_1%

1 2 3 4 5 6 7 8 9

EMI@ PC201 1000P_0402_50V7K

1 2

1 2 PR209 6.49K_0402_1% 1 2 @ PR206 6.49K_0402_1% 1 2 PR207 10K_0402_5%

EC_SMCA EC_SMDA

CONN@ JBAT2 1 2 3 4 5 6 7 GND GND

VMB PF201 12A_65V_451012MRL 1 2

2 1 PR204 100_0402_1%

1 2 3 4 5 6 7 GND GND

VMB2

2 1 PR201 100_0402_1%

CONN@ JBAT1

SUYIN_200082GR007M229ZR

Issued Date

2011/06/15

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

VILG1/G2 MB LA9902P Schematic

Wednesday, May 08, 2013

Sheet

Rev B

PR301 0.01_1206_1%

CHG_B+

5 AON7408L_DFN8-5 PL302 4.7UH_PCMC063T-4R7MN_5.5A_20%

3 2 1

LX_CHG

PR320 PC317 2.2_0603_5% 0.047U_0603_16V7K 1 2 2 1

BST_CHG

PQ310

PD301 16

SRP

BATT+

SRN

PC305 0.1U_0402_25V6

BQ24737VDD

DL_CHG

PC306 0.1U_0402_25V6 2 1

CHG

PR324 0.01_1206_1%

AON7408L_DFN8-5

2 1 PR318 10_0402_5%

11 6.8_0402_5% 1 12 PR317

RB751V-40_SOD323-2 PC312 1U_0603_25V6K

DH_CHG

PR326 2.2_0402_5%

1U_0603_25V6K

PACIN

PC323 10U_0805_25V6K 2 1

REGN

2 G S

PC322 10U_0805_25V6K 2 1

BTST

EMI@ PR323 4.7_1206_5%

ILIM

PR316 100K_0402_1%

PR319 10_1206_5% 2

SCL

ACP

ACN

CMPIN

CMPOUT

ACOK

HIDRV

124737_SN 2

+3VALW

PHASE PU301 BQ24727RGRR_VQFN20_3P5X3P5

BQ24737VCC

PR315 316K_0402_1% 1 2

SDA

PC314 20

2N7002KW_SOT323-3

EMI@ PC320 680P_0603_50V7K

EC_SMB_CK1

IOUT

3 2 1

EC_SMB_DA1

LODRV

<32,38>

SRN

<32,38>

VCC

GND

PC304 100P_0402_50V8J 8

0.1U_0402_25V6

SRP

PC303 1 2

ACDET

PQ309

PQ313 D

PC324 0.1U_0402_25V6 2 1

ADP_I

2 G 3

BATT_OUT

5 <32,38>

2N7002KW_SOT323-3

<38,39>

PD303 1SS355_SOD323-2

ACPRN

392K_0402_1%

1 PR309 2

PR308 64.9K_0402_1% 1 2

PR328 1 2ACOFF-1 2 10K_0402_5%

PQ314

VIN

ACOFF

PR325 200K_0402_1%

1 0.1U_0402_25V6

0.1U_0402_25V6

<32>

PC308

1 PQ305 DTC115EUA_SC70-3

PR305 150K_0402_1%

2 P2-2 3

PQ307B

PR303 47K_0402_1% 1 2

PACIN

PQ306 2N7002KW_SOT323-3 2 BATT_OUT <38,39> G

L2N7002DW1T1G_SC88-6

ACON

1 2

3 6 PQ307A L2N7002DW1T1G_SC88-6

PR306 20K_0402_1%

PQ311 DTC115EUA_SC70-3

DTC115EUA_SC70-3

PC311

PD302

1DISCHG_G-1 1

PC307

0.1U_0402_25V6

P2-1 PQ303

PR321 47K_0402_1%

VIN

ACP

PR322 200K_0402_1% 1 2 2

ACN

DISCHG_G

PC301 5600P_0402_25V7K

8 7 6 5

2 1

PC302 0.1U_0603_25V7K 2 1 PR304 200K_0402_1%

DTA144EUA_SC70-3

PQ312 AO4407AL_SO8

1 2 3

1 2 EMI@ PL301 1UH_NRS4018T1R0NDGJ_3.2A_30%

2ACOFF-1

EMI@ PC319 2200P_0402_50V7K

PQ304

1 PR302 47K_0402_5%

8 7 6 5

EMI@ PC318 470P_0402_50V8J 1 2

1 2 3

8 7 6 5

PC316 10U_0805_25V6K 1 2

VIN

PQ302 AO4423L_SO8

1SS355_SOD323-2

P2 PQ301 AO4407AL_SO8

B+

PC315 10U_0805_25V6K 1 2

PC309 0.1U_0402_25V6

PR314 10K_0402_1% 1 2

BQ24737VDD

PR310 10K_0402_1%

ACIN

<16,32,37>

PACIN 1

1 2

PR307 47K_0402_1%

PR312

2 2

ACPRN

PQ308

DTC115EUA_SC70-3

12K_0402_1%

Compal Secret Data

Security Classification 2011/06/15

Issued Date

2012/07/11

Deciphered Date

Title

Date:

Compal Electronics, Inc.

CHARGER

Document Number

VILG1/G2 MB LA9902P Schematic

Wednesday, May 08, 2013

Sheet

Rev B 52

PR402 499K_0402_1% 2 1

PL402

LX_3V

+3VLP 2

PC414 4.7U_0603_6.3V6M

+3VALWP

1.5UH_PCMC063T-1R5MN_9A_20%

SY8208BQNC_QFN10_3X3

B+

EMI@ PC413 470P_0805_50V8

LDO

EMI@ PC412 470P_0805_50V8 2 1

3V_FB PR401 PC402 2 1 2 2.2_0603_5% 0.1U_0603_25V7K

PC411 22U_0805_6.3V6M 2 1

OUT

BST_3V 1

PC410 22U_0805_6.3V6M 2 1

GND

PC409 22U_0805_6.3V6M 2 1

LX 9

EN2

PC405 PR409 0.01U_0402_25V4Z 1K_0402_5% 1 2 1 2

PC408 22U_0805_6.3V6M 2 1

EN1

3V5V_EN

680P_0603_50V7K 4.7_1206_5%

PC406 10U_0805_25V6K 2 1

EMI@ PC404 2200P_0402_50V7K 2 1

PU401

EMI@ PC415 EMI@ PR404 2 13V_SN 2

3V_VIN

PL401 HCB1608KF-121T30_0603 1 2

PR403 150K_0402_1% 2 1

ENLDO_3V5V

B+ EMI@

@EMI@ PC403 0.1U_0402_25V6 2 1

+5VALWP

+3VALWP

@ PJ401 1

+3VALW

JUMP_43X118

EMI@ PC419 470P_0805_50V8

LDO

SY8208CQNC_QFN10_3X3

PL404

1.5UH_PCMC063T-1R5MN_9A_20%

EMI@ PC416 470P_0805_50V8 2 1

LX_5V

PC426 22U_0805_6.3V6M 2 1

OUT

PC421 0.1U_0603_25V7K 1 2

PC425 22U_0805_6.3V6M 2 1

VCC

PR405 2 2.2_0603_5%

PC424 22U_0805_6.3V6M 2 1

GND

BST_5V

2 PC422 4.7U_0603_6.3V6M

3 6

PC407 PR410 6800P_0402_25V7K 1K_0402_5% 1 2 1 2

5V_FB

9 5V_VCC

3V5V_EN

PC423 22U_0805_6.3V6M 2 1

EN1

PC430 4.7U_0603_6.3V6M

@EMI@ PC418 0.1U_0402_25V6 2 1

EMI@ PC417 2200P_0402_50V7K 2 1

PC427 4.7U_0805_25V6-K 2 1

PC420 4.7U_0805_25V6-K 2 1

EN2

+5VALWP

@ PJ402 1

+5VALW

JUMP_43X118

PR407 2.2K_0402_5% 2 1

<32> EC_ON <32> MAINPWON

PU402

EMI@ PC429 EMI@ PR406 2 15V_SN 2

5V_VIN

PL403 HCB2012KF-121T50_0805 1 2

680P_0603_50V7K 4.7_1206_5%

B+ EMI@

PR408

0_0402_5%

PC431 @ 4.7U_0402_6.3V6M

2 1 @ PR411 1M_0402_5%

3V5V_EN

Compal Secret Data

Security Classification 2011/06/15

Issued Date

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

VILG1/G2 MB LA9902P Schematic

Wednesday, May 08, 2013

Sheet

Rev B

1 2

@EMI@ PC509 0.1U_0402_25V6

1 2

Vo=1.518V

+1.5VP

1 17

16 PHASE

BOOT

UGATE

VTTREF

CS VDDP

PGOOD 10

TON 9

S3 7

PR502 49.9K_0402_5% 1 2

VDD

S5_1.5V

S3_1.5V

PC506 0.033U_0402_16V7K

VDDQ FB

PGND

RT8207MZQW_WQFN20_3X3

LG_1.5V

PR511 6.65K_0402_1% 2 1

13 12

@EMI@ PR515 4.7_1206_5% 1

2 330U_2.5V_M

+ PC521 @EMI@ PC517 680P_0603_50V7K

Rds( on) =2. 7m- 3. 3m ohm

1 PR514 5.1_0603_5%

+3VALW

+5VALW 2

PC511 1U_0603_10V6K

PGOOD_1.5V

PR509 887K_0402_1% 2 1 1.5V_B+

PR507 5.9K_0402_1% 2 1

FB=Vref=0.75V

@ PC508 0.1U_0402_16V7K

0_0402_5%

PL501 1UH_PCMB104T-1R0MH_18A_20% 2 1

5 GND

@ PR505 1

LGATE

VTTSNS

VLDOIN

VTTGND

+1.5VP

PAD

+VTT_REFP

VTT

PC505 10U_0805_25V6K

PC504 10U_0805_25V6K

PU501 21

PC503 0.1U_0402_16V6K

PC520 4.7U_0805_25V6-K

1 1 2

PR501 PC512 2.2_0603_5% 0.1U_0603_25V7K 1 2 BST_1.5V-11 2

BST_1.5V

<32> SYSON

LX_1.5V

@ PR503 0_0603_5%

Note: S3 - sleep ; S5 - power off

<32,36,41,43> SUSP#

PQ501 MDV1525URH_PDFN33-8-5

+0.75VSP

PC501 10U_0805_25V6K

Off

UG_1.5V

Off

+1.5VP

On Off (Hi-Z)

PQ502 MDU1511RH_POWERDFN56-8-5

B+

3 2 1

0.75VSP

3 2 1

VTT_REFP

S4/S5

1.5VP

EMI@ PL502 1 2 HCB2012KF-121T50_0805

1.5V_B+

PC510 1U_0603_10V6K 2 1

2 1 PR510 10K_0402_5%

STATE

EMI@ PC513 2200P_0402_50V7K

+1.5VP Ipeak=14A ; Imax=9.8A Delta I=4.8476A=>1/2Delta I=2.4238A Rton= 887K ohm,F= 285K Hz Rds(on)=3.3m ohm(max) ; Rds(on)=2.7m ohm(typical) PR511=6.65K ohm Ilimit_min=(6.65K*10uA)/(10*3.3m*1.2)=16.793A Ilimit_max=(6.65K*10uA)/(10*2.7m*1.2)=20.525A Iocp=Ilimit+1/2Delta I=19.217 ~ 22.948A

PR506 5.76K_0402_1%

JUMP_43X118 PJ505

@ 1

+1.5VP

PJ504

+1.5V

JUMP_43X118

@ +0.75VSP

PJ506 1

+0.75VS

JUMP_43X39

1M_0402_5% PR504

PC515 22U_0805_6.3VAM

1 2

PC514 22U_0805_6.3VAM

1 2

PC525 68P_0402_50V8J 2 1

Vo=1.8V +1.8VSP

@ 1

+1.8VSP

PJ507 1

+1.8VS

JUMP_43X79

1.8VSP_FB 1

0_0402_5%

PR512 20K_0402_1% 2

EN_1.8VSP

FB=0.6Volt

1 2

@ PR516 1

PL503 1UH_PH041H-1R0MS_3.8A_20% 1 2

SVIN

PC507 @ 0.1U_0402_10V7K

<32,36,41,43> SUSP#

PVIN

1.8VSP_LX

@EMI@ PC523 @EMI@ PR508 680P_0603_50V7K 4.7_0603_5%

PC502 22U_0805_6.3VAM

JUMP_43X79

PVIN

1.8VSP_VIN

+3VALW

PU502 SY8033BDBC_DFN10_3X3 PJ502

PR513 10K_0402_1% 4

Compal Secret Data

Security Classification Issued Date

2011/06/15

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

Date:

VILG1/G2 MB LA9902P Schematic

Wednesday, May 08, 2013 D

Sheet

Rev B 52

VID [0] 0 0 1 1

VID[1] 0 1 0 1

VCCSA Vout 0.9V 0.8V 0.725V 0.675V

VOUT

VID1

VID0

SA_PGOOD

CR@ PR601 100K_0402_5% 1 2

4 5

1 2 NONCR@ PR608 0_0402_5%

+VCCSA_EN

+3VS

@EMI@ PR602 4.7_0603_5%

<43>

@EMI@ PC605 680P_0402_50V7K

+VCCSAP

@CR@ PC606 .1U_0402_16V7K

H_VCCSA_VID0 FB_VCCSA

<32>

+V1.05S_VCCP_PWRGOOD

SVIN

CR@ PC604 22U_0805_6.3V6M 1 2

CR@ PC603 22U_0805_6.3V6M 1 2

10 CR@ PC602 68P_0402_50V8J 2 1 FB_VCCSA_IC9

PVIN

CR@ PL601 0.47UH_FDVE0630-H-R47M=P3_17.7A_20% 1 2 1

CR@ PU601 SY8037BDCC_DFN12_3X3 12 1 +VCCSA_PHASE PVIN LX

+VCCSA_PWR_SRC

JUMP_43X79

+VCCSA

GND

PJ601

PJ602

JUMP_43X118

CR@ PC601 22U_0805_6.3V6M 1 2

@CR@ 1 1

@CR@ 2 2

+VCCSAP

output voltage adjustable network

+3VALW

NONCR@ PR603 0.001_1206_1% 1 2

+V1.05S_VCCP

PR604 1K_0402_5% 2 1

<10>

The 1k PD on the VCCSA VIDs are empty. These should be stuffed to ensure that VCCSA VID is 00 prior to VCCIO stability.

PR605 1K_0402_5% 2 1

H_VCCSA_VID1

CR@ PR606 100_0402_1% 2 1

<10>

@ PR607 1

+VCCSA_SENSE

<10>

0_0402_5%

Compal Secret Data

Security Classification Issued Date

2011/06/15

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

Document Number

Rev B

VILG1/G2 MB LA9902P Schematic Wednesday, May 08, 2013

Sheet 1

+1.05VS_VCCPP Ipeak=15.2A ; Imax=10.64A Delta I=2.48=>1/2Delta I=1.24A (F=400K Hz) D-CAP 2 Rds(on)=3.3m ohm(max) ; Rds(on)=2.7m ohm(typical) PR711=47K ohm Vtrip=(Rtrip*10uA)/8= 58.75mV Iocp=19.043~22.999A

DH_1.05VS_VCCP

GSNS

DL_1.05VS_VCCP

10_0402_1%

PC704 1000P_0402_50V7K

PC708 1U_0603_10V6K

1 2

3 2 1

TRIP

0.01UF_0402_25V7K

+5VALW

PR703

PC706

VCCIO_SENSE

VSSIO_SENSE_L

PGND

V5 GND

VSNS COMP

PQ702 S TR MDU1511RH 1N POWERDFN56-8

TPS51219RTER_QFN16_3X3

1 +V1.05S_VCCP

JUMP_43X118

@EMI@ PC715 0.1U_0402_25V6 2 1

PC712 10U_0805_25V6K 2 1

B+

PL701 1UH_PCMB104T-1R0MH_18A_20% 2 1

LX_1.05VS_VCCP

PC703 0.01UF_0402_25V7K

EMI@ PC711 2200P_0402_50V7K 2 1

REFIN

EMI@ PL702 HCB2012KF-121T50_0805 2 1

MDV1525URH_PDFN33-8-5

JUMP_43X118 PJ703 2 1 2 1

PQ701

PJ701

+1.05VS_VCCPP

@EMI@ PC709 @EMI@ PR714 1000P_0603_50V7K 4.7_1206_5%

BST

15 MODE

VREF

PC707 0.1U_0603_25V7K 1 2

PR711 47K_0402_1% 2 1

<9>

PGOOD

PAD 2

2 1

12K_0402_1%

0_0402_5%

<9>

10.7K_0402_1%~N PR704 2

PU701

PR713 2.2_0603_5% 1 2 BST_1.05VS_VCCP

@ PR702 1

PR705 2

PC702 0.1U_0402_25V6 2 1

1.05VS_B+

+V1.05S_VCCP_PWRGOOD

3 2 1

PR712 2

1 <42>

100K_0402_1%

+3VS PR710 100K_0402_1% 2

2 PR706

PR701 60.4K_0402_1% 1 2

<32,36,41> SUSP#

PC701 .1U_0402_16V7K

@ 10K_0402_1%

+1.05VS_VCCPP

PC714

1 +

330U_2.5V_M

+1.05VP OCP min 20A OVP min 1.24V

Rds( on) =2. 7m- 3. 3m ohm B

PR709

1 2 1

2 10_0402_1%

PC705 1000P_0402_50V7K

Compal Secret Data

Security Classification 2011/06/15

Issued Date

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

Date:

VILG1/G2 MB LA9902P Schematic Wednesday, May 08, 2013

Sheet

Rev B

PC902 2

.1U_0402_16V7K 1 PR904 2

2P: 24K 1P: 24.9K

24.9K_0402_1%

PR915,PR946=200K(setting 113 degreeC) PR915,PR946=8.25K(setting 93 degreeC)

1K_0402_1%

3P: 806 2P: 1K

1 2

2 1

PR905 1 2 75K_0402_1%

6132P_VCCP

BST1

PC920 1 2 2.2U_0603_10V7K

LG2

<45> 1 PR930 2 0_0402_5%

LG1

<45>

HG1

<45> 1 PR9312 BST1_1 1 2.2_0603_5%

+5VS PC922 2 0.22U_0603_25V7K

PUT COLSE TO V_GT HOT SPOT

+5VS

SW2

<45>

Option for 1 phase GFX

2Phase: @ 1Phase: install

SW1A

0_0402_5% @ PR928

SW1

CSP2A

<45>

DROOP

PC937 1 2

CSREF

1000P_0402_50V7K

PUT COLSE TO VCORE Phase 1 Inductor

<45>

PC931

3P: 1500p0.047U_0402_16V7K CSREF 2P: 1200p

@ PR960 6.98K_0402_1%

PR9452 6.98K_0402_1%

SWN2

<45>

SWN1

<45>

@ PR917 0_0402_5%

@ PR961 6.98K_0402_1%

1 PR952 2NTC_PH201 1 PR953 2 75K_0402_1% 165K_0402_1% PH903

SWN1

PR9512 124K_0603_1%

SWN2

2 PH902 100K_0402_1%_TSM0B104F4251RZ

PR9492 124K_0603_1%

2 PC936 820P_0402_25V7

PR946 1

CSSUM PC934 2 1000P_0402_50V7K

PR949.PR951 need link SD014124380. PUT COLSE TO VCORE HOT SPOT

1 220K_0402_5%_ERTJ0EV224J

IMVP_IMON

Compal Secret Data

Security Classification Issued Date

2011/06/15

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

Date:

TSENSE

PR9412 6.98K_0402_1%

CSREF

3Phase: @ 2Phase: install

TSENSE

CSP3

CSP2 PC927 0.047U_0402_16V7K

PC932 1000P_0402_50V7K

0_0402_5% @ PR935

PC924 2 .1U_0402_16V7K

CSP1

Option for 2 phase CPU

3P: 73.2K 2P: 41.2K

3P: 21K 2P: 12.4K

3P: 2200p 2P: 3300p

3P: 3.65K 2P: 9.53K

PR9342 41.2K_0402_1%

200K_0402_1%

806_0402_1%

6132_PWM

CSP1 CSP2 CSP3

CSCOMP

3P: 6.04K 2P: 4.32K

24.9K_0402_1%

PR948

<32>

100K_0402_1%_TSM0B104F4251RZ

1 6132_PWMA

HG2

PC919 2 0.22U_0603_25V7K

<45> 1 PR9242 BST2_1 1 2.2_0603_5% <45>

10P_0402_50V8J

3P: 23.7K 2P: 24.9K 1

LG1A

BST2

PR921 PC918 1 2 BSTA1_11 2 2.2_0603_5% 0.22U_0603_25V7K <45>

PC926 2 1

PR950 1

1 2

1 0.033U_0402_16V7K

PC933

3P: 348 2P: 1.21K

CSCOMP

HG1A

1 PR940 2 1K_0402_1%

PC930 1 2FB_CPU3 1 2 10_0402_1% 0.033U_0402_16V7K PR947 1 2 FB_CPU2

PR955 2

BSTA1

PH904

+5VS

PR942 PC928 PR943 PC929 1 2FB_CPU1 1 2 2 1COMP_CPU12 1 49.9_0402_1% 4.32K_0402_1% 1000P_0402_50V7K 3300P_0402_50V7K

8.06K_0402_1%

45 44 43 42 41 40 39 38 37 36 35 34 33 32 31

2P: 36K 1P: 26.1K

PR918 1 2 26.1K_0402_1%

0_0402_5%

3P: 330p 2P: 1000p

TRBST#

<45>

PC923 1000P_0402_50V7K VSP

3P: 22p 2P: 10p

PR944

<45>

VCCSENSE

VSN

TRBST# FB_CPU COMP_CPU

0_0402_5% @ PR938 1

@ PR936 1

VGATE

SWN1A

.1U_0402_16V7K

<9>

VGATE

VSSSENSE

@ PR916 0_0402_5%

PC914 2

VCC PWMA VDDBP BSTA VRDYA HGA EN SWA SDIO LGA ALERT# BST2 SCLK HG2 VBOOT NCP6132AMNR2G_QFN60_7X7 SW2 ROSC LG2 VRMP PVCC VRHOT# PGND VRDY LG1 VSN SW1 VSP HG1 DIFF BST1

<16,32> <9>

6.98K_0402_1% 2

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

PR933 10K_0402_5%

PAD VSNA VSPA DIFFA TRBSTA# FBA COMPA IOUTA ILIMA DROOPA CSCOMPA CSSUMA CSREFA CSP2A CSP1A TSNSA

2.2U_0603_10V7K

0.01U_0402_25V7K

1 2

.1U_0402_16V7K

PR923 1 2 54.9_0402_1%

PR922 2

130_0402_1%

6132_VCC

TSENSEA

@ CSREFA

PU901

1 2 3 4 VR_ON_CPU <32> VR_ON PC917 VR_SVID_DAT1 5 VR_SVID_ALRT# 6 7 PR927 PR925 VR_SVID_CLK 1 2 VBOOT 8 95.3K_0402_1% 0_0402_5% 1@ PR926 2VR_SVID_DAT1 1 2 9 10K_0402_1% ROSC_CPU 1 2 10 VRMP CPU_B+ H_PROCHOT# 11 <32,37,6> H_PROCHOT# 12 PR929 1K_0402_1% VGATE 13 14 PC921 +3VS 15 DIFF_CPU

<9> VR_SVID_DAT <9> VR_SVID_ALRT# <9> VR_SVID_CLK

CSP1A

PR913 1

PC911 1000P_0402_50V7K

TRBST# FB COMP IOUT ILIM DROOP CSCOMP CSSUM CSREF CSP3 CSP2 CSP1 TSNS DRVEN PWM

1 PR9192 2_0603_5% PC915 1 2

+5VS

SWN1A

63.4K_0603_1%

61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46

PR927=95.3K ohm,F=300Khz PR927=63.4K ohm,F=450Khz

2P: 1.65K 1P: 1K PC910 0.047U_0402_16V7K

CSREFA

1000P_0402_50V7K

+V1.05S_VCCP

PC906 1 2

DROOPA

PR915 2

DIFFA TRBSTA# FBA COMPA

0_0402_5%

PR9122

PR906 2

1K_0402_1%

200K_0402_1%

PC912 1000P_0402_50V7K

CSCOMPA

220K_0402_5%_ERTJ0EV224J

2 PR9071 NTC_PH203 165K_0402_1%

0_0402_5% @ PR954 1

PUT COLSE TO GT Inductor

PH901

CSREFA

VSS_AXG_SENSE

<10>

@ PR937 1

2P: 21.5K 1P: 15.8K

VCC_AXG_SENSE

PR910 10P_0402_50V8JPC909 2 COMPA11 2

6.04K_0402_1% 2200P_0402_50V7K

1K_0402_1%

<10>

15.8K_0402_1%

680P_0402_50V7K

PR9092

FBA2

PC908 1 2

1PR914

1 2 10_0402_1%

0.033U_0402_16V7K

PC907 1 2

ILIMA DROOPA

PR908

PC904 1 2

10.7K_0402_1%

PC905

680P_0402_50V7K

PC903 1 2

ILIM_CPU DROOP

1.21K_0402_1%

PR903

CSCOMPA

FBA1

CSSUMA

PR9022

GPU_IMON

CSP2A CSP1A TSENSEA

<32>

TRBSTA#

0.033U_0402_16V7K

.1U_0402_16V7K

FBA3

IMVP_IMON 1 2 PR939 12.4K_0402_1%

PR9012

10_0402_1%

PC935 1 2

1 D

1200P_0402_50V7K

PC901

VILG1/G2 MB LA9902P Schematic

Wednesday, May 08, 2013

Sheet 1

Rev B

V1N_CPU

PR958

SW2 EMI@ PR957 4.7_1206_5%

CSREF

<44>

LG2

10_0402_1% SWN1

EMI@ PC948

PC943 10U_0805_25V6K 2 1

EMI@ PC944 0.1U_0402_25V6 2 1

EMI@ PC945 2200P_0402_25V7K 2 1

+VCC_CORE

PL903 0.36UH_PCMB104T-R36MH1R105_30A_20%

1 2

PC942 10U_0805_25V6K 2 1

5 3 2 1 <44>

PQ904

<44>

S TR MDU1511RH 1N POWERDFN56-8

680P_0603_50V7K

Rds( on) =2. 7m- 3. 3m ohm

DCR: 1.10m ±5% ohm

V2N_CPU 2 PR959 1 10_0402_1%

CSREF

SWN2

<44>

EMI@ PC949 680P_0603_50V7K

Rds( on) =2. 7m- 3. 3m ohm

PQ902 S TR MDU1516URH 1N POWERDFN56-8

S TR MDU1511RH 1N POWERDFN56-8

3 2 1

PQ903

PC969 68U_25V_M

DCR: 1.10m ±5% ohm

PR963 1 2 2.2_0402_5%

HG2

SNUB_CPU2

<44>

3 2 1

LG1

1SNUB_CPU1

<44>

CPU_B+

EMI@ PR956 4.7_1206_5%

@EMI@ PC972 470P_0402_50V8J

SW1 5

+VCC_CORE

PL902 0.36UH_PCMB104T-R36MH1R105_30A_20%

S TR MDU1516URH 1N POWERDFN56-8

<44>

@EMI@ PC971 470P_0402_50V8J

EMI@ PL901 HCB4532KF-800T90_1812 1 2 PC970 68U_25V_M

PQ901

CPU_B+ B+

EMI@ PC941 2200P_0402_25V7K 2 1

EMI@ PC940 0.1U_0402_25V6 2 1

PR962 1 2 2.2_0402_5%

HG1

3 2 1

<44>

PC939 10U_0805_25V6K 2 1

PC938 10U_0805_25V6K 2 1

CPU_B+

DC 35W CPU VID1=1.05V IccMax=53A Icc_Dyn=43A Icc_TDC=36A R_LL=1.9m ohm OCP~65A

QC 45W CPU VID1=0.9V IccMax=94A Icc_Dyn=66A Icc_TDC=52A R_LL=1.9m ohm OCP~110A

PR964 1 2 2.2_0402_5%

EMI@ PC947 2200P_0402_25V7K 2 1

EMI@ PC946 0.1U_0402_25V6 2 1

SW1A

EMI@ PR967 4.7_1206_5%

Rds( on) =2. 7m- 3. 3m ohm

+VCC_GFXCORE_AXG

DCR: 1.10m ±5% ohm

2 EMI@ PC968

PR971 1

CSREFA

<44>

10_0402_1%

680P_0603_50V7K

SWN1A

S TR MDU1511RH 1N POWERDFN56-8

3 2 1

PQ909

1SNUB_GFX1

LG1A

PL905 0.36UH_PCMB104T-R36MH1R105_30A_20%

V1N_GFX

PQ907 S TR MDU1516URH 1N POWERDFN56-8

5 <44>

<44>

PC958 10U_0805_25V6K 2 1

5 HG1A

3 2 1

<44>

PC957 10U_0805_25V6K 2 1

CPU_B+

<44>

QC 45W GT2 VID1=1.23V IccMax=46A Icc_Dyn=37A Icc_TDC=38A R_LL=3.9m ohm OCP~55A

DC 35W GT2 VID1=1.23V IccMax=33A Icc_Dyn=20.2A Icc_TDC=21.5A R_LL=3.9m ohm OCP~40A

Compal Secret Data

Security Classification Issued Date

2011/06/15

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

Document Number

Rev B

VILG1/G2 MB LA9902P Schematic

Wednesday, May 08, 2013

Sheet 1

+VCC_CORE

10U_0805_6.3VAM

1 PC2 10U_0805_6.3VAM

1 PC3 10U_0805_6.3VAM

1 PC4 10U_0805_6.3VAM

PC5 10U_0805_6.3VAM

@EMI@ PC11 470P_0402_50V8J

+VCC_GFXCORE_AXG

1 PC10 10U_0805_6.3VAM

+VCC_CORE

PC64 22U_0805_6.3V6M

PC58 ESR= 4. 5m ohm PC59 ESR= 9m ohm

ESR= 9m ohm

1 +

PC67 330U_D2_2V_Y

PC66 330U_D2_2V_Y

PC56 22U_0805_6.3V6M

1 PC63 22U_0805_6.3V6M

PC33 22U_0805_6.3V6M

1 PC62 22U_0805_6.3V6M

PC53 22U_0805_6.3V6M

2 1

PC32 22U_0805_6.3V6M

PC61 22U_0805_6.3V6M

2 1 +

PC52 22U_0805_6.3V6M

PC48 22U_0805_6.3V6M

PC31 22U_0805_6.3V6M

PC51 22U_0805_6.3V6M

PC47 22U_0805_6.3V6M

PC30 22U_0805_6.3V6M

PC50 22U_0805_6.3V6M

PC46 22U_0805_6.3V6M

PC29 22U_0805_6.3V6M

+V1.05S_VCCP PC28 22U_0805_6.3V6M

PC45 22U_0805_6.3V6M

+V1.05S_VCCP

PC43 22U_0805_6.3V6M

7 x 22 µF (0805) 2 x (0805) no-stuff sites

PC59 390U_2.5V_M

PC44 22U_0805_6.3V6M

PC58 470U_D2_2VM_R4.5M

PC42 22U_0805_6.3V6M

PC41 22U_0805_6.3V6M

Socket Top

1 PC24 22U_0805_6.3V6M

PC40 22U_0805_6.3V6M

1 PC23 22U_0805_6.3V6M

PC39 22U_0805_6.3V6M

1 PC22 22U_0805_6.3V6M

PC38 22U_0805_6.3V6M

1 PC21 22U_0805_6.3V6M

PC36 22U_0805_6.3V6M

1 PC20 22U_0805_6.3V6M

5 x 22 µF (0805) 5 x (0805) no-stuff sites

PC27 22U_0805_6.3V6M

Socket Bottom

PC19 22U_0805_6.3V6M

1 PC9 10U_0805_6.3VAM

PC18 22U_0805_6.3V6M

1 PC8 10U_0805_6.3VAM

PC17 22U_0805_6.3V6M

1 PC7 10U_0805_6.3VAM

PC15 22U_0805_6.3V6M

1 PC6 10U_0805_6.3VAM

PC13 22U_0805_6.3V6M

Below is 458544_CRV_PDDG_0.5 Table 5-8.

+VCC_GFXCORE_AXG

PC1

1 PC71 22U_0805_6.3V6M

PC72 22U_0805_6.3V6M

1 +

PC76 330U_D2_2V_Y

PC74 330U_D2_2V_Y

PC78 330U_D2_2V_Y

PC77 330U_D2_2V_Y

PC73 330U_D2_2V_Y

+VCC_CORE

ESR= 9m ohm

Compal Secret Data

Security Classification 2011/06/15

Issued Date

Deciphered Date

2012/07/11

Title

Date:

Compal Electronics, Inc. SCHEMATIC M/B LA-9902 Document Number

Rev B

4019N1

Wednesday, May 08, 2013

Sheet 1

Version c hange list (P. I . R. List) I tem

Reason f or change

PG#

Page 1 of 2 f or PW R

Modif y List

Date

Phase

Design Change of

IC Package.

Change PU401 to SA000061M00(S IC SY8208BQNC QFN 10P PWM)

2012/11/22

DVT

Design Change of

IC Package.

Change PU402 to SA000061N00(S IC SY8208CQNC QFN 10P PWM)

2012/11/22

DVT

Add ADP_ID Circuit.

Add PQ102 to SB00000EO10(S TR 2N7002KDW 2N SOT-363-6 PANJIT) Add PR111.PR112 to SD028100380(S RES 1/16W 100K +-5% 0402)

2012/12/03

DVT

Factory lack of material.

Change PC521 to SF000003H00(S_A-P_CAP 330U 2.5V M 6.3X4.2 LESR16M SL)

2012/12/06

DVT

Factory lack of material.

Change PL902.PL903.PL905 to SH00000N900(S COIL .36U PCMB104T-R36MH1R105 30A GLUE)

2012/12/06

DVT

EMI request adjust +3VALWP/+5VALWP snubber function.

Change @PR404.@PC415.@PR406.@PC429 to PR404.PC415.PR406.PC429.

2012/12/06

DVT

EMI request adjust +3VALWP/+5VALWP boost resistor.

Change PR401.PR405 to SD013220B80(S RES 1/10W 2.2 +-5% 0603).

2012/12/06

DVT

EMI request add bypass capacitor.

Add PC412.PC413.PC416.PC419 to SE001471J80(S CER CAP 470P 50V J NPO 0805 H0.6)

2012/12/06

DVT

EMI request adjust CPU/GFX CORE snubber function.

Change @PR956.@PC948.@PR957.@PC949.@PR967.@PC968 to PR956.PC948.PR957.PC949.PR967.PC968.

2012/12/06

DVT

EMI request adjust bypass capacitor.

Change @PC940 to PC940.

2012/12/06

DVT

EMI request add bypass capacitor.

Add PC944.PC946 to SE00000G880(S CER CAP 0.1U 25V K X5R 0402) Add PC945.PC947 to SE075222K80(S CER CAP 2200P 25V K X7R 0402)

2012/12/06

DVT

Design Change of input capacitor.

Change PC420 to SE00000OF80(S CER CAP 4.7U 25V K X6S 0805 H1.25) Add PC427 to SE00000OF80(S CER CAP 4.7U 25V K X6S 0805 H1.25)

2012/12/07

DVT

Design Change of IC Application.

Add Add Add Add

2012/12/10

DVT

2012/12/17

DVT

@PR409.@PR410 to SD028100180(S RES 1/16W 1K +-5% 0402) @PC405 to SE075472K80(S CER CAP 4700P 25V K X7R 0402) @PC407 to SE075472K80(S CER CAP 0.047U 25V K X7R 0402) PR411 to SD028000080(S RES 1/16W 0 +-5% 0402)

Design Change of IC Application.

Change Change Change Change Change Change

Design Change of CPU/GFX CORE Choke.

Change PL902.PL903.PL905 to SH00000NM00(S COIL 0.22UH +-20% PCMB104T-R22MS 35A)

2012/12/21

DVT

Design Change of VCCSA(LDO).

Delete PC607.PC608.PC609.PC610.PC611.PC612.PC613.PC614.PJ603.PJ604.PR608.PR609.PR610.PR611.PU602

2012/12/21

DVT

Reduction Part Count.

Delete PR110.

2013/01/18

PVT

Reduction Part Count.

Delete PR603.

2013/01/18

PVT

Reduction Part Count.

Delete PC916.

2013/01/18

PVT

Design Change of IC Application.

Change @PC405.@PR490.@PC407.@PR410 to PC405.PR490.PC407.PR410. Change PR411 to SD028000080(S RES 1/16W 0 +-5% 0402)

2013/01/18

PVT

PC936 to SE000008980(S CER CAP 820P 25V K X7R 0402) PC929 to SE074332K80(S CER CAP 3300P 50V K X7R 0402) PC926 to SE071100J80(S CER CAP 10P 50V J NPO 0402) PC928 to SE074102K80(S CER CAP 1000P 50V K X7R 0402) PR943 to SD00000J280(S RES 1/16W 4.32K +-1% 0402) PR949.PR951 to SD014124380(S RES 1/10W 124K +-1% 0603 YAGEO)

2011/06/15

Issued Date

Compal Secret Data

Security Classification

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc.

Date:

SCHEMATIC M/B LA-9902

VILG1/G2 MB LA9902P Schematic

Wednesday, May 08, 2013

Sheet

Rev B

Version c hange list (P. I . R. List) I tem

Reason f or change

PG#

Page 2 of 2 f or PW R

Modif y List

Date

Phase

Reduction Part Count.

Change PR505.PR516 to SD028000080(S RES 1/16W 0 +-5% 0402) Change PR503 to SD013000080(S RES 1/10W 0 +-5% 0603)

2013/01/18

PVT

Design Change of Thermal Application.

Change PC521 to SGA20331E10(S POLY C 330U 2V Y D2 LESR9M EEFSX H1.9)

2013/01/18

PVT

Reduction Part Count.

Change PR702 to SD028000080(S RES 1/16W 0 +-5% 0402)

2013/01/18

PVT

Reduction Part Count.

Change PR926.PR916.PR917 to SD028000080(S RES 1/16W 0 +-5% 0402)

2013/01/18

PVT

Design Change of CPU/GFX CORE Choke.

Change PL902.PL903.PL905 to SH00000N900(S COIL .36U PCMB104T-R36MH1R105 30A GLUE)

2013/01/18

PVT

Design Change of CPU/GFX CORE Frequence.

Change PR927 to SD034953280(S RES 1/16W 95.3K +-1% 0402)

2013/01/18

PVT

Factory lack of material.

Change PC420.PC427 to SE000006R80(S CER CAP 4.7U 25V K X5R 0805 H1.25)

2013/01/18

PVT

Reduction Part Count.

Delete PR411.

2013/01/21

PVT

Design Change of Power Circuit Application.

Change PC208 to SE000003J80(S CER CAP 0.068U 16V K X7R 0402)

2013/01/23

PVT

Design Change of Power Circuit Application.

Add PR328 to SD028100280(S RES 1/16W 0 +-5% 0402) Add PQ314 to SB000009Q80(S TR 2N7002KW 1N SOT323-3)

2013/01/23

PVT

Design Change of Power Circuit Application.

Change PC405 to SE072103Z80(S CER CAP .01U 25V Z Y5V 0402) Change PC407 to SE075682K80(S CER CAP 6800P 25V K X7R 0402)

2013/03/04

PVT

Design Change of Power Circuit Application.

Add PR608 to SD028000080(S RES 1/16W 0 +-5% 0402)

2013/03/14

Pre-MP

Compal Secret Data

Security Classification 2011/06/15

Issued Date

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc.

Date:

SCHEMATIC M/B LA-9902

VILG1/G2 MB LA9902P Schematic

Wednesday, May 08, 2013

Sheet

Rev B

COMPAL CONFIDENTIAL D

MODEL NAME: PCB NAME: REVISION: DATE: AC MODE

Power Sequence Block Diagram LA-9901P 0.2 2013/01/14

6 +3V_PCH

PCH_PWROK 14

VIN PU301

BATT MODE

JUMP

BATT+ 3

B1 4

SW3

B+ 2

7 EC_RSMRST#

PU401 +3VALW 6 PU402 +5VALW

SYS_PWROK 19

8 PBTN_OUT#

EC_ON 5 ACIN ON/OFF

GC6_FB_CLAMP_TGL_REQ#

DGPU_PWROK

PM_SLP_S3# PM_SLP_S4# PM_SLP_S5# 9

PCH

15 PM_DRAM_PWRGD 16 H_CPUPWRGD

11 SUSP#

SYSON 10

-->UMA 11 11

10 -->DIS

B+

+5VALW

SUSP +3VALW

SUSP#

+1.5V

SUSP

+1.5V

SUSP# B+

PU502

+1.8VSP

U39

JUMP

QV5

+1.5V

+3VALW

+VCCSA_EN

PU601

B+ 16

JUMP

+1.05VS_VGA

PLT_RST_VGA#

VGA

21 JUMP

UV2

QV11

VRAM

20 PLT_RST# DGPU_HOLD_RST#

+1.05VS_VCCP

GC6_EN

PU602

+3VS_VGA 13

PCH

DV2

DGPU_PWR_EN

+1.05VS_VCCP_PWRGD

+1.5VS_VGA

+1.5V_CPU_VDDQ JUMP

UV11

+1.8VS

+1.5VS

+VGA_CORE 15 16

FBVDDQ_PWR_EN

+5VS_DISPLAY

+3VS +3VS_WLAN 12

PU701

JUMP

+5VS U73

U38

+1.5V +0.75VS

PU801

+1.05VS_VCCP

SUSP

PU501

JUMP

NVDD_PWR_EN B+ EC_VGA_EN

+VCC_CORE +VCC_GFXCORE_AXG

DGPU_PWROK

SUSP#

+3VALW

+1.5VP +0.75VSP

SW1A

NVDD_PWR_EN

SYSON

PU901

SVID

DGPU_PWROK

DGPU_PWR_EN SYS_PWROK VGATE 18 SVID B+ SW1,SW2

VR_ON 13

CPU

20 PLT_RST#

GC6_FB_CLAMP

12 SA_PGOOD

+VCCSA

SA_PGOOD

GC6_FB_CLAMP

GC6_FB_CLAMP_TGL_REQ# Compal Secret Data

Security Classification Issued Date

2011/06/15

2012/07/11

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC M/B LA-9902 Rev B

4019N1

Date:

Wednesday, May 08, 2013

Sheet 1

VILG1/G2 HW PIR List Page

MODI FI CATI ON LI ST

PURPOSE

P. 5~11

Change f oot pr i nt of J CPU1

For Lenovo r ul e

P. 14

Add R406, R407, R408, R409

Reser ve f or i mpr ovement f act or y pr ocesses

P. 42

Add EC_SPI _SO, EC_SPI _SI , EC_SPI _CLK, EC_SPI _CS# t o EC

Reser ve f or i mpr ovement f act or y pr ocesses

P. 42

Add PCH_PWR_EN t o EC Pi n. 107

Reser ve f or i mpr ovement f act or y pr ocesses

P. 42

Reser ve R410

Reser ve Pul l - hi gh f or GPI O use

P. 42

Change EC_FAN_PWM f r om EC Pi n. 34 t o EC Pi n. 26

For common desi gn

P. 42

Change NOVO# f r om EC Pi n. 26 t o EC Pi n. 34

For common desi gn

P. 42

Change ENBKL f r om EC Pi n. 73 t o EC Pi n. 76

For common desi gn

P. 42

Change I MVP_I MON f r om EC Pi n. 76 t o EC Pi n. 73

For common desi gn

P. 42

Change DGPU_PWR_EN f r om EC Pi n. 107 t o EC Pi n. 123

For common desi gn

P. 34

Add R411, R412, C411, C412

Reser ve f or EMI

P. 20

Add Q21, R40, C237, Q22, R418, C243, C252, R413

Reser ve f or power consumpt i on

P. 25

Del Q12/ R806

For Change Audi o J ack t ype f r om Nor mal cl ose t o Nor mal open

I t em

EVT TO DVT D

Compal Secret Data

Security Classification Issued Date

2011/06/15

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

4019N1

Wednesday, May 08, 2013

Sheet 1

Rev B 52

VILG1/G2 HW PIR List D

I t em

Page

MODI FI CATI ON LI ST

PURPOSE

P. 26

Reser ve R508

For l eakage cur r ent i ssue of At her os WLAN

P. 31

Change RA22 t o r eser ve

For PC Beep i ssue( can' t hear d sound of " di " on BI OS set up menu)

P. 31

Reser ve RA10/ RA11

For sol ve Codec speaker Hum noi se i ssue( Zi zi )

P. 32

Reser ve R416

Reser ve +3VLP power r ai l t o EC

P. 32

Change EC_RST# power r ai l t o +3V_EC

Usi ng power r ai l whi ch t he same wi t h EC

P. 32

Change EC_SMB_CK1 & EC_SMB_DA1 power r ai l t o +3V_EC

Usi ng power r ai l whi ch t he same wi t h EC

P. 14

Change U5 f r om 4MB t o 8MB ROM

Fol l ow common desi gn

P. 32

Chagne R416 t o shor t pad

P. 42

Reser ve +1. 05S_VCCP_PWRGOOD of +V1. 05S_VCCP t o connect t o SA_PGOOD

DVT TO PVT D

PVT TO Pr e- MP For Cel er on/ Pent i um CPU

Compal Secret Data

Security Classification Issued Date

2011/06/15

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

4019N1

Wednesday, May 08, 2013

Sheet 1

Rev B 52

Version c hange list (P. I . R. List) I tem

Reason f or change

Page 3 of 3 f or H W PI R PG#

Modif y List

Date

Phase

44 D

45 46 47 48

51 52

53 B

Compal Secret Data

Security Classification Issued Date

2011/06/15

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc. SCHEMATIC M/B LA-9902

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

4019N1

Wednesday, May 08, 2013

Sheet 1

Rev B 52