Thesis a real time qpsk transceiver

FACULTY OF ENGINIEERING TECHNOLOGY CAMPUS GROUP T

A real-time QPSK transceiver Using an open hardware platform for a software defined radio implementation

Ambasa Aklilu & Jef Sabo

Promotor: Prof. L. Bienstman Master thesis to obtain the degree of Master of Science in Engineering Technology: Electronics and ICT

Academic year 2016-2017

Š Copyright KU Leuven

Without written permission of the supervisor(s) and the author(s) it is forbidden to reproduce or adapt in any form or by any means any part of this publication. Requests for obtaining the right to reproduce or utilize parts of this publication should be addressed to KU Leuven, Technology Campus Groep T Leuven, Andreas Vesaliusstraat 13, B-3000 Leuven, +32 16 30 10 30 or via email fet.groept@kuleuven.be.

A written permission of the supervisor(s) is also required to use the methods, products, schematics and programs described in this work for industrial or commercial use, and for submitting this publication in scientific contests.

FOREWORD This thesis is the result of two students’ master program at the Faculty of Engineering Technology at campus GroupT of the KULeuven university. We have studied the field of electronics and ICT over the course of several years and all our knowledge and skills in the field of engineering sciences are owed to the efforts of the many professors and assistants who work at the campus to teach students this broad discipline. We have a great gratitude for the people who passionately passed on their knowledge and knowhow to us. We would also like to thank the campus for the generous supply of teaching materials and facilities which we could use extensively for gaining skills and knowledge over the course of years. The philosophy of GroupT to teach necessary theoretical background together with diverse practical applications and hands-on projects has enabled us to achieve the target of this thesis using a broad knowledge basis and problem-solving pragmatism. Teamwork, planning, project management and other soft skills were equally important for this project and were also a continuous aspect of our education at GroupT. A more specific word of gratitude for Prof. Luc Bienstman is appropriate. Prof. Bienstman has taught the many aspects of practical digital design, which is the main aspect of this thesis, during different stages of our education. He has offered us this thesis subject as a challenging objective to obtain a masters’ degree in Electronics and he has supported the project vigorously as promotor. We are deeply grateful for his continuous support and guidance. Finally, we would like to thank the UGent and its radio research teams for supplying materials for this thesis.

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ABSTRACT This paper describes the digital implementation of a real-time QPSK transceiver on a software defined radio platform. A software defined radio is a radio system where the signal processing and modulation happens on a reconfigurable platform, making the system adaptable to different radio standards. The platform for this thesis consists of the Digilent Zedboard and the Analog Devices FMCOMMS1 analog RF front-end, connected with an FMC connector. Both prototyping boards are open hardware and enable designers to develop various SDR schemes with general purpose tools. This document emphasizes the digital implementation details of QPSK modulation and demodulation using the reconfigurable logic on the Zedboard. Analog Devices provides a complete development reference design for the Zedboard and FMCOMMS1 setup. The reference design contains a design for the programmable logic datapath between the Zedboard memory and the FMCOMMS1 hardware. It also contains application software for the processing system on the Zedboard which provides easy communication with the hardware on both development boards. The reference design itself does not implement any digital modulation scheme and the main subject of this paper is the development of a custom digital QPSK modulation scheme that can be inserted into the reference design to obtain a functional radio system. The resulting system is capable of running a transmission throughput of 15.36Mbits/s. Simulation results show good noise-rejection and stability in the system. Real-life deployment on the hardware provides proof of the functionality of the design. The final system presented in this thesis runs a QPSK radio system at a very basic level. Future work can expand the design to include carrier synchronization logic, automatic gain control and memory access. The radio system could then be used to send and receive payload data like audio and video, instead of test bit patterns which is the case for the project at this point.

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EXTENDED ABSTRACT This paper describes the digital implementation of a real-time QPSK transceiver on a software defined radio platform. A software defined radio is a radio system where the signal processing and modulation happens on a reconfigurable platform, making the system adaptable to different radio standards. The platform for this thesis consists of the Digilent Zedboard and the Analog Devices FMCOMMS1, connected with an FMC connector.

The Zedboard features a Xilinx Zynq 7000 System-on-Chip. It has FPGA fabric for reconfigurable hardware development and an ARM CPU for software co-development on a single chip. The FMCOMMS1 is a general purpose analog RF front-end. Both prototyping boards are open hardware and enable designers to develop various SDR schemes with general purpose tools. This thesis exploits the capabilities of these devices to implement a functional radio system using QPSK at the physical layer. The proposed system is an example implementation for the SDR platform, but the reconfigurability of the system ensures that many modulation schemes can run on it. The thesis handles the practical setup of the hardware and software components for SDR applications and clarifies how the system is adaptable for custom radio designs. More specifically, it emphasizes the digital implementation details of QPSK modulation and demodulation using the reconfigurable logic on the Zynq. The tools for developing on the Zynq are Xilinx Vivado and Xilinx System Generator for DSP. The tools enable complete hardware/software codesign of the digital system with Vivado and a rapid design flow for DSP with System Generator. Analog Devices provides a complete development reference design for the Zedboard and FMCOMMS1 setup. The reference design contains a HDL part for the programmable logic in the Zynq. It implements a datapath from memory to the DAC interface IP core at the transmitter side and a datapath from the ADC interface IP core back to memory at the receiver side. The reference design also contains application software for the processing system in the Zynq. It runs an API to communicate with all hardware components in the programmable logic, as well as with the fixed analog hardware on the FMCOMMS1. The reference design itself does not implement any digital modulation scheme and the main subject of this paper is the development of a custom digital QPSK modulation scheme that can be inserted into the reference design to obtain a functional radio system. The resulting system is capable of running the modulation scheme with a bit rate of 15.36Mbits/s. The thesis describes how the system performs in the System Generator simulation environment as well as after deployment on the actual hardware platform. The results in simulation predict that the modulation scheme is noise resistant and stable. The most important logic that defines the demodulation quality is the symbol timing recovery loop at the receiver. Simulation results show it can lock into sampling any input symbol stream at the maximum effect points. The results after deployment onto the actual hardware confirms that the system can transmit and receive data through the ether at 15.36Mbit/s. The results after deployment are analyzed using Vivado Integrated Logic Analyzer by viewing the received data at the output of the custom demodulation logic in the Zynq. The final system presented in this thesis runs a QPSK radio system at a very basic level. Future work can expand the design to include carrier synchronization logic, automatic gain control and memory access. The radio system could then be used to send and receive payload data like audio and video, instead of test bit patterns which is the case for the project at this point.

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SUMMARY FOREWORD ...................................................................................................... 3 ABSTRACT ........................................................................................................ 4 EXTENDED ABSTRACT....................................................................................... 5 SUMMARY ......................................................................................................... 6 INTRODUCTION................................................................................................ 8 1

NATURE AND SCOPE OF THE THESIS .................................................. 9

1.1 1.2 1.3

Existing SDR solutions ....................................................................... 9 QPSK modulation ............................................................................... 9 Outline of the paper ......................................................................... 11

2

REQUIREMENTS ANALYSIS .............................................................. 12

3

DESIGN PLATFORM .......................................................................... 13

3.1 3.1.1

Hardware ......................................................................................... 13 Digilent Zedboard ................................................................................ 13

3.1.1.1

Input/output .................................................................................................................. 13

3.2.1.1 3.2.1.2 3.2.1.3

Vivado IP Integrator ........................................................................................................ 15 Vivado SDK .................................................................................................................... 15 Vivado ILA ..................................................................................................................... 15

3.4.2.1 3.4.2.2 3.4.2.3

The ad9122 and transmitter core ...................................................................................... 17 The ad9643 and receiver core .......................................................................................... 18 Memory datapath ............................................................................................................ 18

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IMPLEMENTATION ........................................................................... 20

4.1 4.2 4.2.1 4.2.2 4.2.3

Overview .......................................................................................... 20 Transmitter ...................................................................................... 20 Data source ......................................................................................... 20 QPSK modulator .................................................................................. 21 Root raised cosine pulse shaping filter .................................................... 22

4.2.3.1 4.2.3.2

Bandwidth...................................................................................................................... 22 Inter-symbol interference ................................................................................................ 23

4.2.4.1 4.2.4.2

Spectral aliasing ............................................................................................................. 25 Signal-to-noise ratio ........................................................................................................ 25

3.1.2 3.2 3.2.1

3.2.2 3.3 3.3.1 3.3.2 3.4 3.4.1 3.4.2

3.4.3

4.2.4 4.2.5 4.3 4.3.1 4.3.2 4.3.3 4.4 4.5 4.5.1 4.5.2

Analog Devices FMCOMMS1 ................................................................... 14 Software .......................................................................................... 15 Vivado Design Suite ............................................................................. 15

Xilinx System Generator for DSP ............................................................ 15 ADI reference design ....................................................................... 15 HDL reference design ........................................................................... 15 Software reference design ..................................................................... 16 Integration ...................................................................................... 17 Updating the reference design ............................................................... 17 Integrating custom IP cores into the reference block design ...................... 17

Adapting the software parameters .......................................................... 18

2x interpolation halfband filter ............................................................... 24

Data packing ....................................................................................... 26 Channel model ................................................................................. 26 Free space path loss ............................................................................. 26 Add white Gaussian noise...................................................................... 27 Carrier phase and frequency offset ......................................................... 27 ADC model ....................................................................................... 27 Receiver ........................................................................................... 27 Data formatting ................................................................................... 27 2x decimation halfband filter ................................................................. 27

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4.5.3 4.5.4

Root raised cosine filter ........................................................................ 28 Symbol timing synchronizer .................................................................. 28

4.5.4.1 4.5.4.2 4.5.4.3 4.5.4.4

Early-late timing error detection ....................................................................................... 28 Numerically controlled counter .......................................................................................... 29 Loop filter ...................................................................................................................... 30 Outputs ......................................................................................................................... 30

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EVALUATION .................................................................................... 32

5.1 5.1.1 5.1.2 5.1.3 5.2 5.2.1 5.3 5.3.1 5.3.2 5.3.3 5.4

Simulation results ............................................................................ 32 Constellation diagram after the symbol timing synchronizer ...................... 32 Time to achieve lock ............................................................................. 33 Bit Error Rate (BER) ............................................................................. 33 Results after deployment ................................................................. 33 Phase ambiguity .................................................................................. 34 Hardware resource utilization .......................................................... 35 Transmitter IP core .............................................................................. 35 Receiver IP core ................................................................................... 35 Design total ......................................................................................... 35 Development process ....................................................................... 36

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FUTURE WORK ................................................................................. 38

6.1 6.2 6.3 6.4 6.5 6.6

Carrier synchronization .................................................................... 38 Automatic Gain Control .................................................................... 38 Memory datapath ............................................................................. 38 Quality tests ..................................................................................... 38 Hardware optimization..................................................................... 38 OFDM ............................................................................................... 39

4.5.5

Decision logic ...................................................................................... 31

CONCLUSION.................................................................................................. 40 REFERENCES .................................................................................................. 41

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INTRODUCTION A Software Defined Radio is a radio communication system where (most of) the signal processing happens on a reconfigurable platform, instead of dedicated hardware (What is Software Defined Radio, 2017). Such a platform can be software or reconfigurable hardware. The SDR idea already exists for some time (Friedrich, 2005), but it is in recent years that digital systems are becoming powerful enough to realize feasible implementations. A general purpose PC could serve as an SDR, when it is coupled with an analog RF front-end, A/D and D/A converters. It could run demodulation algorithms purely in software, maintaining the possibility to switch standards just by replacing the program. Also, any embedded processor or DSP could perform the same task. The advantage of enabling one device to run different communication protocols is obvious.

The reconfigurable nature of an SDR is also advantageous for the deployment of new protocols and techniques, since the device would merely require an update to support new functionality. Another benefit of the SDR architecture is the possibility to fix issues and deploy updates whenever a problem arises. The device can adapt to different circumstances and use cases, as opposed to the dedicated hardware implementations. A general purpose computer or CPU can provide reconfigurability and calculate demodulation schemes, but not in real-time. The amount of high-speed DSP necessary to accommodate real-time radio communication is too high. Radio developers mostly use CPU’s to simulate radio demodulation schemes off the line. Engineers have to look to other dedicated, reconfigurable hardware for real-time solutions.

DSP’s are processors that are designed and optimized to run DSP algorithms faster and more efficiently than CPU’s. DSP’s contain dedicated multiply-accumulators and have optimized instructions for DSP. They can be a candidate for real-time SDR solutions A regular software program provides reconfigurability and if the DSP can handle the throughput, real-time functionality is achievable. DSP’s, like CPU’s, execute commands in a serial fashion and very high instruction speeds are necessary to accommodate realtime SDR functionality. FPGA’s provide reconfigurable logic and dedicated DSP slices inside the FPGA fabric. The massively-parallel, reconfigurable nature of FPGA’s provide a good solution for real-time SDR implementations. New System-On-Chips feature FPGA fabric with an embedded processor on a single chip. These hardware/software co-design chips provide an excellent solution for real-time SDR applications together with high-level software functionality. This thesis implements a real-time radio system on such a platform.

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1

NATURE AND SCOPE OF THE THESIS

The target is to develop a complete radio transmission modulation/demodulation scheme in the digital domain, using a System-On-Chip. The radio system should be practically functional, so interfacing with analog RF hardware is a part of the design task. Another important aspect of the design is coping with real-life transmission impairments. In order to develop a real-time SDR implementation on a general-purpose SoC, the demodulation design needs an efficient implementation, tailored to the limitations of the digital platform. The analog RF front-end also has practical limitations and these need to be considered during the design. The thesis focuses on the implementation aspects of the SDR scheme. Theoretical background is a necessity to understand and develop SDR solutions, but this paper does not go into much detailed theory as the digital design implementation is the most important aspect. The nature of one specific (de)modulation implementation for SDR is that it is only one particular implementation. The design in this thesis can run on the platform, but any other digital (de)modulation scheme can be developed for it.

1.1

Existing SDR solutions

Some companies have commercially available SDR platforms. Nuand sells the BladeRF, a low-cost SDR platform based on an Altera FPGA. It supplies up to 28MHz baseband bandwidth. Nutaq has different SDR solutions. One of them is called the picoSDR. It features a Xilinx FPGA and a baseband bandwidth of 20MHz. This SDR solution is capable of running a real-time 64-QAM OFDM transceiver.

Figure 1. Nutaq PicoSDR, a commerciallly available SDR solution

Research teams also develop SDR applications and devise new technologies for the field.

IDLab from Imec is an example in Belgium. The problem with these commercial products is that they are closed-source hardware, and the development of different SDR schemes for these platforms are also closed-source implementations, developed by the vendors.

This thesis uses general-purpose hardware instead. The SoC sits on a regular development board which can be used for the development of any digital system. The analog RF front-end also contains general-purpose RF hardware which can be used for a wide range of applications. The resulting platform is available for any designer interested in developing SDR applications for it.

1.2

QPSK modulation

The (de)modulation scheme of choice for this thesis is called Quadrature-phase-shiftkeying. It is the protocol that transmits and receives raw data in the physical

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communication layer. QPSK is a widely used modulation scheme. For example the Wireless-LAN standard IEEE 802.11b uses QPSK as the modulation scheme at the physical layer. Phase shift keying transmits data over a carrier by modulating its phase.

Modulating the phase of the carrier provides good noise rejection, because random noise doesn’t change the phase of a signal. That is why PSK methods are more popular than, for example, ASK (Amplitude Shift Keying) methods which are more susceptible to noise.

QPSK schemes consist out of 2 channels, called the I (in-phase) and Q (quadrature) channels. Both channels are independently modulated with BPSK. BPSK inverts the carrier phase for a 1/0 transition in the datastream (Debaene, 2017).

Figure 2. I and Q channels are BPSK modulated, resulting signal is QPSK modulated

The baseband digital modulation scheme is fully I/Q based and is therefore a dualchannel BPSK modulator. The analog RF front-end phase shifts the carrier into an I carrier and a Q carrier with a 90° phase difference (as in figure 2.). The baseband signals modulate their respective carrier sinusoids and then sum together to form the transmitted QPSK modulated carrier. The carrier now has 4 distinct phase conditions which represent the payload data. The QPSK constellation diagram shows this property.

Figure 3. QPSK constellation diagram

This thesis implements QPSK as an example implementation for an open SDR platform.

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1.3

Outline of the paper

The rest of this paper contains the path to implementation of a real-time QPSK protocol in the physical layer. The requirements analysis states the goals and the minimal requirements of the project. The design platform section gives an overview of all the hardware, software and other tools that took part in the development process. It explains how all the parts are reconfigurable for a wide range of SDR implementations as well as how the integration of all parts into a working SDR solution is possible. It also clarifies where and how the custom digital design fits into the reconfigurable hardware and software. The implementation section describes in detail how every step of the digital modulation scheme works, and it explains every design choice. The implementation section handles the core design of this thesis. It abstracts away all the surrounding hardware and focuses on the actual implementation of the digital modulation scheme.

The evaluation section discusses the results of the design, in simulation and also with real-life signals after deployment on the hardware platform. It also discusses the hardware resource usage and a reflection about the development process. The future work section describes which goals were not met, as well as possible improvements and expansions of the design. Finally, the conclusion summarizes the project.

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2

REQUIREMENTS ANALYSIS

The primary goal of this thesis is to implement a working QPSK transceiver on a reconfigurable platform. It should be able to modulate, transmit, receive and demodulate data in real-time. The campus supplied the platform, containing the hardware, software tools and licenses to develop the transceiver. The promotor also introduced a master’s thesis from an alumnus as a starting point for the development (Pham, 2016). The minimal requirement is to implement an embedded custom modulation scheme that is compatible with the hardware with the help of all tools provided. The modulation scheme of choice was OFDM at first, but this changed to QPSK after time considerations. The design should be general, scalable, easily parameterized and easy to deploy to other platforms as this conforms to the SDR philosophy.

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3

DESIGN PLATFORM

The following section provides an overview of the design tools that were used for developing the QPSK transceiver. First, the used hardware is explained in brief. Second, the software tools and frameworks which enabled the implementation of our design into the hardware are described. Finally, the integration of all the tools and hardware into the complete project is clarified.

3.1

Hardware

3.1.1

Digilent Zedboard

The Zedboard is a prototyping development board, featuring a Xilinx Zynq 7000 SystemOn-Chip. The Zynq series feature a combination of a processing system (PS) and programmable logic (PL) on a single chip. The PS contains a dual-core ARM Cortex-A9 processor, running at 650MHz. The PL is general purpose 28nm FPGA fabric, with embedded DSP slices (Zedboard documentation, 2014). This creates a powerful platform for hardware/software co-design.

3.1.1.1

Input/output

The Zedboard offers many I/O interfaces for the Zynq. The most important connector for this project is the FMC connector (FPGA Mezzanine Card), which is an industry standard for high speed peripherals for reconfigurable I/O devices. It enables high speed data transfers between the Zynq and externally connected hardware, making the system modular.

Figure 4. Digilent Zedboard

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3.1.2

Analog Devices FMCOMMS1

The FMCOMMS1 is a high-speed analog RF frontend. It enables prototyping of diverse wireless modulation schemes. The hardware on the board can be configured through I2C to adapt to a wide range of applications. It uses the FMC connector to connect to the Zedboard.

Figure 5. FMCOMMS1 functional overview (Analog Devices Inc., 2015)

Figure 5 shows an overview of the various components of the FMCOMMS1, which are:       

AD9122: Dual 16-bit DAC, with a sampling frequency up to 1200MSPS. ADL5375: 400MHz to 6GHz broadband quadrature analog modulator.

ADF4351: Wideband synthesizer with integrated VCO, 35MHz to 4400MHz. ADL5602: Linear amplifier for operation between 50MHz and 4GHz, +20dB gain.

ADL5380: 400MHZ to 6GHz quadrature demodulator with 500MHz bandwidth.

AD8366: Linear amplifier for operation between DC and 600MHz with programmable gain from 4.5dB to 20.5dB. AD9643: Dual 14-bit ADC, with a sampling frequency up to 250MSPS.

The Analog devices reference design (see section 3.3) provides an easy way to configure the hardware of the FMCOMMS1.

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3.2

Software

3.2.1

Vivado Design Suite

Xilinx provides Vivado as a software design suite to develop projects for their products.

Vivado provides the tools to develop hardware for the PL and software for the PS. It boasts many features for advanced configuration and programming, some of the most important features for this thesis are highlighted.

3.2.1.1

Vivado IP Integrator

IP integrator provides an overview of the hardware system. A block design contains all the IP cores and their connections. The block design compiles into a bitstream for the PL hardware configuration, and it can be exported into a hardware definition file for the Software Development Kit (SDK).

3.2.1.2

Vivado SDK

The Software Development Kit provides a framework to develop software for the PS, in addition to the hardware. The hardware definition file contains all hardware addresses and definitions for co-designing the software with the hardware.

3.2.1.3

Vivado ILA

The Integrated Logic Analyzer provides a way to debug and view signals within the PL when the system is actually running. This way the designer can validate the design after the hardware is deployed into the PL. 3.2.2

Xilinx System Generator for DSP

System generator is a high-level design tool for DSP algorithms for Xilinx devices (Xilinx Inc., 2016). It offers a design flow with Matlab and Simulink as development environments. Xilinx provides a blockset to use within Simulink to create digital DSP circuits. System generator compiles these circuits to IP cores for integration into a Vivado IP Integrator block diagram. The development of this thesis’ QPSK transceiver digital modulation scheme was entirely developed using System Generator.

3.3

ADI reference design

Analog devices provides a complete hardware/software framework to develop SDR applications with the FMCOMMS1 and Zedboard (Analog Devices Inc., 2017). It abstracts many implementation details for the development boards to work together, so the designer can focus on developing their own modulation algorithms in the PS or in the PL. The HDL hardware framework is a complete datapath to and from memory, together with IP cores that interface with the FMCOMMS1 hardware. The software framework offers initialization of hardware parameters, test routines and an API for easy configuration of various hardware components. There is also a Linux distribution available with specific applications for the FMCOMMS1 and Zedboard setup (Analog Devices Inc., 2013), but this thesis uses the no-OS bare-metal software for easier low-level access.

3.3.1

HDL reference design

The transmitter section of the PL datapath takes data out of a DMA (Direct Memory Access) module and propagates the data to the ad9122 IP core. This core is the interface to the DAC on the FMCOMMS1. The ad9122 core also contains DDS (Direct Digital Synthesis) modules which can produce sinusoids with programmable phase and

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frequency. From the software, the designer can choose to use memory or DDS as a data source for transmission. When the memory datapath is enabled, the ad9122 core takes samples from its inputs as data source. When the DDS is enabled, the core generates sinusoidal data on its own. The software can then also configure the DDS properties.

Figure 6. HDL reference design (Analog Devices Inc., 2015)

Figure 6 can be placed directly to the left of figure 5 to produce a system overview of the PL design and the FMCOMMS1, connected by the FMC connector.

The receive path propagates the received samples coming from the ad9643 core into memory through DMA. 3.3.2

Software reference design

The no-os software of the reference design implements an API to interact with the hardware components in the PL and on the FMCOMMS1. There are three main layers to the software stack, this is visible in figure 7: 





Device Drivers Layer: this layer contains the drivers for all the parts on the FMCOMMS1. Each driver defines all the registers for a specific part and implements the functions needed to interact with that part XCOMM API: this layer implements all the high level functions required to interact with the FMCOMMS1. It hides the implementation details of the actual device drivers and provides a convenient way to work with the board.

PIC Communication Abstraction Layer: this layer implements all the functions needed to communicate with the PIC located on the FMCOMMS1. Its purpose is to translate the drivers’ SPI calls into PIC I2C commands.

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Figure 7. Reference design software stack (Analog Devices Inc., 2012)

The reference design software also contains a test program which initializes all components to standard values, and runs some basic tests.

3.4

Integration

Adaptations to the reference design were necessary to incorporate the QPSK modulation scheme presented in this thesis.

3.4.1

Updating the reference design

Analog devices considers The FMCOMMS1 and its reference design to be obsolete. The most recent build of the reference design is one for Vivado 2015.4. The first task of this thesis was to update everything to the most recent version, which is Vivado 2017.1 at this point. In order to do so, some IP cores had to be removed from the block diagram as they produced errors during updating. The removed components are the I2S and HDMI cores. They are not important for the design, so no functionality was lost by doing this.

However, if the design is to be used with a Linux distribution, instead of the no-os software, these cores have to be implemented for audio and image functionality.

Another consequence of the obsolescence of the reference design is the lack of support for it. The students put a considerate amount of time in figuring out the exact functionality and timing of the ad9122 and ad9643 cores.

3.4.2

Integrating custom IP cores into the reference block design

System generator compiles a design into a netlist folder. This folder contains all files necessary for Vivado IP Integrator to insert the IP core into a block diagram. The netlist folder should be included in the IP repository of the project.

3.4.2.1

The ad9122 and transmitter core

With the memory datapath to the ad9122 core enabled, the inputs of the core accept incoming samples. Channel 0 of the DAC goes to the in-phase branch of the analog modulator. Channel 1 goes to the quadrature branch of the analog modulator. Every I/Q input sample is a 64-bit packet containing 4 16-bit samples, with the last sample in time being the 16 MSB’s of the packet. The ad9122 core will then serialize these packets using SERDES, providing a 16-bit sample to the DAC at every DAC clock pulse. The data format

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of every 16-bit sample for the DAC can either be 2’s complement or offset binary and is configurable by the software.

Figure 8. Custom System Generator transmitter IP core connected to the ad9122 core

The dac_div_clk output of the ad9122 core is the clock signal for sampling the 64-bit packets. In other words, this clock runs at ¼ frequency of the DAC sampling frequency on the FMCOMMS1. The custom core runs at the actual sampling frequency, so an MMCM (mixed-mode clocking manager) generates the DAC clock from the ¼ DAC clock.

The custom QPSK transmitter core of this design does not accept input data at this point, see the Implementation section for more details.

3.4.2.2

The ad9643 and receiver core

The ad9643 core clock output is the actual sampling clock of the ADC on the FMCOMMS1.

The output samples of the core are 16-bit unsigned values, where the 2MSB’s are always 0 because the ADC only has a resolution of 14 bits. The receiver core connects to the outputs of the ad9643 core as shown in figure 9.

Figure 9. Custom System Generator receiver IP core connected to the ad9643 core

3.4.2.3

Memory datapath

The memory datapath is left unconnected to the transmitter and receiver core. The transmitter core generates test bit patterns for transmission and the receiver core outputs are connected to an ILA core to view the received results. The design needs future work to connect the datapath to the transmit and receive cores in order to send custom data, controlled from the software.

3.4.3

Adapting the software parameters

Important parameter settings for the FMCOMMS1 are available at the top of the main.c file, such as: sampling rates, receiver amplifier gain and carrier frequency.

The settings for this designs are as follows:    

ADC sampling rate = 122.88 MSPS DAC sampling rate = 122.88 MSPS Receiver amplifier gain = 20.5dB Carrier frequency = 2.4GHz

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The remainder of the standard test program in the reference design was not adapted significantly, except for: 

A #DAC_DMA definition in the main.c file enables the datapath from memory to the ad9122 core.  An xcomm API function call sets the DAC data format to 2’s complement: “XCOMM_SetDacDataFormat(0);” The custom IP cores of this thesis are not accessible through the software for configuration.

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4

IMPLEMENTATION

This section describes the implementation details of the digital QPSK modulation scheme.

The system is a Xilinx System Generator design and is insertable into the HDL reference design as a transmitter IP core and a receiver IP core. The yellow in and out blocks mark the peripherals of the cores, they will be accessible for connections in Vivado IP Integrator.

4.1

Overview

Figure 10. System Generator design overview

4.2

Transmitter

Figure 11. Transmitter design

4.2.1

Data source

The data source consists of two lookup tables containing test bit patterns. They represent the even/odd bits of custom input data. The bitrate per channel is equal to the symbol rate, 7.68Mbit/s. This makes the total bitrate equal to 15.36Mbit/s. The test bit pattern for both channels is “1 0 1 0 1 0 1 1 0 0 1 1 1 0 0 0�. This test bit pattern is visible in figure 12, 13, 15 and 19. This way, the functionality of all blocks in the transmitter datapath is visualized in the time domain using the same input data.

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Figure 12. Input bit pattern on one channel

To use custom data, one needs to remove the lookup tables and instead implement an even/odd bit multiplexer to split the user input data stream into even and odd bits for the I and Q channels, respectively.

4.2.2

QPSK modulator

The modulator converts the input bits from 0/1 pulses to +1/-1 pulses (scaled down to an amplitude of 0.6 for dynamic range). It then up samples these pulses 8 times with zero stuffing, creating distinct return-to-zero pulses at a sample rate of 61.44MSPS.

Figure 13. Distinct return-to-zero +1/-1 pulses

In figure 13, notice how the pulses are separated by seven 0-samples and how the pulses have a positive and negative magnitude, as opposed to the input bitstream of figure 12.

The two channels now carry discrete I and Q components of QPSK symbols; Both channels always contain one of the constellation points of the QPSK constellation diagram: 1/1, 1/-1, -1/1 or -1/-1. The zero-stuffed periods are there for the RRC pulse shaping filter (see the next section). Figure 14 visualizes this principle by showing the datastream in the I and Q channels after the QPSK modulator block, when a random bitstream is connected to the inputs instead of the test bit pattern.

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Figure 14. I and Q components of QPSK symbols from random even/odd bitstreams

The I and Q channels in the digital domain are not actually in quadrature. The purpose of the naming is that the I and Q samples will eventually be 90° phase shifted in the analog front-end, after D/A conversion, when the analog signal is modulated onto the RF carrier.

The rest of this section will only discuss one channel, because the other channel operates exactly the same.

4.2.3

Root raised cosine pulse shaping filter

The data stream consists of square pulses and therefore has an infinite bandwidth. A pulse shaping filter smooths the pulses in the time domain and thereby limits the bandwidth of the signal in the frequency domain (Avnet Inc., 2013).

Figure 15. Symbols after RRC filter

Figure 15 shows the smoothing action of the filter on the test bit pattern. The zero-stuffed periods are used by the filter for smoothing. A sample rate of 61.44MSPS and a symbol rate of 7.68Msymbols/s means that there are 8 samples per symbol available, which is an important design parameter for the pulse shaping filter. The QPSK modulator block defines this parameter by up sampling 8 times with zero stuffing.

One of the most frequently used pulse shaping filters is the Root Raised Cosine filter. The RRC filter has the beneficial effects of limiting the bandwidth and inter-symbol interference, which are explained next.

4.2.3.1

Bandwidth

The RRC filter has a low-pass characteristic which limits the bandwidth of the pulse train.

The parameters that define the filter response are the samples per symbol, the stopband

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attenuation and the roll-off factor. As mentioned before, there are 8 samples per symbol.

For a given stopband attenuation, a high roll-off factor Îą results in high bandwidth, but good side lobe attenuation. A small roll-off factor provides narrow bandwidth, but less side lobe attenuation. A good trade-off value of Îą = 0.35 (Debaene, 2017) is chosen for our design, with a stopband attenuation of Astop = -20dB. More stopband attenuation would require a filter of a higher order and would use more hardware resources.

Figure 16. Spectrum after RRC filter (Îą = 0.35; Astop = -20dB)

The roll-off factor defines the bandwidth according to: đ??ľđ?‘Š = đ?‘…đ?‘ đ?‘Śđ?‘šđ?‘?đ?‘œđ?‘™ ∗ (1 + đ?›ź) đ??ľđ?‘Š = 7.68 ∗ 106 ∗ 1,35 đ??ľđ?‘Š = 10,368 đ?‘€đ??ťđ?‘§ This bandwidth is visible in the spectrum plot in figure 16. Also note that the magnitude at +/- 5.184MHz is equal to the stopband attenuation of -20dB. 4.2.3.2

Inter-symbol interference

Another very important property of the RRC filter is the effect on inter-symbol interference. The RRC filter at the transmitter is matched with a symmetrical RRC filter at the receiver. This matched filter-pair has a combined response that is called the Raised Cosine response (RC). One could argue that there is no need for another pulse shaping filter in the receiver, as there are no pulses to smooth in the transmitted signal. However, the purpose of the RRC filter in the receiver is not pulse shaping. It filters the transmitted signal with another RRC response to obtain the RC response. The reason for this is the desired quality of supplying theoretical zero ISI. To illustrate this, figure 17 shows the impulse response of the matched filter pair (RC impulse response).

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Figure 17. Raised cosine matched filter impulse response

Notice there are 8 samples per zero-crossing in the impulse response, which corresponds to the 8 samples per symbol in the signal. An impulse results in a local maximum at the center tap, and subsequent symbol pulses will not affect each other as every local maximum point corresponds to a zero-crossing of the previous/next pulse. Figure 18 illustrates this property by showing consecutive impulse responses to a pulse train at the symbol rate.

Figure 18. Consecutive raised-cosine impulses, demonstrating zero ISI property

The peak points of every impulse, which fall together with zero-crossings of previous/next pulses are called the maximum-effect points. These points exhibit no interference from other symbols, which is the desired zero-ISI property. This will be important later on for the symbol timing synchronizer at the receiver.

4.2.4

2x interpolation halfband filter

A Digital Up Converter (DUC) interpolates the samples and increases the sample rate from 61.44MSPS to 122.88MSPS, which is the sample rate of the DAC. The design implements an 18th order halfband low pass interpolation filter, which is efficient for implementation in hardware because every second coefficient tap is equal to 0 except for the center tap, which is equal to 0.5 (Avnet Inc., 2013). The DAC of the FMCOMMS1 can run at sample rates over 1GHz, and it is beneficial to do so.

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Figure 19. Symbols after interpolation up sampling

4.2.4.1

Spectral aliasing

A high sampling rate puts a greater distance between the spectral images of the signal at the analog output of the DAC. This eases the analog hardware requirements for the anti-aliasing reconstruction filter (Avnet Inc., 2013).

4.2.4.2

Signal-to-noise ratio

An interpolated digital signal contains less quantization noise. This improves the overall signal-to-noise ratio of the transmitted signal.

The low pass characteristic is necessary because of the sampling rate change. The higher sampling rate introduces a spectral image of the RRC response, which needs to be filtered out. Figure 20 shows the spectral image of the RRC response and the low pass characteristic of the interpolation filter that cuts it off.

Figure 20. Low pass interpolation filter removes the spectral image of the up sampled RRC response

A normalized cutoff frequency value of 0.2 for the 18 th order filter removes the spectral image, while keeping the roll-off response of the RRC filter intact.

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Figure 21. Spectrum of the transmitted signal

Figure 21 shows that the transmitted signal of the implemented design contains no aliasing and still preserves the roll-off shape of the RRC filter. This design implements a sampling rate of 122.88MSPS because the FPGA fabric can easily meet the timing requirements at this speed. An improvement of the design could implement an extra interpolation filter and an interface to fully use the SERDES functionality of the 4:1 serialization in the AXI_AD9122 IP core of the reference design.

4.2.5

Data packing

At this point, the data is ready for D/A conversion and transmission. The data packing block converts all samples to the correct 2’s complement format for the DAC. It also puts 4 samples of 16-bit into one packet of 64-bit. The ad_9122 IP core will serialize these packets through SERDES functionality at the peripherals of the FPGA fabric and the FMCOMMS1.

4.3

Channel model

Figure 22. Channel model

The channel model enables us to insert RF transmission impairments into the design simulation. The samples coming from the interpolation filter bypass the data packing block, as that block formats data for the hardware DAC and it is not applicable to the simulation environment.

4.3.1

Free space path loss

Transmission through the ether will attenuate the signal considerably. The free space path loss block models this impairment in order to simulate the receiver response at different attenuation levels.

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4.3.2

Add white Gaussian noise

The AWGN block adds random noise to the signal, as will be the case in the ether. This way we can simulate what the receiver’s response will be at different signal-to-noise ratio’s.

4.3.3

Carrier phase and frequency offset

Another important RF impairment is carrier offset. The carrier oscillators at transmitter and receiver are never exactly synchronized. This causes the constellation diagram after symbol recovery to rotate. At this point, carrier synchronization is not implemented in the design and therefore it is pointless to include the impairment in the simulation. The symbol timing recovery loop is able to achieve lock with a carrier offset, so baseband carrier synchronization can readily be implemented in the design.

4.4

ADC model

The ADC model block serves as a simulation representation of the behavior of the ADC on the FMCOMMS1 and the ad_9643 IP core in the reference design. The ADC has a 14bit resolution, and therefore only 14 significant bits exist. The IP core formats these 14 bits into a 16 bit unsigned value, where the 2 MSB’s are always 0 and the binary point is at 0. This data format propagates towards the receiver block, which formats the data again to a usable fractional representation.

4.5

Receiver

Figure 23. Receiver design

4.5.1

Data formatting

The format block formats the unsigned 16 bit data with 2 meaningless MSB’s to a signed 16-bit fractional value. There are only 14 meaningful bits in the data, but the block converts the data to 16-bit fractional values for symmetrical implementations of the receiver and transmitter filters.

4.5.2

2x decimation halfband filter

The decimation filter has the same order and type as the interpolation filter at the transmitter, it also uses the same coefficients. This filter is implemented as a decimation filter and decimates the incoming datastream from 122.88MSPS to 61.44 MSPS.

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4.5.3

Root raised cosine filter

This filter is the matched filter to the RRC filter at the transmitter. The output of the filter produces symbols with theoretically zero ISI when sampled at their maximum effect points (see section 4.2.3.2). The symbol recovery loop is responsible for doing that.

4.5.4

Symbol timing synchronizer

Figure 24. Symbol timing synchronizer design

The symbol timing synchronizer is a loop containing an Early Late Timing Error Detector (ELTED), a loop filter and a Numerically Controlled Clock (NCC). This system has to sample the incoming symbols at their maximum effect points. The logic in the TED, loop filter and NCC implement full precision arithmetic as rounding or truncating causes instability in the loop.

4.5.4.1

Early-late timing error detection

The I and Q symbols enter the TED as signed signals. The TED rectifies the signal to strictly positive values by multiplying the signal with itself. The resulting signal is a

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positive squared version. This squared signal has the extra advantage of magnifying the symbol slopes and peaks. The TED routes the incoming squared symbols through an early branch and a late branch. In this design, they are 1 symbol period (8 samples) delayed relative to each other.

Figure 25. ELTED design

A subtraction of the early and late signals yields the error signal for that channel, with the error signal being the level difference of the early and late samples. Finally, the error signals for both channels are summed together to give the total error output.

Figure 26. Early late error detection mechanism (Robert, Kenneth, Dale, & Louise, 2015)

The total error signal is only zero when the early and late branches of both channels are equally leveled. At this time instance, the punctual branch is at a maximum effect point, as shown in figure 26. The punctual branch bypasses the TED and has a delay of ½ symbol period plus the propagation delay of the TED, as shown in the bottom left part of figure 24. This puts the punctual branch between the early and late branches in time.

The early and late branches are only there for measuring the error, while the punctual branch is the signal that has to be sampled at the maximum effect point.

4.5.4.2

Numerically controlled counter

The NCC counts up to 8, then overflows and produces a strobe signal. This gives the strobe clock a nominal period equal to the symbol period (8 samples).

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Figure 27. Nominal NCC strobe generation

The strobe signal samples the timing error of the TED. The error sample enters the loop filter, which is a simple constant multiplication in this case. The error sample then enters the NCC as an adjustment value to the nominal accumulator step size of 1. This means that the NCC will accumulate faster or slower, depending on the adjustment value. As a consequence, the strobe clock will also speed up or slow down. When the strobe clock synchronizes to the maximum effect points: the TED error sample becomes zero every time, the step size of the NCC stays at the nominal step size of 1 and the strobe clock continues sampling at a constant rate equal to the symbol rate. At synchronization, the NCC actually produces strobes that are half a Symbol period delayed to the punctual branch maximum effect points, that is why the strobe is delayed half a symbol period extra before sampling it (Robert, Kenneth, Dale, & Louise, 2015), as shown in the central part of figure 24.

Figure 28. NCC design

4.5.4.3

Loop filter

The loop filter is a P controller, multiplying the sampled timing error signal with the constant Kp = 0.125. This value provides a stable loop and is also a power of 2, making it possible to execute the multiplication with zero latency. Further improvements are possible by implementing a PI(D) controller in the loop filter.

4.5.4.4

Outputs

The strobe, I_data and Q_data outputs are available as outputs in the top level design.

They are connected to gateway out blocks, making them easily accessible in Vivado IP integrator and for debugging and viewing in Vivado ILA. The I_data and Q_data output ports are the symbols coming from the RRC filter at 61.44MSPS. Together with the strobe signal, they can be used to check if the symbol timing loop has locked into sampling at

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the maximum effect points, when the design is running on actual hardware.

The I_out and Q_out signals are the sampled symbols and continue the datapath to the decision logic. The I_out and Q_out ports are also the ports where one can attach a Simulink constellation diagram viewer to assess the demodulation quality of the system.

4.5.5

Decision logic

The decision logic is the final stage of the datapath. The symbols have been sampled at their maximum effect point and the decision logic converts the positive samples to a 1 and the negative samples to a 0. The outputs after this stage contain the even bits on the I channel and the odd bits on the Q channel.

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5

EVALUATION

This section evaluates the radio system quality. Many evaluation results are only obtainable in the simulation environment at this point of the project. That is why the simulation results are the first chapter of this section. The results after deployment on the hardware are summarized in the next chapter. The third chapter contains some information about the hardware resource usage of the design in the PL. The final chapter is a reflection and evaluation of the development process of this thesis.

5.1

Simulation results

For evaluation purposes, the input bit test pattern data is replaced by random data. This way, the evaluation results apply to any input data.

5.1.1

Constellation diagram after the symbol timing synchronizer

The constellation diagram, also referred to as scatter plot, provides a visual way of measuring the quality of the demodulation.

Figure 29. Scatter plots at the output of the locked symbol timing synchronizer for a SNR of (a)19dB; (b)16dB; (c)13dB; (d)10dB

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Figure 29 shows the scatter plots of the sampled symbols at the outputs of the symbol timing synchronizer after it has achieved lock, for different signal-to-noise ratios. At high SNR’s the sampled symbols are packed densely around the optimal points. At a SNR of only 10dB, the sampled symbols show some divergence from the optimal points.

Once the STS has achieved lock, the loop never loses lock again. This shows that the loop is stable.

5.1.2

Time to achieve lock

Since the input data is random, the time for the STS to achieve lock varies significantly.

The amount of noise also influences the time to achieve lock. A preamble bit pattern should be developed to achieve lock in a predictable way before any payload data is sent.

5.1.3

Bit Error Rate (BER)

The BER at different noise levels was simulated in Simulink. The results after 1 second of transmission is the same for all signal-to-noise ratios: 0% BER after the STS has achieved lock. The students know that this simulated result is not applicable to real-life situations, where the BER will be larger than 0%. The amount of time it takes to simulate 1 second of transmission is very large and the results are not usable. The students can conclude, however, that the symbol recovery loop would be very noise-resistant in real life applications.

5.2

Results after deployment

The results after deployment are proof of a functional radio system. The system runs on the hardware instead of in simulations and the transmitter communicates with the receiver through the actual ether. The evaluation of the functionality after deployment is through Vivado ILA. The logic analyzer buffers samples coming from the receiver core outputs. They are the actual signals from within the running hardware.

Figure 30. Receiver outputs in ILA. From top to bottom: Even bits (I channel) output, Odd bits (Q channel) output, I symbols, strobe clock, Q symbols

Figure 30 shows all signals at the output of the receiver core. The top 2 signals are the even and odd output bits. They are the output of the complete system and should be equal to the input bit pattern. The results show that the output is indeed the same as the input, so the radio system does transmit and receive the test data correctly. The 3 rd and 5th signal are the I and Q symbols of the punctual branches in the STS, respectively. The 4th signal, which is the strobe clock, samples the symbols at their maximum effect points.

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Figure 31. Closer look at the STS timing

Figure 31 show the functionality of the STS strobe clock more clearly. Every strobe pulse is exactly at the maximum effect point of a symbol. The yellow marker line shows one example of such a sample point. The top 2 signals, which are the outputs of the system, show some propagation delay because of the decision logic that follows the STS. 5.2.1

Phase ambiguity

When the antenna does not move and receives a reasonable signal, the radio system demodulates the transmitted test bit pattern well. The only problem for good demodulation is the phase ambiguity. Sometimes the I and Q data arrive at different phase angles, and the transmitted data cannot truthfully be recovered by an even/odd bit multiplexer.

Figure 32. I and Q signals out of phase

Figure 32 shows this effect. The I and Q symbols are 180° out of phase. There are many plausible causes for this effect, but this thesis did not finish a thorough analysis.

A good idea is to implement differential coding into the modulation scheme to remove phase ambiguity. Carrier frequency and phase offset can also contribute to this effect, as well as multipath reflections. The thesis needs further work to solve these problems.

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5.3

Hardware resource utilization

Since all the DSP involved in the reconfigurable radio system runs on the FPGA fabric of the Zynq SoC, the resource utilization of the system on the PL is an important property of the design. The students developed the design with hardware efficiency in mind, and the resulting design should use minimal hardware resources. System generator provides a compiler that generates the resource usage of a design.

5.3.1

Transmitter IP core

Figure 33. Transmitter IP core resources

Figure 33 shows the amount of resources used in the PL for the transmitter core. The amount of LUTs and registers used is negligible, as the total available amounts are several orders of magnitude larger. The design uses 36 dedicated DSP slices, which is a considerate portion of the 220 available DSP slices. The most expensive part of the design is the RRC filter. Further design optimizations could reduce the hardware cost of that part.

5.3.2

Receiver IP core

Figure 34. Receiver IP core resources

Figure 34 shows the amount of resources used in the PL for the receiver core. The usage of LUTs and registers is comparable to the transmitter core. The amount of DSP slices is 39, because the extra STS logic uses 3 DSP slices. Design optimizations in the RRC filter would also greatly benefit the DSP slice usage in the receiver core.

5.3.3

Design total

The ADI reference design also uses considerate resources. The resource usage of the reference design, incorporating the custom IP cores, is considered next.

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Figure 35. Total resources

The amount of used LUTs, registers, distributed-RAM and block-RAM are only small parts of the total available resources. Although the usage can significantly be reduced by deleting unused parts of the ADI reference design. The design uses 161 DSP slices, which is a 73.18% use of the available resources. The total amount of DSP slices used by the custom cores is equal to only 75 slices, which means that the reference design itself uses 86 DSP slices. Again, significant resource optimizations are possible by optimizing and deleting parts of the reference design. There are 4 MMCM modules available on the Zynq PL. The reference design uses 2 MMCM’s, while the custom transmitter IP core clock generator uses 1 MMCM.

5.4

Development process

The development of a radio system using reconfigurable logic requires a multitude of skills and knowledge about various engineering domains. The students experienced a steep learning curve to implement DSP algorithms for radio systems using new tools and frameworks. A theoretical background in wireless communication theory is the first basic prerequisite to start developing an SDR system. A thorough understanding of what happens in every step of a modulation datapath is necessary before it is possible to create one. Studying the wide field of wireless communications systems was therefore the first step of the development process. The next step in the development process of this thesis was gaining deep understanding of the ADI reference design. The HDL design is no longer supported and a significant amount of time was spent in analyzing the functionality of all parts of it. The reference design, both software and HDL, are meant to provide a communication interface and development platform for the Zedboard and the FMCOMMS1. Understanding the functionality of all parts on the FMCOMMS1 was therefore also a crucial part of the development process. After understanding the reference design and the FMCOMMS1 design platform, the reference design needed updating to the most recent Vivado version: 2017.1. Unfortunately the reference design is not easily updateable and many iterations and manual adaptations in the HDL code were necessary to succeed in updating it. The I2S and HDMI interface IP cores had to be removed from the project to gain fully updated functionality. Once the development platform was ready to use, the students had to understand how any custom IP core could fit into the reference design while still keeping all functionality of it available. Then the development process of our custom QPSK modulation and demodulation cores could start. In order to start developing a modulation scheme using FPGA fabric containing DSP slices, the students needed to acquire skills for a suitable design flow. The design flow in this thesis used Xilinx System Generator for DSP extensively. The design flow proved to be a very effective one, but a significant time of the development process was spent gaining skills and know-how concerning System Generator, DSP in general and efficient FPGA resource

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usage.

In summary, the development process for an SDR system using the Zedboard, FMCOMMS1 and reference frameworks was primarily a long phase of gaining skills and knowledge to work with the tools and the theory behind RF. Once the development process passed this phase, the focus on actual development increased and the ease of getting to functional results accelerated rapidly. At the final stages of development, the students gained a deep understanding of many engineering facets and a hands-on approach to problem solving using the provided tools. The possibility to gain a quick path to development has a lot to do with System Generator for DSP. The high-level design tool allows designers to accelerate the design flow for DSP algorithms. The students feel that the project, given some more time, would have rapidly increased in complexity and functionality due to the accelerating design flow.

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6

FUTURE WORK

The design in this thesis is far from complete. The core functionality of a QPSK (de)modulation scheme is present, but many extra features still need implementation for a fully functional radio system.

6.1

Carrier synchronization

Since the transmitter and receiver analog RF modulation section on the FMCOMMS1 share the same PCB, which means they have the same temperature and noise interference and they also receive the same control signals at the exact same time, there is no need to implement carrier synchronization. The phase and frequency offset of the carrier synthesizers is negligible. However, this is not the case when a separate transmitter and receiver system is used as is the case in real life applications. In real life applications there will be some offset and the demodulator has to have carrier synchronization logic.

This logic is one of the most important features of the radio system that was not implemented.

6.2

Automatic Gain Control

The receiver design does not adapt to varying signal levels of the transmitted signal. At this point, the receiver analog amplifier is always at maximum gain, which means that when the signal is too strong, overflow and/or clipping of the signal will occur. When the signal is very weak, there is no room for extra amplification. The analog receiver amplifier should have a lower startup gain and the gain should be adjustable to the signal strength.

This would facilitate the option to amplify the signal when necessary. Extra logic is necessary to measure the signal strength, and adapt the receiver amplifier gain accordingly. This feature would make the radio system more adaptable to variable circumstances.

6.3

Memory datapath

The digital modulation scheme can send and receive any data, but the memory datapath (which is part of the reference design PL) to control which data is sent is not connected to the radio system. Since the radio system has a bit rate of 15.36Mbit/s, the datapath and FIFO settings to/from memory should be adapted to this rate. When the communication between memory and the modulation system is functional, the reference ADI reference Linux distribution for Zedboard + FMCOMMS1 can be used to run applications which transmit and receive any data. The system could, for example, transmit, receive and playback a video or audio stream.

6.4

Quality tests

This thesis ended with the development phase of the implementation of a basic transceiver at the physical layer. The project needs more testing before any attempts to expand the design are made. For example, the BER of the system functioning in a real life environment should be measured. The design also needs a preamble design for the STS to achieve lock before any payload data is sent.

6.5

Hardware optimization

Even though the design implements minimal hardware resources, there is still much room for improvement. The timing requirements of various parts can be analyzed and the hardware can be optimized to meet the timing requirements with minimal resource

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usage. It is advised to strip down many features of the reference HDL design in order to use just the necessary parts. This would greatly improve the hardware resource usage.

6.6

OFDM

When the design is fully functional, tested and optimized the design can be implemented as part of a OFDM transceiver. Various implementations of OFDM use QPSK to modulate and demodulate the baseband carriers. The QPSK design presented in this thesis is a candidate for implementation in an OFDM design, since it is easily parameterizable.

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CONCLUSION This thesis succeeds in the development of a functional transceiver using a reconfigurable platform. The result is an SDR system that implements QPSK as the modulation scheme.

The system has a throughput of 15.36Mbit/s and simulations show that the system is very noise resistant. Results after actual deployment show that the modulation and demodulation according to the QPSK scheme works well in real life. The project builds the system on a general purpose hardware platform. The digital platform is a Xilinx system-on-chip, it runs all real-time DSP on programmable logic with DSP slices and simultaneously runs a high-level software program that initializes and parameterizes all hardware components. Xilinx System Generator for DSP is the main tool of the building process for the digital modulation scheme. The resulting DSP datapath is reasonably efficient in hardware resources, but improvements are possible. Various other tools and interfaces provide a framework to make all hardware and software components work together in order to have a complete system. The integration of these parts into the bigger system was one of the more challenging parts of this thesis. The thesis accomplished to translate theoretical DSP and RF concepts into a practical application.

The most critical part of the digital demodulation scheme, the symbol timing synchronizer, seems to perform well in simulation and in reality. More in-depth tests are necessary to confirm the quality of the demodulation. The reference design, provided by Analog Devices, uses a lot of hardware resources. In order to use less hardware resources parts of it need to be stripped away. The system is a good starting point for a complete SDR system on open hardware, but there is still a lot of future work. Carrier synchronization is a crucial part of a practical receiver, but this thesis did not implement it. Other important expansions of the system include: automatic gain control, memory access and thorough result testing.

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REFERENCES Analog Devices Inc. (2012, December 14). AD-FMComms1-EBZ : no-OS Software Drivers. Retrieved from Analog Devices Wiki: https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1ebz/software/baremetal Analog Devices Inc. (2013, March 4). AD-FMCOMMS1-EBZ Linux support. Retrieved from Analog Devices Wiki: https://wiki.analog.com/resources/eval/userguides/ad-fmcomms1-ebz/software/linux Analog Devices Inc. (2015, July 15). AD-FMCOMMS1-EBZ Functional Overview.

Retrieved from Analog Devices Wiki: https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1ebz/hardware/functional_overview Analog Devices Inc. (2017, February 23). AD-FMCOMMS1-EBZ User Guide. Retrieved from Analog Devices Wiki: https://wiki.analog.com/resources/eval/userguides/ad-fmcomms1-ebz Avnet Inc. (2013). Zynq-7000 SoC / Analog Devices Software-Defined Radio Kit Lab 2: Digital Up/Down-Converters for Wireless Communications Using Model-Based Design with MATLAB and Simulink.

Debaene, T. (2017, February 13). Spread Spectrum and Multi-Carrier Systems. Leuven.

Friedrich, K. J. (2005). Software-Defined Radio - Basics and Evolution to Cognitive Radio. EURASIP Journal on Wireless Communications and Networking.

Pham, H. C. (2016). QPSK Implementations for OFDM Scheme Based SDR Platform.

Leuven: Faculty of Engineering Technology, Campus Group T. Robert, W. S., Kenneth, W. B., Dale, S. W., & Louise, H. C. (2015). Software Defined Radio using MATLAB & Simulink and the RTL-SDR. What is Software Defined Radio. (2017). Retrieved from Wireless Innovation Forum: http://www.wirelessinnovation.org/assets/documents/SoftwareDefinedRadio.pdf Xilinx Inc. (2016, April 6). Model-based DSP design using system generator. Retrieved from Xilinx: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug89 7-vivado-sysgen-user.pdf Zedboard documentation. (2014, January 27). Retrieved from Zedboard: http://zedboard.org/support/documentation/1521

FACULTY OF ENGINEERING TECHNOLOGY CAMPUS GROUP T Andreas Vesaliusstraat 13 3000 LEUVEN, Belgium tel. + 32 16 30 10 30 iiw.groept@kuleuven.be iiw.kuleuven.be