Computer Science 605.611

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Computer Science 605.611 Problem Set 8 Answers (For all of the questions on this problem set, assume that all branch instructions are treated as delayed branches.)

1. Consider the following instruction sequence that executes on our 5-stage scalar pipelined system with a hazard unit as well as a forwarding unit:

loop:

Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

ori add and bne srl addi add Fetch ori add $6 and bne srl addi add $3 add $6 and bne srl addi add $3 add $6 and bne srl addi add $3 add $6 and bne srl addi add $3 sll

$4,$0,4 $6,$7,$8 $9,$4,$7 $4,$0,loop $4,$4,1 $3,$0,1 $3,$3,$3

Decode Exec ori add and bne srl addi bubble add and bne srl addi bubble add and bne srl addi bubble add and bne srl addi add sll

ori add and bne srl bubble bubble add and bne srl bubble bubble add and bne srl bubble bubble add and bne srl addi add sll

Mem

ori add and bne srl bubble bubble add and bne srl bubble bubble add and bne srl bubble bubble add and bne srl addi add sll

Write-back

ori add and bne srl bubble bubble add and bne srl bubble bubble add and bne srl bubble bubble add and bne srl addi add sll

sll

$3,$3,1

a) (5) The ori instruction is fetched in cycle 1. During which clock cycle does the sll instruction complete the write-back stage if no early branch condition evaluation or branch prediction is used?

The ori instruction initializes $4 to the value 4. Each time that the bne instruction is executed, the srl in the delay slot is executed whether the branch is taken or not. The first time through the loop $4=4, $4=2 the second time, $4=1 the third time, $4=0 the last time through the loop.

The bne takes effect when it is in the memory stage. When the bne branches, the instructions in the decode and fetch stages will be flushed causing two bubbles. The last time through the loop, no flushing occurs since the branch is not taken. The instructions flow through the pipeline as follows:

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Therefore the sll completes its write-back stage in cycle 30. b) (5) The ori instruction is fetched in cycle 1. There is no early branch condition evaluation.

During which clock cycle does the sll instruction complete the write-back stage if branch prediction based on a decode history table (DHT) is used? Assume that the DHT always predicts that the branch will be taken.

When the branch is predicted in stage 2, the instruction in the delay slot (srl) will already be in the fetch stage. The next instruction that is fetched into the pipeline behind the srl instruction will be from the branch target address (i.e., the first add instruction). The first three predictions will be correct, but the last is incorrect. When the bne actually branches, no flushing occurs. Flushing only occurs when the prediction is wrong. The incorrect branch prediction will be detected and acted on when the bne is in the MEM stage which causes the two instructions (addi, and) along the incorrect path to be flushed. Hence the instructions flow through the pipeline as follows: Cycle Fetch Decode Exec Mem Write-back 1 ori add $6 ori 2 3 and add ori 4 bne and add ori 5 srl bne and add ori add $6 srl 6 bne and add 7 and add srl bne and 8 bne and add srl bne 9 srl bne and add srl add $6 srl 10 bne and add 11 and add srl bne and 12 bne and add srl bne 2

13 srl bne and add srl add $6 14 srl bne and add 15 and add srl bne and 16 bne and add srl bne 17 srl bne and add srl add $6 srl 18 bne and add 19 and add srl bne and bubble bubble srl 20 addi bne bubble bubble add $3 addi 21 srl bubble bubble 22 sll add addi bubble 23 sll add addi 24 sll add addi 25 sll add 26 sll Therefore the sll completes its write-back stage in cycle 26.

2. (5) Recall that our 5-stage MIPS pipeline is sometimes referred to as a “scalar” pipeline since at most one instruction can occupy any stage at one time. Which of the following types of hazards would this pipeline never experience and why? a) control hazard b) data hazard c) resource hazard (structural hazard) d) branch hazard The answer is c) resource hazard. No two instructions would attempt to use the resources in any pipeline stage at the same time (since each stage contains no more than one instruction).

3.(8) What sorts of changes need to be made to the Hazard Detection Unit to support early branch condition evaluation for the beq instruction?

For beq rs,rt,offset to calculate the branch target address in the ID stage, the Hazard Detection Unit (HDU) must identify situations in which the data for the registers used in the 3

beq instruction are not available during the ID stage and delay the evaluation of the register equality calculation until forwarding can make them available.

The new HDU hardware for the equations must handle: IF (EX/MEM.MemRead AND (ID/EX.opcode=Rtype OR ID/EX.opcode=beq) AND ((EX/MEM.RegisterRt = ID/EX.RegisterRs) or (EX/MEM.RegisterRt = ID/EX.RegisterRt))) stall the pipeline one cycle ELSE IF/ID.opcode=beq AND ( ID/EX.RegWrite=1 AND ( IF/ID.RegisterRs = ID/EX. RegisterRd OR IF/ID.RegisterRt = ID/EX. RegisterRd ) OR ID/EX.MemRead=1 AND (IF/ID.RegisterRs = ID/EX.RegisterRt OR IF/ID. RegisterRt = ID/EX.RegisterRt ) ) delay the beq to the EX stage.

Lines must be added between the HDU and the interstage registers for all the elements in the equations. Control lines for ID/EX.RegWrite and ID/EX.MemRead. Datapath lines for IF/ID.Instruction.opcode=beq, IF/ID.Instruction.rs, IF/ID.Instruction.rt, ID/EX. RegisterRd and ID/EX.RegisterRt. The branching control line which was moved to the ID stage must be duplicated in the EX stage where it started and a control line must signal which source to use for updating the PC.

4. a) (3) What is the earliest pipeline stage in which a branch prediction can be made for the third pass through a loop if the prediction is based on a branch history table?

Since the predicted behavior is obtained based only on the address in the PC, the branch history table can be accessed in stage 1 (the fetch stage). b) (3) When the prediction for a conditional branch instruction is found in a decode history table, what is the maximum branch penalty (i.e., the maximum number of pipeline bubbles required) if the prediction turns out to be incorrect?

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With a decode history table the branch prediction occurs in the ID stage but the actual branch behavior is not known until after the condition has been tested and the EX stage completes. When the branch instruction enters the MEM stage there are 3 instructions behind it in the pipeline. Due to the delayed branch, only the 2 newest stages have to be flushed resulting in a maximum branch penalty of 2 cycles.

5. Consider the following sequence of actual outcomes for a single static branch. “T” means the branch is taken. “N” means the branch is not taken. For this question, assume that this is the only branch in the program.

TTTNNNNTTNTTNTTNNY (i.e., the branch is taken on the first 3 encounters, not taken on the 4th, etc.) a) (7) Assume that we try to predict the branch behavior with a BHT (branch history table) using one-bit counters. The counters in the BHT are initialized to the 0 (not

taken) state. Of the 18 predictions, how many are correct and how many are mispredictions (i.e., incorrect)? For each entry in the table below, show the branch prediction bit before and after the branch is processed and indicate whether or not a misprediction occurs.

Predictor bit before

Branch outcome

0

T T T N N N N T T N T T N T T N N Y

Predictor bit after

Misprediction?

(Y or N)

There are 9 correct 1 Y predictions and 9 1 1 N mispredictions.

1 1 N 1 0 Y b) (8) Now, 0 0 N assume that the 0 0 N branch prediction 0 0 N is based on 2 bits 0 1 Y (initially 00) and 1 1 N that the branch 1 0 Y behaves the same 0 1 Y as in part a). Of the 1 1 N 18 predictions, how 1 0 Y many are correct 0 1 Y with the 2-bit 1 1 N predictor and how 1 0 Y many are 0 0 N mispredictions (i.e., 0 1 Y incorrect)? For each entry in the table below, show the 2 branch prediction bits before and after the branch is processed and indicate whether or not a misprediction occurs.

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Prediction bits before

Branch outcome

Prediction bits after

Misprediction?

(Y or N)

00 N T 01 Y 01 N T 10 Y 10 T T 11 N 11 T N 10 Y 10 T N 01 Y 01 N N 00 N 00 N N 00 N 00 N T 01 Y 01 N T 10 Y 10 T N 01 Y 01 N T 10 Y 10 T T 11 N 11 T N 10 Y 10 T T 11 N 11 T T 11 N 11 T N 10 Y 10 T N 01 Y 01 N Y 10 Y There are 6 correct predictions and 12 mispredictions.

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6. a) (3) Explain why data forwarding can or cannot be used to avoid stalling the ori instruction in the following instruction sequence on a scalar pipeline: lw ori

$5,44($2) $10,$5,0x01FF

Forwarding cannot be used because the required value will not be available until the lw completes its read from memory (in stage 4). The lw reads memory during the same cycle that the ori instruction executes in stage 3, so the ori must be stalled in stage 3 for at least one cycle. b) (3) What type of data hazard (RAW, WAR, WAW, or NONE) could the following two instructions cause each other on a scalar pipeline? sw lw

$5,44($2) $5,44($2)

None. The sw does not modify $5 and the lw does not use $5 as an input. Since instructions execute in-order on the scalar pipeline, the sw completes its write to memory before the lw reads from the location. Also since the instructions execute in the order listed, the lw can’t overwrite $5 before the sw reads $5. c) (3) What type of data hazard (RAW, WAR, WAW, or NONE), and which register(s) could the following two instructions cause each other on a superscalar pipeline? sw lw

$5,44($2) $5,44($2)

On a superscalar system the lw could be allowed to execute before the sw (for example, if the sw was stalled waiting on a result in $5). If so, the lw would change the value in $5 that the sw would write to memory. This would be a WAR data hazard on register $5.

Also a RAW data hazard exists on the shared memory word since the sw must write to memory before the lw reads from the same memory word. Otherwise the lw would read the previous contents of the memory word.

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7. (8) On a certain VLIW system, each long instruction word generated by the compiler is a packet or bundle of six individual machine operations. The hardware system contains three integer units and three floating point units. Therefore, up to 3 integer operations and 3 floating point operations can be performed in parallel in the same clock cycle. However, due to the mix of available instructions and possible dependencies, the system may not be able to make use of all the execution units in every cycle. In that case, the compiler would insert one or more nops into the instruction bundle (i.e., into the long instruction word) to fill any unused slots.

Using the following format to show the instructions within each long instruction word: Int unit1

Int unit2

Int unit3

Flt unit1

Flt unit2

Flt unit3

List the contents of the all long instruction words or bundles that the compiler would generate for the following group of instructions using the minimum number of nops: add add mtc1 cvt.s.w sub.s add.s sll sub.s

$11,$2,$3 $4,$5,$12 $4,$f12 $f12,$f12 $f14,$f16,$f18 $f8,$f14,$f12 $6,$11,5 $f8,$f14,$f8

Based on the available execution units and the dependencies among the instructions, the following 5 long instruction words will be produced: Int unit1 Int unit2 Int unit3 Flt unit1 Flt unit2 Flt unit3 add $11,$2,$3 add $4,$5,$12 sub.s $f14,$f16,$f18 nop nop nop sll $6,$11,5 mtc1 $4,$f12 nop nop nop nop cvt.s.w $f12,$f12 nop nop nop nop nop add.s $f8,$f14,$f12 nop nop nop nop nop nop nop nop nop nop sub.s $f8,$f14,$f8 Floating point instructions must execute on a floating point unit and CPU instructions must execute on an integer unit. The mtc1 instruction is a CPU instruction. The add must write $4 before the mtc1 reads $4. The mtc1 most copy $4 into $f12 before the cvt.s.w can convert the contents of $f12. The cvt.s.w must write $f12 before the add.s reads $f12 and the add.s must write $f8 before the sub.s reads $f8.

8. (5) What is the main advantage provided by the use of separate reservation stations for the execution units within a superscalar system versus using a centralized instruction window?

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When a reservation station becomes full, only later instructions that require the same reservation station are stalled. However, a full instruction window causes later instructions of all types to be stalled. So there is a greater chance that one or more execution units will be idle due to a full instruction window. One or more full reservation stations still allow further instructions to be processed as long as those instructions map to execution units to a reservation station with room. Also simplifies optimization.

9. The diagram below represents a degree 2 superscalar version of our 5-stage MIPS pipelined system. The decode stage includes a buffer to hold instructions that have been decoded but cannot yet execute. The system allows both out-of-order execution and out-of-order completion.

a) (5) What is the maximum throughput (IPC) of this superscalar system for a program consisting of 2 R-type instruction for each 1 load/store instruction?

The maximum throughput is 1.5 instructions per cycle. At most 2 instructions (one R-type and one Mem instruction) can be in the write back stage and write their results in parallel, but half of the instruction pairs have only an R-type instruction. b) (3) What is the maximum throughput of this superscalar system for a program consisting of only R-type instructions?

The maximum throughput is 1 instruction per cycle since the R-type datapath can execute at most one instruction at a time. c) (5) How many clock cycles does the following short instruction sequence consume on this superscalar system?

1. add $5,$4,$3 2. lw $2,16($6) 3. sub $9,$7,$8 4. sw $10,48($12) Since there are no dependencies, no stalls are required.

The add and lw are fetched in cycle 1.

In cycle 2 the add and lw are decoded; the sub and sw are fetched.

In cycle 3 the add and lw are dispatched to their respective execution units; sub & sw are decoded.

In cycle 4 the add writes its result, the lw reads from memory, the sub and sw are executed.

In cycle 5 the lw writes $2, the sub writes $9 and the sw writes to memory 9

In cycle 6 the sw idles in the write-back stage. So the code sequence consumes a total of 6 cycles. d) (3) How many clock cycles does the same instruction sequence consume on the original 5-stage scalar system?

The add instruction completes in cycle 5, and each of the following instructions takes 1 additional cycle for a total of 8 clock cycles. e) (3) How many read ports are required for the register unit to support the superscalar system?

Recall that a separate read port is required for each register input operand.

Four read ports are required since up to 4 input registers can be used (2 per instruction).

An R-type and a sw instruction executing together each have to read a pair of registers at the same time. f) (3) How many write ports are required for the register unit to support the superscalar system?

Write ports receive the register results produced by instructions.

Two write ports are required to allow 2 instructions to write a result register at the same time.

10. (3) Which one of the following is the main reason for using delayed branches? a) to reduce the number of data hazards b) to provide time to compute the branch target address c) to reduce the number of pipeline bubbles d) to provide time to predict the branch behavior The main reason is c) to reduce the number of bubbles that result when a branch is taken.

11. (3) With what pipeline stage is a reorder buffer (ROB) associated and what is its purpose A ROB is associated with the write-back stage. This is a buffer in which instructions that have completed execution (possibly out of order) on a superscalar system are held until they can write their results in the order called for by the original machine code program.

12. Suppose that our 5-stage MIPS pipeline system were transformed into a degree-4 superscalar system. Between which two pipeline stages would each of the following be used? a) (3) a reservation station between the decode stage and the execute stage. b) (3) an ROB (reorder buffer) between the memory stage and the write-back stage. The lw reads its memory operand in stage 4 (the memory stage) before entering the ROB.

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