Verilog Analysis on Mealy and Moore Finite State Machine and Hardware Design

Verilog Analysis on Mealy and Moore Finite State Machine and Hardware Design Alexios Kotsis

University of California Santa Cruz USA November 2018

Abstract— this paper begins with the basic concepts of Verilog language, its use in Finite Sate Machines, and then performs a Verilog analysis of two synchronous sequential circuit Finite State Machines with one input X and one output Z. One FSM is Mealy type and the other one is Moore type. The paper describes the implementation of the sequential circuit using logic gates and D Flip Flops.

The behavior of the circuits and timing diagrams is described by using Modelsim program, and four system Verilog programs one for the actual circuit and one used for test benching for both the Mealy and Moore cases.

An analysis was made in the state sequence, the reduction using Karnaugh maps and finally hardware designing the Finite state Machine using D flip-flops, AND, OR and INVERTER gates.

The paper is addressed to those with an elementary to medium knowledge of Verilog who are interested following the run procedure and code writing of a project. The project is made in order to demonstrate how a state machine behaves with fetch, decode and writeback using Verilog. The software used was System Verilog which is a combination of C/C++, Verilog and also Co-Design Automation Superlog language and was run in a home PC. Finally, a timing diagram was made demonstrating how the Finite Machines behave under clock pulses. .

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Contents 1. INTRODUCTION……………………………………………………………………………………………………………………..3 2. VERILOG AND DESIGN FLOW…………………………………………………………………………………….……………3 3. SYSTEM LEVEL VERIFICATION AND TESTING...……………………………………………………………….……… 4 4. LOOK AHEAD SYNTHESIS………………………………………………………………………………………………………..5 5. ABSTRUCTION LEVELS…………………………………………………………………………………………………………….5 6. DESIGN PROCESS……………………………………………………………………………………………………………….……6 7. SYSTEM LEVEL…………………………………………………………………………………………………………………………7 8. DIGITAL-ANALOG…………………………………………………………………………………………………….………………7 9. VALUES WIRES AND REGISTERS………………………………………………………………..…………………………….7 10. VECTORS…………………………………………………………………………………………………………………………………8 11. DIRECTIVES AND LITERALS………………………………………………………………………………………………………8 12. OPERATORS…………………………………………………………………………………………………………………………….8 13. RUNNING CYCLE……………………………………………………………………………………………………………………..8 14. MEALY FINITE MACHINE ANALYSIS………………………………………………………………………………………..10 15. VERILOG CODING OF THE MEALY FINITE STATE MACHINE……………………………………………………..13 16. MOORE FINITE MACHINE ANALYSIS……………………………………………………………………………………….15 17. VERILOG CODING OF THE MOORE FINITE STATE MACHINE……………………………………………………18 18. VERILOG MOORE AND MEALY PROJECT SIMULATION……………………………………………………………20 19. CONCLUTION…………………………………………………………………………………………………………………………24 20. REFERENCES…………………………………………………………………………………………………………………………..26

21. APPENDIX…………………………………………………………………………………………………………………..………….28

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1. INTRODUCTION VERILOG is a HDL language (Hardware Description Language) intended for describing systems electronic circuits and electronic designs.

What Verilog does is verification with simulation for logic synthesis, test analysis (with fault grading and testability analysis) and finally timing analysis and parallel activity flow.

Examples of designed circuits using Verilog hardware description language are the Intel Pentium microprocessor, the AMD K5, the AMD K6, the Athlon ARM7, etc., and thousands more use Verilog HDL. Verilog is used to produce the model of a system. This is done mainly for reasons of requirement specification, documentation, and control through simulation, formal verification and final synthesis of the required circuit.

The aim is to synthesize a circuit as much reliable as possible with low demands on cost, with low timing constraints, and avoid in advance designing faults.

Verilog can be used to simulate sequential circuits and especially Finite State Machines.

There are many applications that is required for the circuits to have some kind of memory to remember inputs in past time and accordingly calculate their outputs. The dependence of the input not only on the current input but also on the inputs of the past is what we call sequential logic.

We have two kinds of sequential logic Finite Sate Machines. The Mealy type and the Moore type.

In the Mealy Finite Sate Machine, the inputs affect the output which is in contrast with the Moore Finite State Machine where the output is a function only of its current state and not its input.

2. VERILOG AND DESIGN FLOW The design flow is in ASIC (Standard cell) gate array given in the next diagram Which summarizes the design in high level.

What must be noticed is that each section can be fragmented into smaller sections and as errors are revealed these sections in the flow will be iterated. When Verilog modeling is applied, these parts are: a. b. c. d.

Structural to connect the modules e.g. Counter counter_1 (clk, enable, count_out) Data Flow when we are using basic gates e.g. wire = (a&b)/ (c&d) ; Behavioral or Procedural with procedural calls e.g. always @ (posedge clk) beginâ&#x20AC;Śend Synthesizable versus not synthesizable e.g. a < = # 10b+1. e. RTL register transfer level when the design is been made in register level.

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Figure 1: Design flow [3]

3. SYSTEM LEVEL VERIFICATION AND TESTING The basic use of Verilog is to simulate and model of a system that contains FPGAs and ASICs but also can be used to simulate Analog systems and synchronous finite state machines.

This allows the system to be fully analyzed creating a functional description.

We are using Finite State Machines to simplify a complex dynamic problem by separating it into a set of static conditions (the states) and we use the dynamics of moving between them or the process flow (the transitions) in response to various events.

FSM achieves simplification of a complex dynamic problem by dividing it to a set of static conditionsâ&#x20AC;&#x201D;the states, and the dynamics of moving between them, or the processâ&#x20AC;&#x2122; flowâ&#x20AC;&#x201D;the transitions in response to events.

This will also allow the system to be validated before starting a working design in detail. It also allows the designer to have a partial description of the system in specific properties and with a performance model to investigate potential performance bottlenecks. The FSM model makes the transition from requirements to design to implementation simple.

In the end a test bench program must be introduced to verify the procedure with a timing diagram in reference to a clock, and inserting the appropriate delays for the proper display.

The Finite Sate Machine model has elements of the various phases of development so actually this is a layered structure as the following figure 2.

The specific information and data are in a layer of every development steps. First, we have the basic information and a description. Second, we specify the requirements of the system. Third we specify the way the state requirements will be implemented. Fourth we write the actual code either in VHDL, Verilog or Systemverilog to implement the state. We then do the test benching of the developed module.

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Figure 2: Finite State Machine of Development phase [15]

4. LOOK AHEAD SYNTHESIS The basic synthesis production is delayed until a complete functional simulation is achieved.

What bust be noticed is that in order to facilitate the evaluation of the architecture design and to assure area data and correct speed some early synthesis is required.

5. ABSTRUCTION LEVELS For different stages in the designing process Verilog can span many levels of abstraction as in the next figure.

In this way, Verilog, at the highest level, can have random probability distributions and queues.

Thus, Verilog can model the system at an elevated level of abstraction to prove how functional the system is, especially at the partitioning stage and the full analysis of the system.

In the end what Verilog does is to provide register transfer level analysis, very useful in designing digital circuits.

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Figure 3: Abstraction Levels [3] It also provides synthesis at the switching level logic simulation and synthesis at the gate level.

This included fault grading, dynamic timing analysis and testability analysis. In addition, Verilog can be used to take checkpoints and trace waveforms for a better evaluation and measurements of the system.

6. DESIGN PROCESS Verilog contributions in designing can be seen in Figure 4.

This included the full package from system analysis and partitioning to mixed signal simulation and final layout of the design.

Figure 4: Design Process [3] 6

7. SYSTEM LEVEL The drawback in Verilog is that it forbids the designer to deal with predefined system functions and overloaded operators while VHDL can.

It also has the limitation of the built-in language futures that will allow, up to certain degree, modeling performance, queueing and throughput.

Figure 5: Verilog system analysis [3]

8. DIGITAL- ANALOG Verilog is best used in today’s high-level digital hardware design within a full integrated environment in designing.

Thus, Verilog is used in switch level simulation, fault simulations and in providing worst-case scenarios in timing throughout the simulation procedure. It can also simulate routing delays and gate level fan out loading problems.

The level of abstraction of RTL can be useful for proper simulation before synthesis of the entire system project.

Since Verilog is a programming language, it can also be used for analog simulation and especially all cases in mixed signal and normal analog signal simulation.

9. VALUES WIRES AND REGISTERS The basic structural piece is the bit with values 0 and 1. In X we do not know the value or we do not care, and Z is not driven. The values are transmitted through wires- nets and are kept in registers. In the registers, they are combined and logical expressions are created. The expressions can be assigned in to the registers or wires.

Wires represent different unit connections. There are various types of wires but the most common one has the title “wire”.

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Wires do not hold values, they just transfer them and value assignments to wires are done only once.

The register “reg” holds the value assigned to him until the next assignment (like a variable in a programming language). It is used to describe the storage elements as flip-flops, latches memory etc. It is used for combined logic because it is more convenient than the net type.

10. VECTORS One bit cannot do much. We usually need a group of bits where everyone’s place is important (e.g. representing a number). They are called vectors and they exist in both reg and wire.

Describing the vector, it can be upper: lower with upper >= lower. The lower can be any number not necessarily zero. Verilog assigns zeros on the left whatever bits are missing at the assignment. Newer versions of Verilog add predefined types of reg and wire.

To combine vectors, we use {vector1, vector2, …, vectorn}. We can also combine the same vector by using { n { vector } }. It can also be used in the left side of an assignment.

11. DIRECTIVES AND LITERALS Verilog assigns steady values, macros and combines the files. It also translates conditionally into a certain time frame.

Literals usually have a predefined size and they usually start with “size ‘base”.

-size in bits, b-binary, o-octal, h-hexadecimal, d-decimal.

X or Y sets 1 bit for ‘b, 3 bit for ‘o, 4 bit for “h.

If the most significant bit is 0, x or z, it extends automatically till the left edge.

12. OPERATORS In Verilog the following operators are used:

13. RUNNING CYCLE Verilog is used to describe and make the event driven systems (change in state) with simulation starting at t=0. Events, as they processed, created new events. When all events at time t were actually processed, the time advanced to time t+1 (cycles) and stopped at the required cycle time.

The Verilog language used was System Verilog which is a combination of C/C++, Verilog and also Co-Design Automation Superlog language. On this manner the level of abstraction was high.

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Verilog is also used to describe combinational logic and especially finite Sate Machines with the two existing versions of Mealy and Moore type.

We notice the difference in the two codlings of the two FSM. In the Mealy type Finite State Machine, the system Verilog has to written in such a way so as in the computational logic to be able to present accordingly the present and the next state and in the end the output to be one or more cases [2].

Figure 6: Mealy Finite Machine Concept [4] In the Moore type machine, we use separate procedural blocks for the Next state. We then use combinational logic for the state update and also combinational logic for the output. Since the output is a function only of its current state and not its input, we have the output Z depending also on the input X [1].

Figure 7: Moore Finite Machine Concept [5] 9

14. MEALY FINITE MACHINE ANALYSIS We will now address the finite machine we are going to perform the analysis. The finite state machine is a synchronous sequential circuit with one input “X” and one output “Z” and four states named A, B, C, D and one reset in A with the state diagram as follows:

Figure 8: State Diagram of the Mealy Finite Sate Machine

We will describe the circuit, analyze it using Karnaugh maps and finally design it using two D flip-flops and the required And, OR and Inverter gates.

Describing the circuit, the initial sate is “A”. If we receive a positive “1”, we move to the next state, which is “B”, if on the other hand we receive a “0” the next state is “D”. The output Z for positive “1” is “1” and for “0” is “1”.

If we are in state “B” and we receive a “1”, we go to the next state, which is “D”. If we receive a “0”, we remain in the same state “B”. The output for positive “1” is “1” and for “0” is “0”.

If we are in state “C” and the system receives a “1” it goes to state “D” and if it receives a “0” goes to state “B”. The output Z is “1 for positive”1” and “0” for “0”.

If we are in state “D” and the system receives a “1” it returns to state “C” and if it receives a “0” it goes to state “A”. the output Z is “1” for positive “1” and also “1” for “0”.

The behavior of the two flip-flops D1 and D0 depends on the input state of Q1 and Q0.

The State Table symbolic and State Table encoded are given in the following tables: 10

STATE

TABLE

SYMBOLIC

New

State

Output Z

Present Sate

X=0

X=1

X=0

X=1

A

D

B

1

1

B

B

D

0

1

C

B

D

0

1

D

A

C

1

1

STATE

TABLE

ENCODED

D1

D0

Q1

Q0

X=0

X=1

X=0

X=1

0

0

11

01

1

1

0

1

01

11

0

1

1

0

01

11

0

1

1

1

00

10

1

1

We then perform a Karnaugh map analysis to reduce the required gates and been able to draw in the end a final hardware diagram as follows:

D1 X

1 0

Q0 0 1

1 1

Q0 1 1

D0 X

0 1 Q1

0 1

0 0 Q1

1 1

11

Z X

1 1

Q0 0 1

1 1 Q1

0 1

We can now deduce the results for the two D flip-flops and the output “Z” which is as follows:

D0 = Q1 + Q0 D1 = X Q1Q0 + XQ0 + XQ1 Z = X + Q1Q0 + Q1Q0 We then perform the designing of the two D flip-flops, 6 two input AND gates, 5 two input OR gates, 7 inverters, input “X” and the “output ” Z” using the OrCAD program as follows:

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Figure 9: Hardware design of the Mealy Finite Sate Machine

15. VERILOG CODING OF THE MEALY FINITE STATE MACHINE The program to be used is Modelsim. We first create a new file by the name AlexiosMealyFSM with the extension SV meaning Systemverilog.

For the input and out declaration we create a nodule with inputs as the clock to run synchronously the finite state machine, the input reset with negative logic (meaning with a low we are resetting the finite machine), the input “X” and the output “Z” as follows: //initiate Mealy Finite Sate Machine Alexios Kotsis (module AlexiosMealyFSM (clk, reset, X, Z); input clk, reset, X; output reg Z; We must then add the sate variables for the present and next state. We also load the local parameters specifications to specify the states A, B, C, D. To make the code more readable we assign a particular bit to pattern A, B, C, D and we count up the bits. These assignments cannot be changed from the outside. localparam A=2'b00, B=2'b01, C=2'b10, D=2'b11; Two bits are enough to make the state assignment.

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reg [1:0] presentstate,nextstate; And we also define the present sate and the output with: always @(presentstate,Z) We then define the next combinational logic which computes what the next specification is, based on the current state and also based on input “X” since we have a Mealy Finite State Machine.

We First specify the next state. So, if we are in the initial state “A” and if the input “X” is a “1” the next state is going to be “B” and the output “Z” at the same time is going to be “1”. If the input “X” is a “0” the next sate is going to be “D” and the output is going to be “1”.

We repeat the procedure with the other states: If we are in state B and we receive a “1” we go to the next state, which is “D” with an output of “1”, otherwise the next state is going to be “B” with an output “Z” of “0”. If we are in state “C” and we receive a “1” we go to the next state, which is “D” with an output of “1”, otherwise the next state is going to be “B” with an output “Z” of “0”. If we are in state “D” and we receive a “1” we go to the next state, which is “C” with an output of “1”, otherwise the next state is going to be “A” with an output “Z” of “0”.

The coding is a s follows: case (presentstate) A: if (X) begin nextstate = B; Z = 1; end else begin nextstate = D; Z = 1; end B: if (X) begin nextstate = D; Z = 1; end else begin nextstate = B; Z = 0; end C: if (X) begin nextstate = D; Z = 1; end else begin nextstate = B; Z = 0; end D: if (X) begin nextstate = C; Z = 1; end else begin nextstate = A; Z = 0; end endcase

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We must then do the update of the computational logic. So, if a negative edge happens it is a reset and the positive edge to be the clock. So, if we have a reset, we also have the present state otherwise the next state becomes the present state.

The coding is as follows: always @(negedge reset, posedge clk) if (!reset) presentstate <= A; else presentstate <= nextstate; And we finally end the initial module: endmodule // Mealy Finite Sate Machine Alexios Kotsis We then used the program MultiSim to compile the program and the result was successful as the following screen:

Figure 10: Successful Compilation of the Mealy FSM

16. MOORE FINITE MACHINE ANALYSIS

The Finite machine to be designed is a circuit from cmpe100L that will transmit a one cycle duration pulse when a button is pressed. The next pulse will be transmitted when the button 15

is depressed and pressed again.

Since this is a function regardless of the input and only depending on the current state so this is a Moore machine.

The machine is initialized / reset state and is waiting for a “1” in the input and then it transmits a high pulse as an output. In case the button is constantly pressed the finite system goes to the next state which has a loop to wait. In that state if the button is stopped being pressed the input receives a “0” and is sending a low in the output. The procedure is repeated again.

The state diagram of the Moore machine is follows:

Figure 11: Moore Finite State Machine The state table is as follows:

Current State A 0 0 0 0 1 1 1 1

Current Sate B 0 0 1 1 0 0 1 1

INPUT

NEXT

STATE

OUTPUT

I 0 1 0 1 0 1 0 1

D1 0 0 0 1 0 1 X X

D0 0 1 0 0 0 0 X X

Z 0 0 1 1 0 0 X X

And if we are to use D flip plops again the state table with D flip-flops is:

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Current Current INPUT State Sate A B I 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

NEXT

STATE OUTPUT

D1 0 0 0 1 0 1 X X

D0 0 1 0 0 0 0 X X

Z 0 0 1 1 0 0 X X

FlipFlop D1 0 0 0 1 0 1 X X

Inputs D0 0 1 0 0 0 0 X X

Doing the Karnaugh tables for the outputs of the two D flip -flops:

0 1

0 1

00 0 0

D1 01 0 0

11 1 X

10 0 X

00 00 0

D0 01 1 0

11 0 X

10 0 X

And the Karnaugh map for the output:

0 1

Output Z 0 0 0 Output is given by

1 1 1

Z =Q Q 0

1

We then perform the designing of the two D flip-flops, 3 AND gates and 1 OR gate, input “X” and the output” Z” using the OrCAD program as follows”

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Figure 12: Hardware Design of Moore Finite State Machine

17. VERILOG CODING OF THE MOORE FINITE STATE MACHINE The program to be used is Modelsim. We first create a new file by the name AlexiosMooreFSM with the extension SV, meaning Systemverilog.

We then use the Finite Sate Machine from figure 5 noticing that in the state named “B” depends on the present state.

Writing the code in Systemverilog we must write a module named AlexiosMooreFSM and inputs clock, reset, input X and output Z as follows: module AlexiosMooreFSM(input logic clk, input logic reset, input logic X, output logic Z); We then create a type definition for the states and since we only have four states we only need two bits. We then give these states values A, B, C and we call this type state as follows: typedef enum logic [1:0] { A, B, C } State; We then create two state variables, which are current state and the other next state as follows: State currentState, nextState; We must then determine that the state of the flip-flops is going to be determined by the positive edge of the clock. We then are going to check if the reset button is “high” we are going back no 18

matter what and the state is going to be “A”. To do that we write current state equals to “A”. If this is not going to happen in every positive, we are setting the current state equal to the next stage. This is the synchronous operation and the code is as follows: Always ff @(posedge clk) if(reset) currentState <= A; else currentState <= nextState; We must then insure that we have a combinational logic and what state to go on is based on the input. To do that we add the following line: always_comb We then write our case to be our current state.

If our current state is “A” and the input is “1” then the next case is “B”. If on the other hand the input is “0” the next case is going to be “D”. If the current state is “B” case(currentState) A: if(X) nextState = B; else nextState = A; We repeat the same algorithm for all the cases as follows: case(currentState) A: if(X) nextState = B; else nextState = D; B: if(X) nextState = C; else nextState = A; C: if(X) nextState = C; else nextState = A; endcase To ensure that everything will run smoothly by default if none of the cases is happening, we return by default to state “A” using the following line: default nextState =A; Since this is a Moore type Finite Sate Machine the output depends on the state so for output “Z” we assign the Current state to be equal to state “D” or state “C” and we are making an assignment as follows: assign Z = (currentState == C); We then end the module with the instruction: “endmodule”.

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We then used the program MultiSim to compile the program and the result was successful as the following screen:

Figure 13: Successful Compilation of the Moore FSM

18. VERILOG MOORE AND MEALY PROJECT SIMULATION To reach a timing diagram for our proposed Systemverilog code for the Mealy Finite Sate machine simulation we add a new project called AlexiosMealytestbench in MultiSim, which will have also the extension “sv” meaning systemverilog.

We first must establish a time scale, which can have the variable either 1 or 10 or 100 ns.

Since we are going to run the project for 100 Nano seconds and since we want a fast response, we choose 1 ns over 1 ns with the following line:

`timescale 1ns/1ns We then insert the name of the module to be tested which in our case is AlexiosMealyFSM. We must then add variables to be used in the simulation as logic variables, which are going to be the clock, the reset, the “in” and the “out”, which is the element that contains the output of the Finite State Machine as follows: logic clk; logic reset; logic in; logic out; 20

We must then wire everything together. We write “dut” which stands for “device under test”.

We insert the clock wire which is going to be fed by the variable “clock”, the reset wire variable which is going to be fed by the variable “reset”, the input “X” which is going to be fed by the variable “in” and the output “Z” which is going to be fed by the variable “out” as follows: AlexiosFSM1 dut( .clk(clk), .reset(reset), .X(in), .Z(out) ); We must then feed the initial values. The first initial value is “reset” when the input is “1” and we are going to wait for ten Nano seconds by inserting the value “#10”.

With then set “reset” equal to “0” and also wait for two Nano seconds by also inserting the value “#10”.

With the same procedure, we set the “in” to be set equal to “1” and wait for ten Nano seconds.

We repeat the procedure for a few more “in” with following code:

Begin reset <= 1; #10; reset <= 0; in <= 1; #10; in <= 1; #10; in <= 1; #10; in <= 1; #10; in <= 1; #10; in <= 0; #10; end We then have two categories. The first is when the clock goes “high” and when the clock goes “low”. Some delay is given, since we want the clock to run smoothly. We instruct the clock to wait for 5 Nano seconds for the “high” and 5 Nano seconds for the “low with meaning the whole period is going to be 10 Nano seconds with the following line:

Always Begin

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clk <= 1; #5; clk <= 0; #5; end We then compile the project using MultiSim with positive results as shown in the following picture.

Figure 14: Successful Compilation of the Mealy Test Bench We then simulate our initial project AlexiosMealyFSM by pressing “simulate without optimization” for the file Alexiostestbench.sv in the “work” library of MultiSim as follows:

This will create four objects in the simulation panel. These four objects we add to “Wave” and then “Signals in region”.

We then simulate our FSM my pressing “simulate” then “Run” and finally “run 100” meaning that our code will run for 100 Nano seconds and create the required dimming diagram which is presented in the next figure:

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Figure 14: Mealy Finite Machine Timing Diagram We repeat the same procedure for the Moore Finite State Machine and we compile the program with positive results as the next figure:

Figure 15: Successful Compilation of Moore Test Bench

We then follow the same procedure for the timing diagram as before with the Mealy Finite State Machine and we get the following timing diagram:

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Figure 16: Moore Finite Machine timing diagram 19. CONCLUSION Verilog hardware Description Language (HDL) is a very important language in todayâ&#x20AC;&#x2122;s world used in technology world and various companies designing Field Programming Gate arrays (FPFAs) and Application Specific Integrated Circuits (ASICs). The knowledge of this language is very important to engineers who are in Digital technology and networking systems to The project was made in order to demonstrate how a state machine behaves with fetch, decode and writeback using Verilog. The software used was System Verilog which is a combination of C/C++, Verilog and also Co-Design Automation Superlog language. On this manner the level of abstraction was high.

FSM states can have multiple layers. Every requirement layer can determine what is to happen in the state, creating a requirements Finite Sate Machine. These are used in the requirements engineering process by identifying missing and conflicting requirement. In such a way we can achieve a complete, better and correct requirements.

The project had to essentially demonstrate the two different kinds of Finite Sate Machines finish these four files in Systemverilog, compile them, and create timing diagrams demonstrating the various states of the Finite Sate Machine and their behavior: AlexiosMealyFSM AlexiosMealytestbench AlexiosMooreFSM 24

AlexiosMooretestbenchFSM The variation and the difference of the two types Finite Sate Machines of one depending on the previous state but also on the initial input (Mealy) and the other one only on the previous sate (Moore) led us in a variation of the total coding, represented in the Appendix, both on the computational logic but also on the form of the output coding.

In the end we used a test bench program to check the correctness of the code and also creating the required timing diagrams.

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REFERENCES

1. FSM-based Digital Design using Verilog HDL: Ian Elliott, Peter Minns, John Wiley & Sons, May 2008, ISBN: 9780470060704 2. Finite State Machines in Hardware: Theory and Design (with VHDL and SystemVerilog), Volnei A. Pedroni, The MIT Press, December 20, 2013 3. https://courses.cs.washington.edu/courses/cse567/01au/ 4. Modeling Software with Finite State Machines: A Practical Approach: Ferdinand Wagner, Ruedi Schmuki, and Thomas Wagner, May 15, 2006 5. Introduction to the theory of finite-state machines: Arthur Gill, 1962 6. https://en.wikipedia.org/wiki/Instruction_cycle 7. http://teachers.teicm.gr/kalomiros/Mtptx/e-books/Essential_VHDL_Kalomiros.pdf 8. http://docplayer.gr/33649362-Iy225-organosi-ypologiston-eisagogi-sti-verilog.html 9. https://ipfs.io/ipfs/QmXoypizjW3WknFiJnKLwHCnL72vedxjQkDDP1mXWo6uco/wiki/RIS C.html 10. https://ipfs.io/ipfs/QmXoypizjW3WknFiJnKLwHCnL72vedxjQkDDP1mXWo6uco/wiki/MIP S_architecture.html 11. Verilog of HDL Quick Reference Guide : Stuart Sutherland HDL 2001file /Verilog%20Books/[Stuart_Sutherland]_Verilog_2001_Quick_Reference_Guide.pdf 12. Verilog and System Verilog Gotchas 101 Common Coding Errors and How to Avoid Them: Springer Science Library of Congress Control Number: 2007926706 ISBN978-0387-71714-2 Printed on acid-free paper.e-ISBN978-0-387-71715-9 13. Logic Synthesis for Finite State Machines Based on Linear Chains of States: Alexander Barkalov, Jacek Bieganowski, and Larissa Titarenko June 24, 2017 14. Finite Element Analysis of Electrical Machines: Sheppard Joel Salon July 31, 1995

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15. Finite State Machines for Real-Time Software Engineering :Arie Avnur https://www.researchgate.net/publication/3363248_Finite_State_Machines_for_RealTime_Software_Engineering

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APPENDIX

// MEALY FINITE SATE MACHINE ALEXIOS KOTSIS MODULE ALEXIOSMEALYFSM (CLK, RESET, X, Z); INPUT CLK, RESET, X; OUTPUT REG Z; REG [1:0] PRESENTSTATE,NEXTSTATE; LOCALPARAM A=2'B00, B=2'B01,

C=2'B10, D=2'B11; ALWAYS @(PRESENTSTATE,Z)

// WE DEFINE THE NEXT STATE REQUIREMENTS // AND THE COMPUTATIONAL LOGIC CASE (PRESENTSTATE)

A: IF (X) BEGIN NEXTSTATE = B; Z = 1; END ELSE BEGIN NEXTSTATE = D; Z = 1; END

B: IF (X) BEGIN NEXTSTATE = D; Z = 1; END ELSE BEGIN NEXTSTATE = B; Z = 0; END

C: IF (X) BEGIN NEXTSTATE = D; Z = 1; END ELSE BEGIN NEXTSTATE = B; Z = 0; END

D: IF (X) BEGIN NEXTSTATE = C; Z = 1; END ELSE BEGIN NEXTSTATE

= A; Z = 0; END

ENDCASE

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ALWAYS @(NEGEDGE RESET, POSEDGE CLK) IF (!RESET) PRESENTSTATE <= A; ELSE PRESENTSTATE <= NEXTSTATE; ENDMODULE // MEALY FINITE SATE MACHINE ALEXIOS KOTSIS

`TIMESCALE 1NS/1NS MODULE ALEXIOMEALYTESTBENCH; LOGIC CLK; LOGIC RESET; LOGIC IN; LOGIC OUT;

ALEXIOSMEALYFSM DUT( .CLK(CLK), .RESET(RESET), .X(IN), .Z(OUT) ); INITIAL BEGIN RESET <= 1; #10; RESET <= 0; IN <= 0; #10; IN <= 1; #10; IN <= 1; #10; IN <= 0; #10; END ALWAYS BEGIN CLK <= 1; #5; CLK <= 0; #5; END

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//MOORE FINITE STATE MACHINE ALEXIOS KOTSIS MODULE ALEXIOSMOOREFSM(INPUT LOGIC CLK, INPUT LOGIC RESET, INPUT LOGIC X, OUTPUT LOGIC Z); TYPEDEF ENUM LOGIC [2:0] { A, B, C, D } STATE;

STATE CURRENTSTATE, NEXTSTATE; ALWAYS_FF @(POSEDGE CLK) IF(RESET) CURRENTSTATE <= A; ELSE

CURRENTSTATE <= NEXTSTATE;

ALWAYS_COMB

// WE DEFINE THE NEXT STATE LOGIC CASE(CURRENTSTATE)

A: IF(X) NEXTSTATE = B; ELSE NEXTSTATE = D;

B: IF(X) NEXTSTATE = C; ELSE NEXTSTATE = A;

C: IF(X) NEXTSTATE = C; ELSE NEXTSTATE = A; DEFAULT NEXTSTATE =A; ENDCASE ASSIGN Z = (CURRENTSTATE == C); ENDMODULE // MOORE FINITE STATE MACHINE ALEXIOS KOTSIS

// TEST BENCH ALEXIOSMOORE FSM // WE USE TIME SCALE ONE OVER 1 NSEC `TIMESCALE 1NS/1NS MODULE ALEXIOSMOORETESTBENCH; LOGIC CLK; LOGIC RESET; LOGIC IN;

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LOGIC OUT;

ALEXIOSMOOREFSM DUT( .CLK(CLK), .RESET(RESET), .X(IN), .Z(OUT) ); INITIAL BEGIN RESET <= 1; #10; RESET <= 0; IN <= 0; #10; IN <= 1; #10; IN <= 1; #10; IN <= 1; #10; END ALWAYS BEGIN CLK <= 1; #5; CLK <= 0; #5; END

ENDMODULE

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