X P L A N AT I O N : F P G A 1 0 1
VDD
Input
VDD
Output
VDD
Input
Output
a) Inverted output
b) Noninverted output Figure 1 – Typical CMOS digital output driver
you can use the back-to-back structure in Figure 1b instead. The input of the CMOS output driver is high impedance while the output is low impedance. At the input to the driver, the gates of the two CMOS transistors present high impedance, which can range from kilohms to megohms. At the output of the driver, the impedance is governed by the drain current, ID, which keeps the impedance to less than a few hundred ohms. The voltage levels for CMOS swing from approximately VDD to ground and can therefore be quite large depending on the magnitude of VDD. VDD
Some important things to consider with CMOS are the typical switching speed of the logic levels (~1 V/ns), output loading (~10 pF/gate driven) and charging currents (~10 mA/output). It is important to minimize the charging current by using the smallest capacitive load possible. In addition, a damping resistor will minimize the charging current, as illustrated in Figure 2. It is important to minimize these currents because of how quickly they can add up. For example, a quad-channel 14-bit A/D converter could have a transient current as high as 14 x 4 x 10 mA, which would be a whopping 560 mA. VDD
dV/dt = 1V/ns
R Input
Output C i = CxdV/dt
10pF
Figure 2 – CMOS output driver with transient-current and damping resistor
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Xcell Journal
The series-damping resistors will help suppress this large transient current. This technique will reduce the noise that the transients generate in the outputs, and thus help prevent the outputs from generating additional noise and distortion in the A/D converter. LVDS INTERFACE LVDS offers some nice advantages over CMOS technology for the FPGA designer. The interface has a low-voltage differential signal of approximately 350 mV peak-to-peak. The lower-voltage swing has a faster switching time and reduces EMI concerns. In addition, many of the Xilinx® FPGA families, such as the Spartan®, Virtex®, Kintex® and Artix® devices, support LVDS. Also, by virtue of being differential, LVDS offers the benefit of commonmode rejection. This means that noise coupled to the signals tends to be common to both signal paths and is mostly canceled out by the differential receiver. In LVDS, the load resistance needs to be approximately 100 Ω and is usually achieved by a parallel termination resistor at the LVDS receiver. In addition, you must route the LVDS signals using controlledimpedance transmission lines. Figure 3 shows a high-level view of a typical LVDS output driver. Third Quarter 2013