XCELLENCE IN AEROSPACE
3V3 3V3 & 1V5
Data to be checked
Data Radiation-Hardened FPGA
SRAM FPGA
Configuration Data
Payload I2C Address and Data
FPGA PROM
FPGA PROM
RAM
3V3
FPGA 3V3
5V Linear Regulator
FPGA 1V5
Linear Regulator
FPGA 1V2
Linear Regulator
FPGA 2V5
Linear Regulator
PROM 1V8
FET Switch
FPGA 3V3_Xilinx
FET Switch
3V3_PROM
Figure 1 – The EADS Astrium payload for the UKube1 mission comprises two experiments, both of which are FPGA based.
REQUIREMENTS AND CHALLENGES Designing for a CubeSat mission provides the engineers with many challenges, not least of which is the available power—there is not much of it, at 400 milliwatts on average in sunlight orbit for the UKube1. Weight restrictions come in at a shade over 300 grams for a 3U, 4.5-kg satellite. Combined with the space envelope available for a payload, these limitations present the design team with an 16
Xcell Journal
interesting set of challenges to address if they are to develop a successful payload. The engineers must also address single-event upsets (SEUs) and other radiation effects, which can affect the performance of a device in orbit regardless of the class of satellite. The power architecture in UKube1 provides regulated 3.3-, 5- and 12-volt supplies to each of the payloads. It is permissible to take up to 600 mA from each of these rails. However, the sunlitorbit average must be less than 400 mW.
Unfortunately, the voltages supplied are not at levels suitable to supply today’s high-performance space-grade FPGAs, which typically require 1.5 V or less to supply the core voltage. For example, the Virtex-4 space-grade device we selected for this mission, the XQR4VSX55 FPGA, requires a core voltage of 1.2 V along with supporting voltages of 2.5 and 3.3 V. The configuration PROMs needed to support the FPGA require 1.8 V. We selected the XQR4VSX55 because it was the largest high-performance Second Quarter 2011