Research & reviews journal of embedded system & applications (vol2, issue3)

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I take the privilege to present the hard copy compilation for the Volume 2 Issue (3) of Research & Reviews: Journal of Embedded System & Applications (RRJoESA). The intension of RRJoESA is to create an atmosphere that stimulates creativeness, research and growth in the area of Embedded System & Applications. The development and growth of the mankind is the consequence of brilliant Research done by eminent Scientists and Engineers in every field. RRJoESA provides an outlet for Research findings and reviews in areas of Embedded System & Applications. found to be relevant for National and International recent developments & research initiative. The aim and scope of the Journal is to provide an academic medium and an important reference for the advancement and dissemination of Research results that support high level learning, teaching and research in the domain of Embedded System & Applications. Finally, I express my sincere gratitude and thanks to our Editorial/ Reviewer board and Authors for their continued support and invaluable contributions and suggestions in the form of authoring writeups/ reviewing and providing constructive comments for the advancement of the journals. With regards to their due continuous support and co-operation, we have been able to publish quality Research/Reviesw findings for our customers base. I hope you will enjoy reading this issue and we welcome your feedback on any aspect of the Journal.

Dr. Archana Mehrotra Director STM Journals


Research & Reviews: Journal of Embedded System & Applications

Contents

1. FPGA and Microcontroller based Data Acquisition System using Two Wire Serial Communication Md. Maruf Ibne Hasan, Kazi Ahmed Asif Fuad, Nipu Rani Barai, Maroof Muhammad Hasan, Shahriyar Masud Rizvi

1

2. Design of a Modified Low Power PTL based 64-Bit Comparator Shilparani Panda, Manas Ranjan Jena, Snigdharani Nath

10

3. A Novel Decomposable Pixel Component Analysis Algorithm for Automating Multispectral Satellite Image Denoising Ankush Rai

18


Research & Review: Journal of Embedded System & Applications ISSN: 2321-8533 Volume 2, Issue 3 www.stmjournals.com

FPGA and Microcontroller based Data Acquisition System using Two Wire Serial Communication Md. Maruf Ibne Hasan*, Kazi Ahmed Asif Fuad, Nipu Rani Barai, Maroof Muhammad Hasan, Shahriyar Masud Rizvi Electrical and Electronic Engineering Department, American International University-Bangladesh, Dhaka, Bangladesh

Abstract Monitoring and controlling systems are common in industry safety and security systems, measurements, data logging, etc. However, these systems are generally expensive. In addition, components and electronic design automation (EDA) tools needed for advanced controlling and monitoring are not widely available in some countries. This work focuses on designing a simple and low cost Data Acquisition (DAQ) system for the purpose of monitoring and controlling with low cost microcontrollers (MCU) and field programmable gate array (FPGA) utilizing two wire serial communication. Typically, DAQ systems perform signal conditioning, data conversion, processing, multiplexing along with associated transmission, storage and displaying data. A variety of design approaches were adopted to design this system from which the single master multi slave system device architecture was chosen. Two versions of the DAQ device were implemented; one with only MCU as both master and slave device and the other with FPGA as master device and MCU as slave device.

Keywords: Data acquisition, two wire serial communication, field-programmable gate array

RRJoESA (2014)Š STM Journals 2014. All Rights Reserved


Research & Review: Journal of Embedded System & Applications ISSN: 2321-8533 Volume 2, Issue 3 www.stmjournals.com

Design of a Modified Low Power PTL based 64-Bit Comparator Shilparani Panda1, Manas Ranjan Jena2*, Snigdharani Nath1 1

Department of ETC, SIET, Dhenkanal,Odisha, India Department of ELTCE, VSSUT, Burla, Odisha, India

2

Abstract In this paper, we have presented comparison of modified and existing 64-bit binary comparator designs concentrating on power consumption, delay and PDP. Modifications are done in existing 64-bit binary comparator design to improve the PDP of the proposed design. The modified design have been performed by using PTL logic in existing 64-bit binary comparator design to improve the speed of the circuit. Comparison between modified and existing 64-bit binary comparator designs is calculated by simulation that is performed at 180 nm technology in Tanner EDA Tool.

Keywords: Binary comparator, digital arithmetic, power delay product, PTL, power, area

RRJoESA (2014)Š STM Journals 2014. All Rights Reserved


Research & Review: Journal of Embedded System & Applications ISSN: 2321-8533 (online) Volume 2, Issue 3 www.stmjournals.com

A Novel Decomposable Pixel Component Analysis Algorithm for Automating Multispectral Satellite Image Denoising Ankush Rai* CRIAD Laboratories, Department of Applied Science, Smiriti Nagar, India Abstract In comparison with the standard RGB or gray-scale images the usual multispectral images (MSI) is intended to convey high definition and an authentic representation for real world scenes to significantly enhance the performance measures of several other tasks involving with computer vision, segmentation of image, object extraction and object tagging operations. However, in practices a MSI image is always prone to corruption by various sources of noises while procuring the images. In this paper we propose a methodology which effectively denoised the MSI images through a novel Decomposable Pixel Component Analysis Algorithm. The proposed algorithm uses two essential properties of a MSI image to its advantage, i.e., the dissimilarity of nonlocal space and the global illumination of the correlated regions across wide spectrum; to consider the correlation between non-variant local sub-spaces within the given noise influenced MSI image. The spatial regularity of neighboring pixels within the image is maintained while the block's homogeneity is checked to extract the decomposable pixels which latter is replaced by neighboring full band patches.

Keywords: Multi spectral image denoising, spatial regularity, satellite imagery, noise removal

RRJoESA (2014)Š STM Journals 2014. All Rights Reserved


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