System Development
Zero to FPGA in Minutes
32 GPIO In-Out 32
GPIO In-Out
45-bric Array
GPIO In-Out
32
DDR2 400
32
336 32-bit Processors: 32
DDR2 400
168 Streaming RISC 168 Streaming RISC with DSP Extensions +8 16-bit micro-engine accelerators. 1 teraOPS, 50 GMACS, 202 GSADS @ 300 MHz 7.1 Mbits Distribued SRAM
Serial Flash JTAG
Figure 2
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[ 40 ] COTS Journal April 2008 Untitled-4 1
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Host CPU I/F
PCI Express 4 lanes
8
GPIO In-Out 32
Ambric’s Am2045 is a standard-cell 130 nanometer ASIC. Shown here are the external interfaces, including external SDRAM interfaces, a PCIe interface and four general-purpose I/O (GPIO) ports. FPGAs are a step down from ASICs in performance and a step up in ease of use. Because they rely on reprogrammable logic, FPGAs are inherently less siliconefficient than ASICs but offer more flexibility because they are programmable. FPGAs are programmed at the RegisterTransfer-Level (RTL), applying very basic operations such as Boolean equations and control logic to registers, in languages such as Verilog or VHDL. Programmable I/O and a large number of pins make FPGAs well suited for interfacing devices. High-end DSPs are at the opposite end of the spectrum from ASICs. DSPs are processors programmed in a mixture of a high-level language and assembly language, a trait that is appealing to software developers. Most DSPs include hardware multipliers for efficient multiply and multiply-accumulate operations. They support two memory accesses per cycle to more efficiently run algorithms such as filters, which operate on two arrays at once. Programming complexity is a major challenge with FPGAs. Writing code for an FPGA requires two distinct sets of skills, of which few people possess both: good knowledge of hardware constraints, such as timing closure and gate-level cod-
ing, and the good software programming skills and DSP theory knowledge needed to efficiently implement complex algorithms. Another problem with FPGAs is the complexity involved in creating a correct design. FPGA designs of average complexity often take hours to place and route. This significantly impedes code development and validation. This increased programming complexity results in longer development times or in designs that do not efficiently use the available logic.
DSP Programing Advantages The strength of DSPs is their ease of programming: software developers code entire applications in a mix of high-level and assembly languages, a key advantage compared with using RTL. High-end DSPs have an increased pipeline and are packed with specialized hardware. This requires programmers to handcraft code, such as instruction rescheduling and loop unrolling, to use these features to achieve the desired performance. The complexity of DSP programming has increased exponentially with the recent introduction of multicore DSPs. In these devices, several identical DSP-oriented cores are connected to share mem-