System Development
Hardware Feature
Capability
Microprocessor
Available PowerPC processors with inherent radiation-tolerant capabilities provide superior performance and low power consumption for space applications. ECC and parity-protected on-die L1 and L2 cache to provide mitigation to Single Event Effects.
Volatile Memory
SDRAM arranged in a triple-redundant configuration with zero-wait state when executing CPU memory read or write requests.
Non-Volatile Boot Memory
Dual-redundant boot memory to minimize any single-point failure when a system starts up or it is being reset.
Non-Volatile User Memory
ECC-corrected user flash memory provides real-time correction and detection to data corrupted by Single Event Effects.
Data Buffers
Triple voting takes place on a memory buffer when a read request is made to a specific input or output data buffer in order to minimize bit flips rooted in any Single Event Upset event.
Redundant Channels
Each mission-critical data channel can be designed to provide redundant data paths with anti-fuse FPGA implementations.
I/O Expansion
Conduction-cooled PCI Mezzanine Card (ccPMC) slot on the processor module or on an alternate carrier card delivers flexible and modular I/O expansion and increases density of additional functions.
Bus Interface
Incorporating a standard bus interface ensures capabilities for additional redundancy and for integrating signals from outside the enclosure, including future capability enhancements through backward and forward technology insertion.
closure. A customer typically procures most of the modules required for a specific spacecraft avionics solution, then develops one or two custom I/O cards with the same bus interface to provide unique or proprietary capabilities not offered otherwise. Open architecture helps minimize this time-consuming and costly effort. Other benefits include using spaceproven hardware, further reducing costs associated with continually re-inventing and re-architecting the spacecraft mission computer. Time-to-market and the pressures of platform qualification prior to launch decrease. Typical features in a cPCI system solution could include: • A PowerPC processor module as the system controller; • Redundant processor modules or additional modules for increasing performance and reliability; • Coordinated reset signals on a cPCI backplane; • A backplane with no wire harness, increasing reliability in launch conditions or hypersonic cruising environments; • A custom reset to allow each individual processor module to reset itself or the whole cPCI backplane bus and; • Local and cPCI bridges on processor modules to separate high-speed traffic and increase overall system throughput.
Table 2
Embedded modules and their associated capabilities. more complex as well as redundant or coordinated mission operations. To achieve rapid and cost-effective space system integration with the “plug-and-play” methodology, there are three key elements to consider: a widely accepted open bus architecture (such as CompactPCI), a radiation-tolerant FPGA implementation of bus interface and the use of a common enclosure design. A mature and well-defined open architecture, a primary element in achieving a modular, flexible space system, allows the modules to seamlessly operate together with a common protocol and [ 46 ] COTS Journal August 2007
a physical bus interface. In contemporary spacecraft design, some popular open architectures include VMEbus and CompactPCI (cPCI). In particular, CompactPCI has recently gained significant notoriety due to the small, rugged form-factor of modules, plenty of available user-defined backplane I/O pins and the extensive knowledge base across various industries such as telecom, military and space applications. The use of open architecture also permits various parties to develop modules that can work together properly in a single bus interface within the same en-
FPGA Implementation To enable a flexible architecture for space applications, the common bus interface must be implemented in a radiation-tolerant silicon solution. In the case of cPCI, radiation-hardened FPGAs can be used for this implementation on each module to communicate across a cPCI bus. In addition to offering a bus interface, the same FPGA can also control operations for onboard interfaces to minimize real-time interactions or relax timing constraints from software to complete specific tasks. An example of such a design is an analog I/O card. As shown in Figure 2, the front-end of the FPGA implemented on the card is a cPCI interface. The