module MLD_s3(clk,reset,x15_s3,x); input clk; input reset; input [31:0] x15_s3; output x;
wire [2:0] sum0_0, sum0_1, sum0_2, sum0_3, sum0_4, sum0_5, sum0_6, sum0_7; wire [3:0] sum1_0, sum1_1, sum1_2, sum1_3; //wire [11:0] sum1; wire [4:0] sum2_0, sum2_1;
wire [5:0] sum;
//reg x;
assign sum0_0 = x15_s3[31] + x15_s3[30] + x15_s3[29] + x15_s3[28]; assign sum0_1 = x15_s3[27] + x15_s3[26] + x15_s3[25] + x15_s3[24]; assign sum0_2 = x15_s3[23] + x15_s3[22] + x15_s3[21] + x15_s3[20]; assign sum0_3 = x15_s3[19] + x15_s3[18] + x15_s3[17] + x15_s3[16]; assign sum0_4 = x15_s3[15] + x15_s3[14] + x15_s3[13] + x15_s3[12]; assign sum0_5 = x15_s3[11] + x15_s3[10] + x15_s3[9] + x15_s3[8]; assign sum0_6 = x15_s3[7] + x15_s3[6] + x15_s3[5] + x15_s3[4]; assign sum0_7 = x15_s3[3] + x15_s3[2] + x15_s3[1] + x15_s3[0];
assign sum1_0 = sum0_0 + sum0_1; assign sum1_1 = sum0_2 + sum0_3; assign sum1_2 = sum0_4 + sum0_5; assign sum1_3 = sum0_6 + sum0_7;