IC Data Sheets 8.7
Q548.1E LA
8.
EN 55
Diagram SSB: Class-D B06A, TPA3123D (IC 7L10)
Block Diagram 1 F
0.22 F LIN
BSR
RIN
ROUT
1 F
22 H 0.68 F
PGNDR
0.68 F
PGNDL
1 F
470 F
LOUT
BYPASS AGND
22 H
BSL
470 F
0.22 F
PVCCL
AVCC
PVCCR
VCLAMP Shutdown Control
SD
1 F
MUTE
}
GAIN0 GAIN1
Control
Pin Configuration PVCCL SD PVCCL MUTE LIN RIN BYPASS AGND AGND PVCCR VCLAMP PVCCR
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
PGNDL PGNDL LOUT BSL AVCC AVCC GAIN0 GAIN1 BSR ROUT PGNDR PGNDR
TERMINAL 24-PIN (PWP)
I/O/P
DESCRIPTION
SD
2
I
Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance to AVCC
RIN
6
I
Audio input for right channel
LIN
5
I
Audio input for left channel
GAIN0
18
I
Gain select least-significant bit. TTL logic levels with compliance to AVCC
GAIN1
17
I
Gain select most-significant bit. TTL logic levels with compliance to AVCC
MUTE
4
I
Mute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle, low = outputs enabled). TTL logic levels with compliance to AVCC
BSL
21
I/O
PVCCL
1, 3
P
LOUT
22
O
Class-D 1/2-H-bridge positive output for left channel
23, 24
P
Power ground for left-channel H-bridge
NAME
PGNDL
Bootstrap I/O for left channel Power supply for left-channel H-bridge, not internally connected to PVCCR or AVCC
VCLAMP
11
P
BSR
16
I/O
Bootstrap I/O for right channel
ROUT
Internally generated voltage supply for bootstrap capacitors
15
O
Class-D 1/2-H-bridge negative output for right channel
PGNDR
13, 14
P
Power ground for right-channel H-bridge.
PVCCR
10, 12
P
Power supply for right-channel H-bridge, not connected to PVCCL or AVCC
AGND
9
P
Analog ground for digital/analog cells in core
AGND
8
P
Analog ground for analog cells in core
BYPASS
7
O
Reference for preamplifier inputs. Nominally equal to AVCC/8. Also controls start-up time via external capacitor sizing.
AVCC Thermal pad
19, 20
P
High-voltage analog power supply. Not internally connected to PVCCR or PVCCL
Die pad
P
Connect to ground. Thermal pad should be soldered down on all applications to properly secure device to printed wiring board.
18440_302_090303.eps 090303
Figure 8-7 Internal block diagram and pin configuration 2009-Apr-03