1377 file wrapper by Mark Boys

PART B- FEE(S) TRANSMITTAL ·~

3 'n\US

Mail Stop Iss&E Commissioner for Patents P.O. Box 1450 Alexandria, Virginia 22313-1450 (703) 746-4000

form, together .applicable fee(s), to: Mail

1.1:'

(CL __ r-

C"'

6--.)

or EilX

!:'

should be used for transmitting the ISSUE FEE and PUBLICATION FEE (if required). Blocks I through 5 should be completed wh appropn ' '/':, 1 furthe spondence including the Patent, advance orders and notification of maintenance fees will be mailed to the current lcorrespondence address ~~ elow or directed otherwise in Block 1, by (a) specifying a new correspondence address; and/or (b) indicating a sep:trate "FEE ADDRESS" indicated maintenance ee utiflcations. Note: A certificate of mailing can only be used for domestic mailings of Fee(s) TransmittaL This certificate cannot be used for any other accompany papers. Each additional paper, such as an assignment or formal drawing, m have its own certificate of mailing or transmissiOn. 7590 OU04/2005 24739

CENTRAL COAST PATENT AGENCY

Certificate of Mailing or Transmission I hereby certify that this Fee(s) Transmittal is being deposited with the Un States Postal Service with sufficient postage for first class mail in an envel addressed to the Mail Stop ISSUE FEE address above, or being facsim transmitted to the USPTO 703 746-4000, on the date indicated below.

PO BOX 187 AROMAS, CA 95004

(DepOiiito~s

01/19/2005 KBETEKA2 00000017 10390194 01 FC:2501 700.00 OP 02 FC:1504 300.00

(Signat (D

APPLICATION NO.

FILING DATE

FIRST NAMED INVENTOR

10/390,194

03/1412003

Ajay Janami Daga

CONFIRMATION NO.

Pl377

3209

TITLE OF INVENTION: AUTOMATED APPROACH TO CONSTRATh.'T GENERATION IN IC DESIGN

APPLN. TYPE

SMALL ENTITY

ISSUE FEE

PUBLICATION FEE

TOTAL FEE(S) DUE

DATE DUE

nonprovisional

YES

$700

$300

$1000

04/04/2005

EXAMINER

ART UNIT

CLASS-SUBCLASS

LIN, SUN J

2825

716-001000

I. Chanl!.e of correspondence address or indication of "Fee Address" (3 7 CFR Lf63). 0 Change of corresJlondence address (or Change of Correspondence Address form PTO/SB/122) attached.

2. For printing on the patent front page, list (I) the names of up to 3 registered patent attorneys or agents OR, alternatively, (2) the name of a single fum (having as a member a registered attorney or agent) and the names of up to 2 registered patent attorneys or agents. If no name is listed, no name will be printed.

0 "Fee Addres~" indication (or "Fee Address" Indication form • PTO/SB/47; Rev 03-02 or more recent) attached. Use of a Customer · - Number is required.

\ASSIGNEE NAME AND RESIDENCE DATA TO BE PRINTED ON THE PATENT (print or type) PLEASE NOTE: Unless an assignee is identified below, no assignee data will appear on the patent. If an assignee is identified below, the doCument has been filed recordation as set forth in 37 CFR 3.1 L Completion of this form is NOT a substitute for filing an assignment. (A) NAME OF ASSIGNEE

(B) RESIDENCE: (CITY and STATE OR COUNTRY)

F/ shfa-,· I Des;1// AIL.f~maf;~/} Irt~. Please check the appropriate assignee category or categories (will not be printed on the patent) : 4a The following fee(s) are enclosed:

~ue Fee

~ication Fee (No small entity discount permitted) 0 Advance Order- # of Copies 5. Change in Entity Status (from status indicated above) 0 a. Applicant claims SMALL ENTITY status. See 37 CFR 1.27.

J_~05v..>e.jD) Individual

D {{..

~oration or other private group entity 0

Govemm

4b. Payment ofFee(s):

13-A: checiZ in the amount of the fee( s) is enclosed. 0 Payment by credit card. Form PT0-2038 is attached. ld-rhe' Director is hereby authorized b c e the required fee(s), or credit any ovell'ayment Deposit Account Number

(enclose an extra copy of this form).

b. Applicant is no longer claiming SMALL ENTITY status. See 37 CFR L27(g)(2).

The Director of the USPTO is requested to apply the Issue Fee and Publication Fee (if any) or to re-apply any previously paid issue fee to the application identified above. NOTE: The Issue Fee and Publication Fee (if required) will not be accepted from anyone other than the applicant; a regtstered attorney or agent; or the assignee or other part ·ted States ent and rademark Office. interest as shown by the records of the

Typed or printed name

__Jbo.a.a~rJL..!..!!t>-=...l...!od~_._R~-_"?:2~~0~'1q....5.L_____

This collection of information is required by 3 7 CFR 1.311. The information is required to obtain or retain a benefit by the public which is to file (and by the USPTO to proc an appl\cation. Confidentiality_is governed by 35 U.S.C. 122_and 3? CFR 1.14. TIJ,is collection \s e~t\mated to take 1~ minutes to complete, includi_ng gathering,_preparmg, submitting the completed applicatiOn form to the USPTO. Time Will vary depending upon the mdivJdual case. Any co=ents on the amount of time you reg_urre to comp this form and/or suggestions for reducing this burden, should be sent to the Chief Information Officer, U.S. Patent and Trademark Office, U.S. Department of Co=erce, 1> Box 1450, Alexandria, Virginia 22313-1'150. DO NOT SEND FEES OR COMPLETED FORMS TO THIS ADDRESS. SEND TO: Commissioner for Patents, P.O. Box 14 Alexandria, Virginia 22313-1450. Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it displays a valid OMB control number.

PTOL 85 (Rev 12/04) Approved for use through 04/30/2007

OMB 0651 0033

US Patent and Trademark Office; US DEPARTMENT OF COMMER

Certificate of Express Mailing

"Express Mail" Mailing Label Number: EV584080300US Date of Deposit: 01/13/2005 Ref: Case Docket No.: P1377 Application of: Ajay Janami Daga Serial Number: 10/390,194 Filing Date: 03/14/2003 Title of Case: Automated Approach to Constraint Generation in IC Design

I hereby certify that the attached papers are being deposited with the United States Postal Service "Express Mail Post Office to Addressee" service under 37 C.F.R. 1.10 on the date indicated above and addressed to the Commissioner for Patents, Alexandria, VA 22313-1450.

C.,

1. 2. 3. 4.

Part B of issue fee transmittal. Check for fees in the amount of$1000.00 ($700/Issue fee and $300/Pub. fee). Certificate of express mailing. Postcard listing contents.

Mark A. Boys

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Offi(e Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria. Virginia 22313-1450 www.usptn.go\'

NOTICE OF ALLOWANCE AND FEE(S) DUE 24739

7590

EXAMINER

Ol/0412005

CENTRAL COAST PATENT AGENCY

LIN,SUNJ

PO BOX 187 AROMAS, CA 95004

ART UNIT

PAPER NUMBER

2825

DATE MAILED: 0 1/04/2005

APPLICATION NO.

FILING DATE

FIRST NAMED INVENTOR

ATTORNEY DOCKET NO.

CONFIRMATION NO.

10/390,194

03/14/2003

Ajay Janami Daga

Pl377

3209

TITLE OF INVENTION: AUTOMATED APPROACH TO CONSTRAINT GENERATION IN IC DESIGN

APPLN. TYPE

SMALL ENTITY

ISSUE FEE

PUBLICATION FEE

TOTAL FEE(S) DUE

DATE DUE

nonprovisional

YES

$700

$300

$1000

04/04/2005

THE APPLICATION IDENTIFIED ABOVE HAS BEEN EXAMINED AND IS ALLOWED FOR ISSUANCE AS A PATEN PROSECUTION .QN IHE MERITS IS CLOSED. TIDS NOTICE OF ALLOWANCE IS NOT A GRANT OF PATENT RIGHT TIDS APPLICATION IS SUBJECT TO WITHDRAWAL FROM ISSUE AT THE INITIATIVE OF THE OFFICE OR UPO PETITION BY THE APPLICANT. SEE 37 CFR 1.313 AND MPEP 1308. THE ISSUE FEE AND PUBLICATION FEE (IF REQUIRED) MUST BE PAID WITIDN THREE MONTHS FROM TH MAILING DATE OF TIDS NOTICE OR TIDS APPLICATION SHALL BE REGARDED AS ABANDONED. .IH._ STATUTORY PERIOD CANNOT BE EXTENDED. SEE 35 U.S.C. 151. THE ISSUE FEE DUE INDICATED ABOV REFLECTS A CREDIT FOR ANY PREVIOUSLY PAID ISSUE FEE APPLIED IN TIDS APPLICATION. THE PTOL-85B (0 AN EQUIVALENT) MUST BE RETURNED WITIDN TIDS PERIOD EVEN IF NO FEE IS DUE OR THE APPLICATION WIL BE REGARDED AS ABANDONED. HOW TO REPLY TO TIDS NOTICE: I. Review the SMALL ENTITY status shown above. If the SMALL ENTITY is shown as YES, verify your current SMALL ENTITY status:

If the SMALL ENTITY is shown as NO:

A. If the status is the same, pay the TOTAL FEE(S) DUE shown above.

A. Pay TOTAL FEE(S) DUE shown above, or

B. If the status above is to be removed, check box 5b on Part B Fee(s) Transmittal and pay the PUBLICATION FEE (if required} and twice the amount of the ISSUE FEE shown above, or

B. If applicant claimed SMALL ENTITY status before, or is n claiming SMALL ENTITY status, check box 5a on Part B- Fee Transmittal and pay the PUBLICATION FEE (if required) and I the ISSUE FEE shown above.

II. PART B- FEE(S) TRANSMITTAL should be completed and returned to the United States Patent and Trademark Office (USPTO) w your ISSUE FEE and PUBLICATION FEE (if required). Even if the fee(s) have already been paid, Part B - Fee(s) Transmittal should completed and returned. If you are charging the fee(s) to your deposit account, section "4b" of Part B - Fee(s) Transmittal should completed and an extra copy of the form should be submitted. III. All communications regarding this application must give the application number. Please direct all communications prior to issuance Mail Stop ISSUE FEE unless advised to the contrary.

IMPORTANT REMINDER: Utility patents issuing on applications filed on or after Dec. 12, 1980 may require payment maintenance fees. It is patentee's responsibility to ensure timely payment of maintenance fees when due. Page 1 of 3 PTOL 85 (Rev 12/04) Approved for use through 04/30/2007

PART B- FEE(S) TRANSMITTAL Complete and send this form, together with applicable fee(s), to: Mail

Mail Stop ISSUE FEE Commissioner for Patents P.O. Box 1450 Alexandria, Virginia 22313-1450 (703) 746-4000

or fix

INSTRUCTIONS: This form should be used for transmitting the ISSUE FEE and PUBLICATION FEE (if required). Blocks I through 5 should be completed wh !IJlpropriate. All further corresponden~ including tb,e P!Uent. advance orders ll!ld. notification of maintenance fees will be maile_d (? tb,e current co~ondence addre~.s mdicated unless corrected below or directed otherwiSe m Block I, by (a) spec1fying a new correspondence address; and/or (b) mdicatmg a separate "FEE ADDRESS maintenance fee notifications. CURRENT COAAESPONDENCE 1\DDRESS (Note: Use Block I for any ehange of ad~..) Note: A certificate of mailing can only be used for domestic mailings of Fee(s) Transmittal. This certificate cannot be used for any other accompany papers. Each additional paper, such as an assignment or formal drawing, m have its own certificate of mailing or transmission. OU0412005 24739 7590

CENTRAL COAST PATENT AGENCY

Certificate of Mailing or Transmission I hereby certify that this Fee(s) Transmittal is being deposited with the Un States Postal Service with sufficient postage for firSt clilss mail in an envei addressed to the Mail S~ ISSUE FEn address above, or be~ facsim OW. transmitted to the USPTO 03) 746-4000, on the date indicated

PO BOX 187 AROMAS, CA 95004

(Dep06ito~â&#x20AC;˘

(Signal

APPLICATION NO.

FILING DATE

10/390,194

FIRST NAMED INVENTOR

I ATTORNEY DOCKET NO. I

CONFIRMATION NO.

Ajay Janami Daga

PJ377

3209

03114/2003

TITLE OF INVENTION: AUTOMATED APPROACH TO CONSTRAINT GENERATION IN IC DESIGN

SMALL ENTITY

ISSUE FEE

PUBLICATION FEE

TOTAL FEE(S) DUE

DATE DUE

YES

$700

$300

$1000

04/04/2005

EXAMINER

ART UNIT

CLASS-SUBCLASS

LIN, SUN 1

2825

7I6-00IOOO

APPLN.TYPE nonprovisional

I. Change of correspondence address or indication of "Fee Address" (37 CFR I.363). 0 Change of correspondence address (or Change of Correspondence Address form PTO/SB/I22) attached.

2. For printing on the patent front page, list (I) the names of up to 3 registered patent attorneys or agents OR, alternatively, (2) the name of a single firm (having as a member a registered attorney or agent) and the names of up to 2 registered patent attorneys or agents. If no name is listeQ, no name will be printed.

"Fee Address" indication (or "Fee Address" Indication form PTO/SB/4 7; Rev 03-02 or more recent) attached. Use of a Customer Number is required.

2._ _ _ _ _ _ _ _ _ _ _ __ 3 -------------

3. ASSIGNEE NAME AND RESIDENCE DATA TO BE PRINTED ON THE PATENT (print or type) PLEASE NOTE: Unless an assignee is identified below, no assignee data will appear on the patent. If an assignee is identified below, the document has been filed recordation as set forth in 37 CFR 3.11. Completion of this form is NOT a substitute for filing an assignment. (A) NAME OF ASSIGNEE

(B) RESIDENCE: (CITY and STATE OR COUNTRY)

Please check the appropriate assignee category or categories (will not be printed on the patent) : 4a The following fee(s) are enclosed:

0 0

Issue Fee

Advance Order- #of Copies

Publication Fee (No small entity discount permitted)

Individual

Corporation or other private group entity

Governm

4b. Payment ofFee(s):

0 0

A check in the amount of the fee(s) is enclosed. Payment by credit card. Form PT0-2038 is attached.

0 The Director is hereby authorized by charge the required fee(s), or credit any ovel'J?ayment Deposit Account Number (enclose an extra copy of this form).

5. Change in Entity Status (from status indicated above)

a. Applicant claims SMALL ENTITY status. See 37 CFR 1.27.

b. Applicant is no longer claiming SMALL ENTITY status. See 37 CFR 1.27(g)(2).

The Director of the USPTO is requested to apply the Issue Fee and Publication Fee (if any) or to re-apply any previously paid issue fee to the application identified above. NOTE: The Issue Fee and Publication Fee (if required) will not be accepted from anyone other than the apphcant; a regrstered attorney or agent; or the assignee or other part interest as shown by the records of the United States Patent and Trademark Office. Authorized S i g n a t u r e - - - - - - - - - - - - - - - - - - - - - Typed or printed n a m e - - - - - - - - - - - - - - - - - - - - -

Date _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ Registration N o . - - - - - - - - - - - - - -

This collection of information is required by 3 7 CFR I.3II. The information is required to obtain or retain a benefit by the public which is to file (and by the USPTO to l'roc an application. Confidentiality is governed by 35 U.S.C. I22 and 37 CFR 1.14. This collection is estimated to take 12 minutes to complete, including gathering, preparmg, submrtting the completed applicatiOn form to the USPTO. Time will vary depending upon the individual case. Any co=ents on the amount of time you require to comp this form and/or suggestions for reducing this burden, should be sent to the Chief Information Officer, U.S. Patent and Trademark Office, U.S. Department ofCo=erce, 1> Box I450, Alexandria, Virginia 22313-1450. DO NOT SEND FEES OR COMPLETED FORMS TO THIS ADDRESS. SEND TO: Commissioner for Patents, P.O. Box 14 Alexandria, Virginia 223I3-1450. Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it displays a valid OMB control number.

PTOL 85 (Rev I2/04) Approved for use through 04/30/2007

OMB 065I 0033

US Patent and Trademark Office; US DEPARTMENT OF COMMER

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTME.NT OF COMMERCE United States Patent and Trademark. Office Add=<: COMMISSIONER FOR PATENTS P.O. Box 1450 1\leundria, Vuginia 22313-1450

www.usptt>.gov

APPLICATION NO.

FILING DATE

FIRST NAMED INVENTOR

ATTORNEY DOCKET NO.

CONFIRMATION NO.

10/390,194

03/14noo3

A jay Janami Daga

P1377

3209

24739

7590

EXAMINER

01/04/2005

CENTRAL COAST PATENT AGENCY

LIN,SUNJ

PO BOX 187 AROMAS, CA 95004

ART UNIT

PAPER NUMBER

2825

DATE MAILED: 01/04/2005

Determination of Patent Term Adjustment under 35 U.S.C. 154 (b) (application filed on or after May 29, 2000) The Patent Term Adjustment to date is 102 day(s). If the issue fee is paid on the date that is three months after t mailing date of this notice and the patent issues on the Tuesday before the date that is 28 weeks (six and a h months) after the mailing date of this notice, the Patent Term Adjustment will be 102 day(s). If a Continued Prosecution Application (CPA) was filed in the above-identified application, the filing date th determines Patent Term Adjustment is the filing date ofthe most recent CPA. Applicant will be able to obtain more detailed information by accessing the Patent Application Information Retriev (PAIR) WEB site (http://pair.uspto.gov). Any questions regarding the Patent Term Extension or Adjustment determination should be directed to the Office Patent Legal Administration at (571) 272-7702. Questions relating to issue and publication fee payments should directed to the Customer Service Center ofthe Office P~t~nt P_ubli_c~ti~n_at (703) 30~-~283. _ _ __

Page 3 of 3 PTOL 85 (Rev 12/04) Approved for use through 04/30/2007

Notice of Allowability

Application No.

Applicant(s)

10/390,194 Examiner

DAGA, AJAY JANAMI Art Unit

Sun J Un

2825

-- The MAILING DATE of this communication appears on the cover sheet with the correspondence address-All daims being allowable, PROSECUTION ON THE MERITS IS (OR REMAINS) CLOSED in this application. If not included herewith (or previously mailed), a Notice of Allowance (PTOL-85) or other appropriate communication will be mailed in due course. THIS NOTICE OF ALLOWABILITY IS NOT A GRANT OF PATENT RIGHTS. This application is subject to withdrawal from issue at the initiative of the Office or upon petition by the applicant. See 37 CFR 1.313 and MPEP 1308. 1. [gl This communication is responsive to Amendment & Remarks filed on 1111712004. 2. [gl The 路allowed claim(s) is/are 1.3-13 and 15-24. renumbered (37CFR 1.126!. 3.

[gJ

The drawings filed on 03/1412003 are accepted by the Examiner.

Acknowledgment is made of a claim for foreign priority under 35 U.S. C.搂 119(a)-(d) or (f). a)

b) D Some*

All

D 2. D 3. D 1.

c) D None

of the:

Certified copies of the priority documents have been received. Certified copies of the priority documents have been received in Application No. _ _ . Copies of the certified copies of the priority documents have been received in this national stage application from the International Bureau (PCT Rule 17.2(a)).

*Certified copies not received: _ _ . Applicant has THREE MONTHS FROM THE "MAILING DATE" of this communication to file a reply complying with the requirements noted below. Failure to timely comply will result in ABANDONMENT of this application. THIS THREE-MONTH PERIOD IS NOT EXTENDABLE. 5.

A SUBSTITUTE OATH OR DECLARATION must be submitted. Note the attached EXAMINER'S AMENDMENT or NOTICE OF INFORMAL PATENT APPLICATION (PT0-152) which gives reason(s) why the oath or declaration is deficient.

CORRECTED DRAWINGS ( as "replacement sheets") must be submitted.

(a) D including changes required by the Notice of Draftsperson's Patent Drawing Review ( PT0-948) attached 1) D hereto or 2) D to Paper No./Mail Date _ _ . (b) D including changes required by the attached Examiner's Amendment I Comment or in the Office action of Paper No./Mail Date _ _ . Identifying indicia such as the application number (see 37 CFR 1.84(c)) should be written on the drawings in the front (not the back) of -~AcJ!.sJ!e.!!:_~~lac..!!!!._ent sheet{&) should be labeled as such in the header according to 37 CFR 1.121(d).

- --

--------~---

--...-

- ----

-----~ ........

----------- ---- --

DEPOSIT OF and/or INFORMATION about the deposit of BIOLOGICAL MATERIAL must be submitted. Note the attached Examiner's comment regarding REQUIREMENT FOR THE DEPOSIT OF BIOLOGICAL MATERIAL.

Attachment( s) 1. D Notice of References Cited (PT0-892) 2.

Notice of Draftperson's Patent Drawing Review (PT0-948)

D D

Information Disclosure Statements (PT0-1449 or PTO/SB/08), Paper No./Mail Date _ _ Examiner's Comment Regarding Requirement for Deposit

D D

of Biological Material

Notice of Informal Patent Application (PT0-152) Interview Summary (PT0-413), Paper No./Mail Date _ _ . Examiner's AmendmenVComment Examiner's Statement of Reasons for Allowance Other

U.S. Patent ard Trademar1< Office

PTOL-37 (Rev. 1-04)

Notice of Allowability

Part of Paper No./Mail Date 1221200

路

---~--

Applicant(s)

Application No.

Issue Classification

Ill II~ Ill

II II II I

10/390,194

DAGA, AJAY JANAMI

Examiner

Art Unit

Sun J Lin

2825

in the same order as iii r:::

I DCPA

1 1

:::,

.!:

II·] Hlllll iii u:

(§

111Ti 1::::::.

1// 1

~~T\:§1 u.

R1.47

iii

....

l-...:...111~...:..::...._12_r:::::::::::I--+-....:..=.._42F::::::::::I--+-...:....=....72LL'::'''::'''::''::':I--+-1.:...::10.=2.....r;. ::::::: _12

13_

1s 16 17

11 18 19

47 48 49

78 79

103 •

~==:=:= . . . 1-----f-~i-'--l: :- +- =- =-~;E.=. . . t= •.= . .

~! ~~

I I

H H

101 1o8 109

,,,. ·

r :

129 ·• · ···

159

132 133

162l H

163~

132 1

~E1 '~==:~~~~

~E 137 1381 139 IT

189

167 168 169

_1 ~ 199

7•

I 1

U.S. Patent and Trademark Office

Part of Paper No. 12212004

IIIIIIIIIIIIIIIW I ..J

Rejected

= Allowed Claim "iii c:

"iii c: 'ii> ·c:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

23 24 25 26 27 28 29

· · -3o··

DAGA, AJAY JANAMI Art Unit

Sun J Lin

2825

Restricted

Date

Claim

"iii c:

c;:;

i'l

N Non-Elected

Appeal

Objected

Interference

Date

Claim

"iii c: 'ii> ·c:

"iii c:

51 52 53 54

55 56 57 58 59 60 61 62 63

I I

1 1~ 1

= = = = =

1:::1

II II JU

= = = =

•·.

10/390,194 Examiner

(Through numeral) Cancelled

= = = = = = = = = = = = =

Applicant(s)

Application No.

Index of Claims

.. .. - ..

II II

31 32 33 34 35 36 37 38 39 40 41 42 43

65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 -~80.

II -.

81 82 83 84

85 86 87 88 89 90 91 92 93

45 46 47 48 49 50

95 96 97 98 99 100

U.S. Patent and Trademark Office

II IHI

HI IHI

1 1 1:~ Ll

Date

"iii c: 'ii>

(5 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Part of Paper No. 12212004

1111111111111

Ill II I

10/390,194

DAGA, AJAY JANAMI

Examiner

Art Unit

Sun J Lin

2825

SEARCH NOTES (INCLUDING SEARCH STRATEGY)

SEARCHED Class

Subclass

Date

Examiner

716

12/21/2004

JSL

716

Applicant(s)

Application No.

路search Notes

DATE

EXMR

EAST [USPAT;USPGPUB;UPO;JPO;DERWENT;IBM_T DB]

12/21/2004

JSL

IEEE

12/21/2004

JSL

12/21/2004

GOOGLE

JSL

....._..

_____

INTERFERENCE SEARCHED Class

Subclass

Date

Examiner

716

12/21/2004

JSL

716

12/21/2004

JSL

U.S. Patent and Trademark Office

Part of Paper No. 12212004

.:..

Application or Docket Number

PATENT APPUCATION FEE DETERMINATION RECORD. · Effective January 1, 2003 CLAIMS AS FILED - PART I

p 131/

SMALL ENTITY TYPE c::::J

TOTAL CLAIMS

RATE BASIC FEE

FOR TOTAL CHARGEABLE ClAIMS

MULTIPLE DEPENDENT CLAIM PRESENT

·o

* If the difference in column 1 is less than zero, enter ·od in column 2

FEE

375.00 0

X$9=

X$18=

X42=

X84=

+140=

+280;;

TOTAL

OR TOTAL

SMALL ENTITY

CLAIMS AS AMENDED • PART II PRESENT EXTRA

RATE

ADD ITIONAL ·FEE

OTHER THAN SMALL ENTITY RATE

X$9=

X$18=

.X42=

X84=

+140=

+280=

TOTAL ADDIT.FEE

PRESENT. EXTRA

OTHER THAN SMALL ENTilY

RATE

ADDI· TIONAL

OR ADDIT. ADDI· TIONAL FEE

RATE

X$-9=

X$18=

X42=

X84=

+140=

+280=

ADDITIONAL

TOTAL ADDIT. FEE

PRESENT ·EXTRA

RATE

X$9=

X$18=

X42=

X84=

+140=

.+280=

TOTAL ADDIT. FEE

12/02)

ADDI· TIONAL FEE

ADDI-. TIONAL

..,

11111.

IOIIIm

·:.

·... ';..

OIIID

'l f)

·~

~·

.'... ..

II:" I

7.C 76

1251

.· :

12 IS

IH · 19 10

·-..:

•

IW ~2£

~3J 8

8 8

_,_......

,.... 91 ·' 92

1--c

<16

~ .. l J

MOe. I

1-·

.:...:.-- 1- 1 - 1-1-

,.:....-1 - r I-I..-'-I ,;-

_1.

1-1-:-

114!

,_ .c-1-1-1-

~sc

.-1-

,..--

·~

1:--

ISti

98 99

181

_,?,

... .

IGO

I··

l42

~ (g

tl 26

Tfi

181

11·

81 82 8S &4 IIJS

.. ttl lfl

·eo '

~·'

ff!

~·11

69 10

120

10 f11

11 rf11

66 fiT 66.

1101

r- j12

-.·

ICS ~-"'~...

._:.

fOO

109

61 62 -68

116 ··. 11

106

fot

,.-

67 68.

100

r-;

- t02 --.· ~

63 64 66

·.

1...;1

I r-

I 61

1..

I·

. .

Date

' ..... 11ft

01110

L-'-

:-1-1- .

,_l~l...--

•·

h"n 160 ~alma or 10 aotlons If more t n~ · ·

staple add!tlonal·shoot n.ere (LEFT INSIDE~

BEST AVAILABLE COPY

L....-L--

Page 1 o

Google Search: (exception) (single cycle clocking) "timing constraint"

i,QMI Web £PDF]

Web

Images

GroupsNew!

News

Froogle

l(~J(_<;~P.~.~.r1) ..(S.!~~-!~ . C.Y..<;_I_~_.c;_I_()_C.~.r1J0 ..~-~r.!l.i.r1.~..s!:!!1!:!111!!!!!1!1!1 ~:,~~:~~earctt Results 1 - 50 of about 93 for (exception) (single cycle clocking) "timing constraint". (1.26 secon

Focus: The Automatic Generation of Golden Timing Constraints

Fih:.: Format: PDF/Adobe Acrobat- View as HTML ... ·collectively referred to as exceptions to single-cycle clocking .•.• Figure 4: Golden timing constraint file for example design •.. W\1\'W.saros.co.uk/focus/whitepaper.pdf- $.i.m\!~LP~9~§. [PDFJ

Designing the Low-Power M ·CORE Architecture

File Fonnat PDF/Adobe Acrobat- View as HTML ... Architecture (ISA), the custom datapath design, and the clocking. methodology . ... single cycle find-first-one instruction (FF1), a hardware loop ..• www.ece.umd.edu/courses/enee759m.S2000i papers/scott1998-lowpower.pdf- .$l.mH~L!~~.9~.§. [PDFJ

XAPP640 "Timing Constraints for Virtex-11 Pro Designs" v1.1 (01/03)

File Format: PDF/Adobe Acrobat- View as HTML ... processor is in single-cycle mode. Multi-cycle mode occurs when the ..• timing constraint used is the PERIOD constraint, the clocks are related back to .•. direct.xilinx.com/bvdocs/appnotes/xapp640.pdf- Si;ni!ar pages

TechXclusives- Timing Closure- 6.1 i ... Exception: Spartan-3. Can reduce multiplexer delays Omprove •.. synchronous elements driven by a single clock ... Based on these two facts, multi-cycle constraints can ... direct.xilinx.com/xlnx/xweb/xil_tx_display. jsp?sTechX_ID=r.v_tim_closure_61i&iLanguageiD=1 - 69kG.?..GI:!~~- - .$.!mi.!?..L!?.?..9.~~

FPGA FAQ comp.arch.fpga archives- messages from 73725 ... a slow clock and it would be best if I could put a timing constraint on the fast signals .... If you have a DCM available just for clocking in the data, ... W'<.vw.fpga-faq.corn/archives/73725.htrn! - 61 k- Cached - Sirnilar oaaes

FPGA FAQ comp.arch.fpga archives- messages from 52075

- - -- -

... Timing constraint: TS_clk2x_int = PERIOD TIMEGRP "clk2x_int" ts_clk_in I> 2.000000 ... sounds like the result of over-clocking a > systolic processor! .•• www.fpga-faq.com/archives/52075.html - 75k - G~.!.<.tl~Q - .S.i.r.nU5;1LP.~.9.~-~ __ rr~Jog~ @;?.!?.tt~.:~m.m.w.w.~ir.m~~::t.~9,:~gm_

1 ------- - - --- -· ·- - --

__________ _

Synopsys Design Compiler - Whitepaper ... By default, Design Compiler calculates single cycle timing for .•. allows designers to define multi-cycle paths, false .•. point-to-point timing exception commands are ... WW'N.synopsys.corn/products/!ogic/dc_wp97.htrnl- 39k- Cached- Simi!ar pages [PDFJ

Designing the Low-Power M • CORE Architecture

Filt:.: Format: PDF/Adobe Acrobat -View as HTML ... shift (ASR), and rotate operations (ROTL), a single cycle find-first ••. to select either register file for exception processing with no cycle penalty [20 ..• davinci .sn u.a c. kr/courses/emb/2000/doc/34 .pdf - §i.mH~r..p~g~_;? [PDFJ

Microcontrollers

I f).- :Jt-o4-

File Fonnat PDF/Adobe Acrobat- View as HTML ... normal CPU operation provided that it can be completed in a single cycle .••• The BDM serial interface uses a clocking scheme in which the external host ••• vV\.V\"'.freescale.cornlfiles/microcontrollers/ doc/ref_rnanuaVS12BDMV4.pdf- .$.!m.i.!~.L~~-9-~§ [PDFJ

Microcontrollers

gee

e ch

e ce

geccecc

h e

Page 1 o

Search Results

ar•

Wr:.k:~me

United States Patent and Trademark Office

»Search Results

Your search matched 0 of 1105713 documents. A maximum of 500 results are displayed, 15 to a page, sorted by Relevance in Descending order.

0Home 0WhatCan I Accem,'? 0LGW-DUt

Refine This Search: You may refine your search by editing the current search expression or entering a new one in the text box.

0Joumafs.

O 0

& Magazines Conferenre

Proceedings Stamlard"s

l(til!li

~Q) .~ ~~. ~.>.. (~~.~~ pti o~) ..<: (l~~~ ..(~i.n.Q I~ ..~'!~~.~ .~~()~.~

C Check

111111111llltill11111111

to search within this result set

Results Key: JNL = Journal or Magazine

CNF

= Conference

STD

= Standard

Oaytruthor

Ooasic

Results: No documents matched your query.

0Advanood Ocr~$Rt1i1

0JoinlfEE Establlsb IEEE Web JY:oount Acces~ the

0 0

IEEE Member

Digital library

Print f'c,~rrn~t

H9.m>l

I Log-out I Journals I Conference Proceedings I Standards I Search by Author I Basic Search I &1Y.?.r!~fi.:S~.i!I~h I Join IEEE I Web Account I New this week I_O_ Linking Information I Your Feedback I Technical Supoort I Email Alerting I No Robots Please I Release Notes I IEEE Online Publications I~ FAOI Terms I Sack to Copyright© 2004 IEEE- All rights reserved

/9.- 9.{-0d

eee

e eee

g e ch e ch e

e ce

Page 1 o

Search Results

+IEEE we:r.om;; United States Patent and Trademark Office

1.9.~i.C:~.. ~i.r:'.~ ........................................•

Your search matched 9 of 1105713 documents. A maximum of 500 results are displayed, 15 to a page, sorted by Relevance in Descending order.

0Home 0WhatCan lA~'?

0Log-out

..T~ieS of OOiminm..........

OJoumats .

· & Maga.dnes

Confere~ce Procoodlfli!JS

Ostamlatds

0 0

» Search Results

Refine This Search: You may refine your search by editing the current search expression or entering a new one in the text box.

((ti~i~~t.~CI~~::> .. (~~~~.P.~'?f1J.:O:~f1.~.>... (~.1.()_c;_k.if1.Q.L ............... .

Check to search within this result set

Results Key: JNL = Journal or Magazine

Bytrutllur

CNF

= Conference

STD

= Standard

1 Fast and practical false-path elimination method for large SoC designs Chul Rim; Soo-Hyun Kim; Joo-Hyun Park; Myung-Soo lang; Jin-Yong Lee; KyuMyong Choi; Jeong- Taek Kong; SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip] , 17-20 Sept. 2003 Pages: 397 - 400

Basi:c 0Advancad 0Cr(l$R~f

0JoinlfEE Establish IEEE Web:Aecoom

0Accassthe

fEEE Member

mgitat library

[Abstract]

[PDF Full-Text (355 KB)]

IEEE CNF

2 A protocol for timed atomic commitment Davidson, 5.; Lee, I.; Wolfe, V.; Distributed Computing Systems, 1989., 9th International Conference on , 5-9 June 1989

[Abstract]

[PDF Full-Text (664 KB)]

IEEE CNF

3 A 4-GHz effective sample rate integrated test core for analog and mixedsignal circuits Hafed, M.M.; Abaskharoun, N.; Roberts, G. W.; Solid-State Circuits, IEEE Journal of, Volume: 37 , Issue: 4 , April 2002 Pages:499- 514

[Abstract]

[PDF Fu II-Text (714 KB)]

IEEE JNL

Asynchronous processor survey Werner, T.; Akella, V.; Computer, Volume: 30 , Issue: 11 , Nov. 1997 Pages:67- 76

[Abstract]

[PDF Full-Text (352 KB)]

I .2-21-ot/.

IEEE JNL

s A picosecond-accuracy, 700-MHz range, Si bipolar time interval counter LSI

eee

e eee

g e ch e ch e

e ce

DBs

(timing adj constraint) and (synthesizable) and (exception same clock)

Default Operator

Plurals

Time Stamp

OFF

2004/12/2113:55

•~~'~ii~/~f!:~~::~e.•: ·······

!!!!!!!!!!!!!!!!!!!!! I! !!!!!!!!!!!I I 52

1478

(716/6).ccls. and (timing adj constraint) and (synthesiz$) and ((single adj cycle) adj clock$)

(timing adj constraint) and (synthesiz$) and ((single adj cycle) adj clock$)

OFF

2004/12/2113:28

US-PGPUB; USPAT; EPO; JPO; DERWENT; IBM_TDB

OFF

2004/12/2113:30

US-PGPUB; USPAT; EPO; JPO; DERWENT; IBM_TDB

OFF

2004/12/2113:35

716/6

Search History 12/21/04 1:55:50 PM Page 1 C:\APPS\east\workspaces\CASE191B.wsp

jjjjj~;: ~;: ~ ~ ~llll; i1~ ~jl~j ~ ~ ~ :::::::::::::::::::·:::::::::::: "'''"''''·''""'''''''"''' j

...........

(timing adj constraint) and (synthesizable) and ((single adj cycle) adj clocking)

Search History 12/21/04 1:55:50 PM Page 2 C:\APPS\east\workspaces\CASE191B. wsp

US-PGPUB; USPAT; EPO; JPO; DERWENT; IBM_TDB

OFF

2004/12/21 13:54

11/17/2004 ··'

15:29

CCPA

8317263475

PAGE

RECEIVED CENTRAL FAX CENTER

NOV 1 7 2004

1377

PTOISB/97 (12-n\

Appi'UWI!d far ll5a lhrougll 11130100. OMB 0861o003t

Pablnt and Tmdel!'lalf< Offlca: U.s. DEPAR'I"MEHT 01'" COMMERCE ID a ~on of nfannaiiGn un~eaa H carlalna • var OMB cordJDI numbllr.

In re: Caee;

Ajay Janaml Daga

P1377

Appllcatloi1No.;

Att Unit 2825 Subject

Elcaminer.

10/390.194 Sun J. lin

Filing date:

03/14/2003

An Automated Approach to Constraint Generation In IC Design

Certificate of Transmission under 37 CFR 1.8 Attention:

Sun J. Lin , Examiner

Fax No.: (703) 872-9306 I hereby certify that. this correspondence is being facsimile transmitted to the Patent and Trademark Office

on 11/17/2004 Date

Sheri Beasley Typed or j:)rtnted name of person signing Certificate

Note: Each paper must have Its each submitl:sd paper.

awn certificate of transmission, or this csrtifieate must IdentitY

Total Sheets Transmitted - 10 1. 2. 3. 4.

Amendment Transmittal - 1 sheet Duplicate Amendment Transmittal- 1 sheet Response A - 7 sheets Certificate of Transmission - 1 sheet

Please call (831) 726-1457 if you have any questions.

Burden Hour Statement: Thl& farm Is ....~m..t~Jd ID lake 0.03 hauns

a.~m!J(ate, Time will 1181}' _d'*cndlng 1111011 llle Reed& of lh" Individual CBBB.

A.rry CQtnmaniB on the amount a1 time ralllllred to comJIIo!la tl'lls fOnn allould ba aant lo Ole Cl1iaf lnformallon Olllcet, Patent and Trademark Office, Washington. DC 20231. DO NOT SEND FEES OR COMPLETED fOF!MS TO THIS ADDRESS. SEND TO; Asalatanl Commlaaiii~W~r for Patenla, WllahlngiDII, DC 20231.

PAGE 1/W RCVD AT 1111712004 5:25:48 PM ~astern Standard"TimW SVR:USPTO.£FXRF·112~ DNIS:8729306 *CSID:8317263475 *DURATION (mm-ss):02-38

11/17/2004

8317263475

i5:29

Method ofTransm.ission:

Facsimile

In q:ference to application of Serial No. For

PAGE

CCPA

P1377

CA.SE DOCKET NO.

Ajay Janami Daga

10/390,194

AD Automated Approach to Constraint Generation in IC Design

Sir. Transmitted herewith is and an amendment in the abovc-idattifiro application, under 37 C.F.R. 1.312.

Ill 121 0

No additional fee is required. Applicant claims Small entity status under 37 CFR 1.27. The fee has been calculated as sbown below.

•••• CLAIMS AS AMENDED **** ~

(1)

(2) Claims Remaining After Amendment

Total Claims

Minus

(5)

Highest No. Paid For PteViously

Present

Extra

Jndep Claims

Minus

....

First presentation of a multiple dependent claim

Terminal Disclaimer Fees

Extension Fee

lstMontb

(8)

Rate

Small Entitv

Large Entitv

Additional Fcc

s o.oo

"'"'"'

(7)'

{6)

(4)

(3)

02ndMonth

$ 0

3rdMonth

Total additional for claims, time e11:tensions and diselailXlcr kcs

0.00

o.oo

"'*

If the "highest Number Previously Paid For" in this space is tess than 20, write "20" in this space. **"'If the "highest Number PreviOQsly Paid For" in this space is less than 3, write "3~ in this sp~. """*"'Multiple dq>cmdoncies, if any, included in the above calculation. *If the entry in col.umn 2 is less than the ~ntry in column 4, write "0" in columnS.

A check in the amount of

0Charge$

0.00

to deposit account

is attached.

50-0534 • (A duplicate of this sheet is enclosed)

~ Please charge any additional fees or credit overpayment to Deposit Account is enclosed.

Respectfully Submitted,

50-0534

. A duplicate of this sheet

~ Donald R. Boys

R.,g, No. 35074

Donald R.. :Boys Central Coast Patent Agency, Inc. P.O. Box 187 Aromas, CA 95004 (831) 726-1457

PAGE 2110 aRCVD AT 11/1712004 5:25:48 PM ~astern Standaril TlmeJ aSVR:USPTO.fFXRF·1/2 aDNIS:8729306 aCSID:8317263475 *DURATION (mm-ss):02-38

11/17/2084

Method ofTransmission:

PAGE

CCPA

8317263475

15:29

Facsimile

P1377

CASB OOCKl!T NO.

In refc:nmce to application of Ajay Janami Daga SerialNo. For

10/390,194

An Automated Approach to Constraint Generation in IC Design

Sir; Transmitted herewith i$ and an amendment in the above-identified appHcation, undet 37 C.F.R. l.3ll.

0 0

No additional fee is required. Applicant claims SmaU entity status under 37 CFR l.:l7. The fee has been calculated as shown below.

G2l

**** CLAJMS AS AMENDED

•••• ~

(1)

(4)

(S)

(6)

(7)

(8)

Highest No. Paid Pot Previously

Present Extra

Rate Small

Rate L&.rp Entity

Additional

(3)"

(2) Claims Rem$ining After Amendment

Entitv Total

Minus

Minm;

** 24

Claims .lndep Claims

•••

First presentation of a multiple dependent claim

Terminal Disclaimer Pees

Extension Fee

lst Month

$ 0

02ndMonth

03rdMonth

Total additional for claims, time extensions and disclaimer fees

Fee

0.00

o:oo

0.00

•• If the "highest Number Previously Paid For" ln. this space is less than 20, write "20q in this spBA;;e. ••• If the "highest Number Previously Paid for" in this space is less than 3, write "3" in this space. •••• Multiple dependencies, if any, included in the above calculation. • If the: entry in colu.mn .2 is less than the entty in column 4, write "0'' in column 5.

A check ln the amount of

0Charge$

0.00

to deposit account

is attached.

50-0534 . (A duplicate of this sheet is enclosed)

Ill Please charge any additional f~ or credit overpayment to Deposit AccolUlt is enclosed.

Respectfully Submitted,

50-0534

. A duplicate of this sheet

£d/~f/LrDonAld R. Boys Reg. No. 35074

Donald R. Boys Central Coast Patent Agency, Inc. P.O. Box 187 Aromas, CA 95004 (831) 726-1457

COIP>Y

PAGE 3110 1 RCVD AT 1111712004 5:25:48 PM ~astern· standard TimeJ 1 SVR:USPTO-EFXRF·112 1 DNIS:8729306 *CSID:8317263475 *DURATION (mm-ss):02-38

11/17/~aa4

15:29

8317263475

CCPA

RECE~

CENTRAL F. ~

NOV 1 7 2004

IN mE UNITED STATES PATENT AND TRADEMARK OFFICE Art Unit 2825

ExiUlliner: Lin, Sun J. lnRe: Case: Serial No.: Filed: Subject:

To:

CENTER

Ajay Janami Daga P1377 10/390,194 03/14/2003 An Automated Approach to Constraint Generation in IC Design

The Commissioner of Patents and Trademarks Alexandria, VA 22313-1450

Dear Sir;

Response A

PAGE 4/W RCVD AT 11/1712004 5:25:48 PM ~astern Standard TlmeJ' SVR:USPTO.fFXRF路112' DNIS:8729306 aCSID:8317263475 aDURATION (mm-ss):02-38

11/17/2884

15:29

8317263475

CCPA

PAGE

-2-

Claims 1-24 are presented below for examination. Claims 1, 3, 5, 12, 13, 15, 17

and 24 are ~ended, and claims 2 and I 4 are canceled in this response.

1. (currently amended) A software-based system for generating timing constraints for a proposed IC desi!W, comprising: a first input as a synthesizable description of.the proposed IC dWgn; a second input as a clock specification for the proposed IC design; and a processing unit accepting the first and second inputs, apd determining therefrom as an output a set of timing constraints to guide implementation ·of the

proposed IC design;, wherein the processing unit. in detennining the timing constraints. determines exceptions to single-cycle clocking for the proposed IC design.

2. (canceled) 3. (currently amended) The system of claim ~ .Lwherein the exceptions include false paths and multi-cycle paths. ·4. toriginal) The system of cla1m 1 wherein the output is provided in Synopsys Design Constraint (SOC) format useable by one or more of virtual prototyping, logic synthesis, place & route, and static timing tools in design implementation. . .. · '·

5. (currently amended) The system of claim 1 wherein the oroposed IC design is one of an application-specific integrated circuit (A~IC) or a field-programmable gate array (FPGA).

6. (original) The system of claim 1 wherein the first and second inputs and output

••••

.,PAGE 5110 ~ RCVD AT 1111712004 5:25:48 PM ~astern Standard TimeJ ~ SVR:USPTO.£FXRF·112 ~ DNIS:8729306 •CSID:8317263475 •DURATION (mm-ss):02-38

11/17/2004

8317263475

15:29

CCPA

PAGE

-3timing constraints are for an individual functional block on an IC instead of for the entire IC.

7. (original) The system of claim 1 wherein the flrst and second inputs and output timing constraints are for paths between functional blocks on an IC.

8. (original) The system of claim 7 wherein results are used to partition overall IC timing requirements into block timing budgets.

9. (original) The system of claim 1 wherein the synthesizable description is provided as one of Verilog or VHDL format.

10. (original) The system of claim 1 wherein the first input is derived from a .lib model, and converted into one ofVerilog or VHDL format.

11. (original) The system of claim 10 wherein a facility is provided for a user to manually refine an automatically-generated model by adding functional detail.

12. (currently amended) The system of claim 1 wherein, as part of the clock specification users define the clocks, their periods, their phase shifts relative to a reference clock, and the nets on the proposed IC design to which a clock is applied.

13. (currently amended) A method for guiding an implementation phase for a proposed IC design, comprising the steps of: (a) providing to a processing unit as a first input a synthesizable description ofthe proposed IC design;

.. PAGE 6110' RCVD AT 11/1712004 5:25:48 PM ~astern Standard Time)' SVR:USPTO.ffXRF·1f2' DNIS:8729306 •CSID:8317263475 •DURATION (mm-ss):02-38

11/17/2004

15:29

8317263475

PAGE

CCPA

(b) providing as a second input to the processing unit clock specification for the proposed IC design; and (c) using the first and the second inputs by the processing unit to determine therefrom,

as an output, a set of timing constraints to guide

implementation of the proposed IC design. wherein, the processing unit in determining the timing constraints. determines exceptions to single-cycle clocking for the proposed IC design.

14. (canceled)

15. (currently amended) The method of claim M

.11.wherein the exceptions

include false paths and multi-cycle paths.

16. (original) The method ofclaim 13 wherein th.e output is provided in Synopsys Design Constraint (SDC) fonnat useable by one or more of virtual prototyping, logic synthesis, place & route, and static timing tools in design implementation.

17. (currently amended) The method of claim 13 wherein the proposed IC design is one of an application-specific integrated circuit (ASIC) or a fieldprogrammable gate array (FPGA).

18. (original) The method of claim 13 wherein the first and second inputs and output timing constraints are for an individual functional block on an IC instead of for the entire IC.

19. (original) The method of claim 13 wherein the first and second inputs and output timing constraints are for interaction paths between functional blocks on

PAGE 7110 a.RCVD AT 1111712004 5:25:48 PM ~astern Standard Time] aSVR:USPTO.£FXRF·112 aDNIS:8729306 •CSID:8317263475 •DURATION (mm-ss):02-38

11/17/2004

15:29

8317263475

CCPA

PAGE

aniC.

20. (original) The system of claim 19 wherein results are used to partition overall IC timing requirements into block timing budgets.

21. (original) The method of claim 13 wherein the synthesizable description is provided as one ofVerilog or VHDL format.

22. (original) The method of claim 13 wherein the first input is derived from a .lib model, and converted into one ofVerilog or VHDL format 23. (original) The method of claim 22 wherein a facility is provided for a user to manually refine an automatically-generated model by adding functional detail.

24. (currently amended) The method of claim 13 wherein, as part of the clock specification users define the clocks, their periods, their phase shifts relative to a reference clock, and the nets on the proposed IC design to which a clock is applied.

PAGE 8110 3 RCVD AT 1111712004 5:25:48 PM ~astern Stariltirlf TimeJ 3 SVR:USPTO-EFXRF·112 3 DNIS:8729306 •CSID:8317263475 •DURATION (mm-ss):02-38

11/17/2004

15:29

8317263475

CCPA

PAGE

â&#x20AC;˘ 6-

REMARKS The present response is to the Office Action mailed in the abovereferenced case on August 24, 2004. Claims 1-24 are presented for examination. Claims 1, 5-9, 12, 13, 17-21 and 24 are rejected under 35 U.S.C. 102(b) as being anticipated by Ginetti et al. (5,896,299), hereinafter Ginetti. Claims 4 and 16 are rejected under 35 U.S.C. 103(a) as being unpatentable over Ginetti in view of Landy et al. {6,658,628 Bl), hereinafter Landy. Claims 2, 3, 10, 11, 14, 15,22 and 23 are objected to as being dependent upon a rejected base claim, but are. indicated by the Examiner as reciting allowable subject matter. Applicant has carefully studied tbe prior art presented by the Examiner, and the Examiner's rejections and statements in the instant Office Action. In response to the merit rejections applicant amends independent claims 1

and 13 to recite the patentable limitations of claims 2 and 14 respectively. Claims 2 and 14 are accordingly canceled, and depending claims 3 and 15 are amended to correct the dependencies. Responding to the Examiner's claim rejections due to infonnalities, applicant amends the affected claims appropriately as suggested by the Examiner. Applicant's independent claims 1 and 13, as amended to include subject matter indicated by the Examiner as allowable, are now patentable over the prior

art presented by the Examiner. Claims 3 and 15 have been amended to reflect new dependencies. Depending claims 3~12 and 15-24 are now patentable on their own merits in their original form, or as amended herein, or at least as depended from a patentable claim. It is therefore respectfully requested that this application be reconsidered,

the claims the allowed, and that this case be passed quickly to issue. Ifthere are

PAGE 911.0 1 RCVD AT 11117/2004 5:25:48 PM ~astern standatd TimeJ 1 SVR:USPTO.fFXRFÂˇ112 1 DNIS:8729306 *CSID:8317263475 1 DURATION (mm-ss):02-38

11/17/2884

15:29

8317263475

CCPA

PAGE

-7-

any time extensions needed beyond any extension specifically requested witJl this amendment, such extension of time is hereby requested. If there are any fees due beyond any fees paid with this amendment, authorization is given to deduct such fees from deposit account 50-0534.

Respectfully Submitted, Ajay Janami Daga by

d.-.«6:!,~

• Donald R Boys Reg. No. 35,074

Donald R. Boys Central Coast Patent Agency P.O. Box 187 Aromas, CA 95004 (831) 72()..1457

PAGE 10110 *RCVD AT 1111712004 5:25:48 PM ~astern Standard TIRle) ~ SVR:USPTO·EFXRF·112 3 DNIS:8729306- CSID:8317263475 *DURATION (rnm-ss):02·38

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE

United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450

www.uspto.gov

APPLICATION NO.

FILING DATE

FIRST NAMED INVENTOR

IATTORNEY DOCKET NO. I

CONFIRMATION NO.

10/390,194

03/14/2003

Ajay Janami Daga

P1377

3209

24739

7590

EXAMINER

08/2412004

CENTRAL COAST PATENT AGENCY PO BOX 187 AROMAS, CA 95004

LIN, SUN J ART UNIT

PAPER NUMBER

2825

DATE MAILED: 08/24/2004

Please find below and/or attached an Office communication concerning this application or proceeding.

PT0-90C (Rev. 10/03)

Application No.

Applicant(s) DAGA, AJAY JANAMI

10/390,194

Office Action Summary

Examiner

Art Unit

Sun J Lin

2825

-- The MAILING DATE of this communication appears on the cover sheet with the correspondence address --

Period for Reply A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE THE MAILING DATE OF THIS COMMUNICATION. -

;a MONTH(S) FROM

Extensions oftime may be available under the provisions of 37 CFR 1.136(a). In no event, however, may a reply be timely filed after SIX (6) MONTHS from the mailing date of this communication. If the period for reply specified above is less than thirty (30) days, a reply within the statutory minimum of thirty (30) days will be considered timely. If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication. Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. ยง 133). Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any earned patent term adjustment. See 37 CFR 1.704(b).

Status 1)1:8l Responsive to communication(s) filed on 14 March 2003. 2a)0 This action is FINAL.

2b)C8] This action is non-final.

3)0 Since this application is in condition for allowance except for fonnal matters, prosecution as to the merits is closed in accordance with the practice under Ex parte Quayle, 1935 C.D. 11, 453 O.G. 213.

Disposition of Claims 4)1:8l Claim(s) 1-24 is/are pending in the application. 4a) Of the above claim(s) _ _ is/are withdrawn from consideration. 5)0 Claim(s) _ _ is/are allowed. 6)C8] Claim(s) 1,4-9.12.13.16-21 and 24 is/are rejected. 7)1:8l Claim(s) 2.3.10. 11.14.15.22 and 23 is/are objected to. 8)0 Claim(s) _ _ are subject to restriction and/or election requirement.

Application Papers 9)0 The specification is objected to by the Examiner. 1O)C8] The drawing(s) filed on 14 March 2003 is/are: a)C8] accepted or b)O objected to by the Examiner. Applicant

m~y

not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).

Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).

11 )0 The oath or declaration is objected to by the Examiner. Note the attached Office Action or fonn PT0-152.

Priority under 35 U.S.C. ยง 119 12)0 Acknowledgment is made of a claim for foreign priority under 35 U.S.C. ยง 119(a)-(d) or (f). a)O All

b)O Some* c)O None of:

1.0 Certified copies of the priority documents have been received. 2.0 Certified copies of the priority documents have been received in Application No. _ _ . 3.0 Copies of the certified copies of the priority documents have been received in this National Stage application from the International Bureau (PCT Rule 17.2(a)). * See the attached detailed Office action for a list of the certified copies not received.

Attachment(s)

C8J

1) Notice of References Cited (PT0-892) 2) Notice of Draftsperson's Patent Drawing Review (PT0-948) 3) 1:8Jinformation Disclosure Statement(s) (PT0-1449 or PTO/SB/08) Paper No(s)/Mail Date 03/14/03.

0 5) 0 6) 0

Interview Summary (PT0-413) Paper No(s)/Mail Date. _ _ . Notice of Informal Patent Application (PT0-152) Other: _ _ .

U.S. Patent and Trademarl< Off1ce

PTOL-326 (Rev. 1-04)

Office Action Summary

Part of Paper No./Mall Date 08182004

Application/Control Number: 10/390,194 Art Unit: 2825

Page 2

DETAILED ACTION

This office action is in response to application 10/390,194 filed on 03/14/2003.

Claims 1 - 24 remain pending in the application. Claim Objections

Claims listed below are objected to because of the following informalities: Claim 1, line 3, after "IC" insert -design-. Claim 1, line 4, after "IC" insert -design-. Claim 5, line 1, change "IC" to -proposed IC design-. Claim 12, Claim 13, Claim 14, Claim 17, Claim 24,

line 3, line 4, line 6, line 1, line 3,

in front of "design" insert -proposed IC-. after "IC" insert -design-. after "IC" insert -design-. change "IC" to -proposed IC design-. in front of "design" insert -proposed IC-.

Appropriate correction is required. Claim Rejections - 35 USCยง 102(b)

3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. ยง102(b) that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.

Claims 1, 5-9, 12, 13, 17-21 and 24 are rejected under 35 U.S.C. ยง1 02(b) as

being unpatentable over U.S. Patent No. 5,896,299 to Ginetti eta/. 5.

As to Claim 1, Ginetti eta/. teach the following subject matter: โ ข

Method and svstem containing a computer implemented process (i.e., software-based svstem) for fixing timing constraints for a hierarchical design

of electronic circuit- [title; abstract; col. 1, line 66- col. 2, line 5]; Notice that appropriate timing constraints are generated through fixing existing timing

Application/Control Number: 10/390,194

Page 3

Art Unit: 2825 constraints- [abstract]; A hierarchv design of circuit- [Fig. 14]; Notice that in a hierarchv design, an electronic circuit under study may be a function block in one hierarchical/eve/ (e.g., Fig. 3A) or a group of functional blocks arranged in manvhierarchica//eve/s (e.g., Fig. 14); A proposed IC design is any hierarchv design (one hierarchical/eve/ or many hierarchical levels) of electronic circuit under study. •

synthesizing a RTL-HDL tvpe description of the circuit (i.e., proposed /C) -

[abstract]; Notice that RTL-HDL is a synthesizable description (called first input); •

real clock timing (latency and skew). worst case conditions. best case conditions- [abstract]; Notice that the real clock timing (latency and skew). worst case conditions. best case conditions are constituents of a clock specification (called second input) of the proposed IC design under study;

•

Computer implemented process accepting the synthesizable description (first input) and the clock specification (second input), and determining therefrom

as an output a set of timing constraints (upper-bond timing constraints, lowerbound timing constraints)- [abstract]; Notice that the set of timing constraints

could be utilized in guiding timing implementation of the hierarchical circuit design {proposed IC design)- [col. 2, line 31 - 47; col. 5, line 1 - 60]. For reference purposes, the explanations given above in response to Claim 1 are called [Response A] hereinafter. 6.

As to claim 13, reasons are included in [Response A] given above.

As to Claims 5 and 17, Ginetti eta/. disclose one of his related publication on

"Using the ASIC synthesizer in DSP Designs"- [Other Publications]. Notice that the ASIC is a synthesizable IC. 8.

As to Claims 6 and 18, the explanations included in [Response A] could be applied

to any hierarchy circuit design, including a functional block (e.g., flip-flops) in an IC design. Ginetti eta/. show and teach timing constraints (CK1, CK2) of a circuit containing flip-flops 11. 13, which is a functional block- [Fig. 3A].

Application/Control Number: 10/390,194

Page4

Art Unit: 2825

As to Claims 7 and 19, in addition to reasons included in [Response A] given

above, Ginetti et a/. show and teach a circuit design 108 with two hierarchical parts (subcells 110. 112), there are timing constraints for paths (data path, clock path)

between subce/1 110 and subce/1 112- [Fig. 14; col. 6, line 66- col. 7, line 27]. Notice that subce/1 110 and subce/1 112 are functional blocks. For reference purposes, the explanations given above in response to Claims 7 and 19 are called [Response B] hereinafter. 10.

As to Claims 8 and 20, in addition to reasons included in [Response A] and

[Response B] given above, Ginetti eta/. teach subject matter on timing constrains in hierarchical designs of electronic circuits- [abstract; col. 1, line 5-9]. Notice that timing requirements is clock timing Oatencv and skew) specifications of hierarchical

parts- [abstract]. Block timing budgets are timing constraints of hierarchical parts. In a hierarchical design, overall IC is partitioned in hierarchical manners. 11.

As to Claims 9 and 21, as explained in [Response A] given above, Ginetti eta/.

teach that the svnthesizable description is provided as a HDL tvpe. Notice that a VHDL format description is a HDL type description. 12.

As to Claims 12 and 24, Ginetti eta/. teach that the clock description includes

clock period, (clock) waveform, skew and latency associated with each clock- [col. 5,

line 4- 6]. Notice that clock description is an input, therefore clock period, (clock) waveform, skew and latencv are defined and inputted by users. Waveform, skew and latencv of a clock define its phase shift relative to a reference clock. A clock is assigned

to each clock net. In designing a hierarchical electronic circuit, a user may need to assign many clocks to different clock nets. Notice also that many users may have different ideas in defining clocks, their periods, their phase shifts relative to a reference clock to the clock nets in the proposed IC design.

Application/Control Number: 10/390,194

Page 5

Art Unit: 2825

Claim Rejections - 35 USC Â§ 103 The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all 13. obviousness rejections set forth in this Office action: (a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.

The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows: (1 ). (2). (3). (4 ).

14.

Determining the scope and contents of the prior art. Ascertaining the differences between the prior art and the claims at issue. Resolving the level of ordinary skill in the pertinent art. Considering objective evidence present in the application indicating obviousness or nonobviousness.

Claims 4 and 16 are rejected under 35 U.S.C. 103(a) as being unpatentable over

U.S. Patent No. 5,896,299 to Ginetti eta/. in view of U.S. Patent No. 6,658,628 81 to

Landv eta/. As to Claim 4, Ginetti eta/. teach all subject matter recited in Claim 1, they do not

teach a method of providing the output in Svnopsvs Design Constraint (SOC) format usable by one or more of virtual prototyping, logic synthesis, place & route and static timing tools in design implementation.

But Landv eta/. teach generating appropriate

time budget (or timing constraints) in Synopsvs Design Constraint (SOC) format file, which is generated in a format or syntax corresponding to a .sdc suffix, for a particular design- [col. 4, line 34- 38]. Landy eta/. also show and teach the following subject matter:

â&#x20AC;˘

Timing file generator for hardmacro (e.g., AS/C)- [Fig. 1];

â&#x20AC;˘

Providing hardmac technology file and/or timing generation tool that may provide

transportable language or syntax that can be read and/or processed by other synthesis/layout/analysis tools- [col. 1, line 38- 54]; Notice that synthesis tool includes logic synthesis tool, layout tool includes place & rout tool, analysis tool includes static timing tool.

Application/Control Number: 10/390,194

Page 6

Art Unit: 2825

Notice that the Synopsys Design Constraint (SOC) format file is a transportable language or syntax. The timing constraints are generated in Synopsys Design Constraint (SOC) format file in order to provide a capability of being read and/or processed by logic synthesis, place & rout tool and static timing tools provided by other

vendors. Data generated in a transportable language or syntax is very helpful for a design company utilizing a variety of logic synthesis, place & rout tool and/or static timing tools, which are provided by different manufacturers.

Therefore, it would have been obvious at the time the invention was made to a person having ordinary skill in the art to have applied the teachings of Landy eta/. in generating timing constraints in Synopsys Design Constraint (SOC) format file in order to provide a transportable capability of being read and/or processed by a variety of logic synthesis, place & rout tool and static timing tools, which are provided by different vendors. For reference purposes, the explanations given above in response to Claim 4 are called [Response C) hereinafter. 16.

As to Claim 16, reasons are included in [Response C) given above. Allowable Subject Matter

17.

Claims 2, 3, 10, 11, 14, 15, 22 and 23 are objected to as being dependent upon a

rejected base claim, but they would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Those claims are allowed is because that the prior art does not teach or fairly suggest the following subject matter: â&#x20AC;˘

The processing unit, in determining the timing constraints, determines exceptions to single-cycle clocking for the proposed IC design in combination

with other limitations as recited in Claim 2 and Claim 14, respectively; â&#x20AC;˘

The first input is derived from a .lib model and converted into one of Veri log of VHDL format in combination with other limitations as recited in Claim 10 and Claim 22, respectively;

Page 7

Application/Control Number: 10/390,194 Art Unit: 2825 Conclusion

18.

Any inquiry concerning this communication or earlier communications from the

examiner should be directed to Sun J. Lin whose telephone number is (571) 272-1899. The examiner can normally be reached on Monday-Friday (9:00AM-6:00PM). If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Matthew Smith can be reached on (571) 272-1907. The fax phone numbers for the organization where this application or proceeding is assigned are (703) 872-9318 for regular communications and (703) 872-9319 for After Final communications. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (703) 3081782.

Sun James Lin Art Unit 2825 August23,2004

•

PTO/SB/08A (10.01) Approved for use through 10/3112002. OMB 0651.0031 U.S. Patent and Trademark Offl~e: U.S. DEPARTMENT OF COMMERCE Under the Paperwork Reduction Act of 1995, no persons are required to reapond to a collection of information unless It contslns a valid OMB

""nlrnl numbAr

INFORMATION DISCLOSURE STATEMENT BY APPLICANT (us& as many sh&ets as necessary) Sheet

lot I

Application Number Flllna Data First Named Inventor Art Unit Examiner Name Attorney Docket Number

_~ •.Ts;a ••-''"-~...«--

Publication Date MM.OO..YYYY

o..-t =o

....

I')

"i'+lr- "Z 11 'Z- 5"' N*' I

Nama of Patentee or Applicant of Cited Document

~"'

Pages, Columns, Lines, Where Relevant Passages or Relevant Flaures Aooear

_U$:_60/365_,~_9___ ._--.N~A__ Aiav Janam__i_D_a..;.ltli"· .. -..-I---...;Prio=·o=ri!Y. Clai!Jl:;._____ 1 ____________ 1__________1____________________ r------------------

------l·--·~~u=s-

·----·· ............. !:'~:......... --.. ·--···-···- ·--..·------ --------·------··t------------"·--- - - - __ us~-----. ----·----- -·---·--·-- ·------·--·-·--..·-- _____ , ___ ,________. ._____ _ ---·-..---- · usus....... _..______ ·-----·---r---.. --------·--- -----------------

....... ----·-------- -

-- ------·---------1

-··-·. --- --- ..!1.~----------- __________ . . . --._ --------- -------------... ____ --· ~~----- ..-------- ----------·- -----·-----------·-·- ---------·--·--·----·-------

r---·-·-- - - _u_s-----------·-·-·- --------- - - - - - - - - - - - - ------..----·----11

r-·

us·----- ·-- us._ us.

. ......................................................_..._.....----------11--------------H

US........ --u-5:-·-. .-...----·--· --------- -·-·-----·--·-·---- --------------·---

------ --'-'----------1------1·----·--------- ------·------------ __ US- - - - - - - - · ----·-----1---· ---------------------------

- - - - - - U S - - - - - - - - - - - 1 - - - - - - · 1 - - - · - - - - - - - - - · - - ·--------····-------·--.. --·---

· - · - - --I·..::Uo::S:...·------·-1·--------US-

-------·--·--··-1·--·-------·-----

------ --------------;+--------1- ----------1·---------------

---- ---- ~-=---·--------------- ------------------·-------·-USFOREIGN PATENT DOC Examiner Cite 1 Initials' No.

-~Podol ~u!!'be~:IOnd~a'Jf.-)

Publication Dale .....~M-[;)~YYYY

Name of Patentee or Applicant of Cited Document

Pages, Columna. Unoo, Where Relevant PaNgea or Relevant Flgurea Appear

------- -------------------------- --------- --·----------- -----------· - - - ·----------------c......._,__...............-.......................___________ !-----------·-·---- ·-- ----·------ ----·--- -------· - - -..------··!---------- ----- -- - - - · ·-----------........ ____.. --·----- -------·---r--..-------·--- -- - - - - - - - - - - - - - - - - - - ·---------..- - - - - - - - -..·-·--1---------1--

'EXAMINER: Initial If reference consider , whether or nol cltstion is In conformance with MPEP 609. Draw line through citation If not In conformance and not considered. Include copy of this form wllh next communication to applicant. Applicant's unique citation designation number (optional). 2 See Kinds Codes of USPTO Patent Documents at www.uspto.gov or MPEP 901.04. 3 Enter Office thai Issued the documen~ by the two-letter code (WIPO Standard ST.3). 4 For Japanese patent documents, the indication of the year of the reign of the Emperor must precede the aerial number of the patent document. 5 Kind of document by the appropriate symbols as indicatad on the document under WIPO Standard ST. 16 If possible. 8 Applicant Is to place e chock marie here if English language Translation Is attached. Burden Hour Ststoment: This form Ia estimated to take 2.0 h011n1to complete. Time will vary depending upon the needs of the Individual case. Any commanb on the amount of time you are required to complete this form should ba sent to the Chief Information Officer, U.S. Patant and Trademark Ofllce, Washington, DC 20231. DO NOT SEND FEES OR COMPLETED FORMS TO THIS ADDRESS. SEND TO: Asalstsnt Commissioner fer Patents, Washington, DC 20231. 1

;:;;;;;;g .

C"'c:::::a~C"'

03/1412003 Ajay Janami Daga

U.S. PATENT DOCUMENTS Examiner Cite tnltiats' No. 1 Number·IOndCodo'(lf-

•~

-~= . . \D..__,

P1377

ood4 ~

Ulc:::::a-...... ..:en=..,.

Complet if Known

Substitute for form 1449A/PTO

10/390,194

Applicant(sYPatent Under Reexamination DAGA, AJAY JANAMI

Examiner

Art Unit

Sun J Lin

2825

Application/Control No.

Notice of References Cited

Page 1 of 1

U.S. PATENT DOCUMENTS Document Number Country Code-N umber-Kind Code

Date

Classification

Name

MM-YYYY

US-5,896,299

04-1999

Ginetti et al.

716/4

US-6,658,628 81

12-2003

Landy et al.

716/1

US-

USFOREIGN PATENT DOCUMENTS Document Number Country Code-Number-Kind Code

Date

MM-YYYY

Country

Name

Classification

N 0

p Q R

s T NON-PATENT DOCUMENTS

Include as applicable: Author, Title Date, Publisher, Edition or Volume, Pertinent Pages)

u v

w X

A copy of thts reference IS not being furntshed wtth thts Office action. (See MPEP ยง 707.05(a).) Dates in MM-YYYY format are publication dates. Classifications may be US or foreign. U.S. Patent ard Trademarl< Office

PT0-892 (Rev. 01-2001)

Notice of References Cited

Part of Paper No. 08182004

Page 1 o UNITED STATES PATENT AND 1'RADEMARK OFFICE UNITED STATFS DEPARTMENT OF COMMERCE United States Patent and Trademark Office Addre": COMMISSIONER FOR PATENTS P.O.llox 14'0 Al""""dria, Vu:gi.nia 22313·1450 www.uspto.gov

*BIBDATASHEET*

CONFIRMATION NO.3

Bib Oat! Sheet

FILING DATE 03/14/2003

SERIAL NUMBER 10/390,194

CLASS

GROUP ART UNIT

ATIORNEY DOCKET NO

716

2825

P1377

RULE

~PPLICANTS Ajay Janami Daga, Lake Oswego, OR;

Y'o:s.

*CONTINUING DATA •••••••••••••••••••••••••

This appln claims benefit of 60/365,749 03/18/2002

* FOREIGN APPLICA 110NS ••••••••••••••••••••

!JlJ7V(r

•• SMALL ENTITY ••

IF REQUIRED, FOREIGN FILING LICENSE GRANTED • 05/13/2003

Foreign Priority claimed 5

usc 119 (a·d) condttlons met ~ ~

!verified and Acknowledged

yes

!!(no

yes

IE)' ')."

D Me1 a11er All

Ex!lnineilfl Signature

lni

STATE OR

SHEETS

TOTAL

INDEPENDEN

COUNTRY OR

DRAWING

CLAIMS 24

CLAIMS 2

!ADDRESS

~4739

CENTRAL COAST PATENT AGENCY PO BOX 187 IAROMAS,CA 195004 !TITLE

~utomated approach to constraint generation in IC design

FILING FEE RECEIVED 411

FEES: Authority has been given in Paper No. to charge/credit DEPOSIT ACCOUNT No. for following:

ID ICJ ICJ ID ID ID

All Fees 1.16 Fees ( Filing ) 1.17 Fees ( Processing Ext. of time ) 1.18Fees{lssue) Other credit

Index of Claims

I III II 111111 II

10/390,194 Examiner

DAGA, AJA Y JANAMI Art Unit

Sun J Lin

2825

(Through numeral) Cancelled

= Allowed

Restricted

Claim c:: ii

Applicant(s)

Rejected

..;

1\l

Application No.

Date

(ij

c:: ~ ·a ·c:: "'

ii)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

.,J

0 0 .,J .,J .,J .,J .,J .,J

0 0 .,J .,J

0 0 .,J .,J .,J .,J .,J .,J

0 0 .,J

Claim iii

c:: ii

Appeal

Interference

Objected

Claim

Date

(ij

c:: ·a ·c

iii

c:: ii

51 52 53 54 55 56 57 58 59 60 61 62 63 64

65 66 67 68 69 70 71 72 73 74 75 76 77

78 79 80 81 82 83

35 36 37 38 39 40 41 42 43

85 86 87 88 89 90 91 92 93

45 46 47 48 49 50

95 96 97 98 99 100

U.S. Patent and Trademark Office

Non-Elected

1'""1

HI I:'' I I I

Date

iii

c:: ·a ·c::

101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Part of Paper No. 08182004

Application No.

Search Notes

1111~1111111111111111111

10/390,194

DAGA, AJAY JANAMI

Examiner

Art Unit

Sun J Lin

2825

SEARCH NOTES (INCLUDING SEARCH STRATEGY)

SEARCHED Class

Subclass

Date

Examiner

716

8/10/2004

JSL

716

Applicant(s)

8/10/2004

DATE

EXMR

EAST (USPAT;USPGPUB;UPO;JPO;DERWENT;IBM_T DB]

8/10/2004

JSL

IEEE

8/10/2004

JSL

INTERFERENCE SEARCHED Class

Subclass

U.S. Patent and Trademark Office

Date

Examiner

Part of Paper No. 08182004

Page 1 o

Search Results

+IEEE W~i(~()mi\

United States Patent and

.l:!.!llQ.

FAO

Terms

IEEE Peer Review

Tradem~rk

Office

. . . . . . . . . . . . . . . ...lil

>> Search Results

Your search matched 0 of 1060766 documents. A maximum of 500 results are displayed, 15 to a page, sorted by Relevance in Descending order.

Ottome QwWllatCan iA~'1

0Log4lut

Refine This Search: You may refine your search by editing the current search expression or entering a new one in the text box.

O 路路

j(lib... r:rlo~~l).~~n,~~.(V.~~r.<o.I?.V.~r.iiO.Q) .. C Check to search within this result set

Joumals & ~'aga.dn~ ConferenC$ Pmcoodings Ostanoa~

Results Key: JNL = Journal or Magazine

CNF

= Conference

STD

= Standard

0ByAuthor

Oaasic

Results: No documents matched your query.

OM~at\C~

0JoiniEEE b"'WbiiSb lEEE web M.etltmt

0 0

Access the: IEEE Men:tbaf

DigHal Ubrnry

J.bti(t搂f< tha

Ente:r.pns;:e

fHeCabitH~t

lEi3 Print FQrm~t I Log-out I Journals I Conference Proceedings I Standards I Search by Author 1Basic Search I A.:~.Y.;\!'l9'l>i.:";!~!m<h 1Join IEEE 1Web Account 1New this week I_O_ Linking Information I Your Feedback I Technical Support I Email Alerting I No Robots Please 1Release Notes I IEEE Online Publications 1.!:!2.!R..I FAOI Terms 1Back to

.tlJ?.m~

8-to-ot/.

eee

e eee

g e ch e ch e

) LNumber 1

Search Text (clock adj specification) and ((phase adj shift) near (reference adj clock)) and (period)

((phase adj shift) near (reference adj clock)) and (period)

1580

716/1

1345

716/6

(716/l).ccls. and (timing adj constraint) and (synthesiz$ adj description) and ( clock adj specification)

(716/6).ccls. and (timing adj constraint) and (synthesiz$ adj description) and ( clock adj specification)

(716/$).ccls. and (timing adj constraint) and (synthesiz$ adj description) and (clock adj specification)

(timing adj constraint) and (synthesiz$ adj description) and (clock adj specification)

(relaxation same (clock adj requirements)) and (timing adj constraint) and (synthesiz$ adj description) and (clock adj specification)

(relaxation same (clock adj requirements)) and (timing adj constraint) and (clock adj specification)

(relaxation same (clock adj requirements)) and (timing adj constraint)

Search History

(specification) same ((phase adj shift) near (reference adj clock)) same (period)

8/10/04 3:59:40 PM

Page 1

C:\APPS\east\workspaces\CASE 191. wsp

DB USPAT; US-PGPUB; EPO; JPO; DERWENT; IBM_IDB USPAT; US-PGPUB; EPO; JPO; DERWENT; IBM_IDB USPAT; US-PGPUB; EPO; JPO; DERWENT; IBM_IDB USPAT; US-PGPUB; EPO;JPO; DERWENT; IBM_IDB USPAT; US-PGPUB; EPO; JPO; DERWENT; IBM_IDB USPAT; US-PGPUB; EPO;JPO; DERWENT; IBM_IDB USPAT; US-PGPUB; EPO; JPO; DERWENT; IBM_IDB USPAT; US-PGPUB; EPO;JPO; DERWENT; IBM_IDB USPAT; US-PGPUB; EPO; JPO; DERWENT; IBM_IDB USPAT; US-PGPUB; EPO;JPO; DERWENT; IBM_IDB USPAT; US-PGPUB; EPO;JPO; DERWENT; IBM_IDB USPAT; US-PGPUB; EPO;JPO; DERWENT; IBM IDB

Time stamp 2004/08110 15:57

2004/08/10 15:58

2004/08/10 12:51

2004/08/10 12:53

2004/08110 13:35

2004/08/10 15:23

2004/08/10 13:43

2004/08/1 0 13:44

2004/08/10 13:44

1 (relaxation same (clock adj requirements)) and (clock adj specification)

1 (relax$ same (clock adj requirements)) and (clock adj specification)

(relax$ same (clock adj requirements))

(relax$ same (clock adj requirement))

(exceptions near ((single adj cycle) adj clock$))

(synopsys adj (design adj constraint))

(timing adj constraint) and ((VHDL or HDL or Verilog) same (lib adj model))

1 ((VHDL or IIDL or Verilog) same (lib adj model))

USPAT; US-PGPUB; EPO;JPO; DERWENT;

2004/08/10 13:45

IBM_TDB USPAT; US-PGPUB; EPO; JPO; DERWENT;

2004/08/10 14:57

IBM_TDB USPAT; US-PGPUB; EPO; JPO; DERWENT;

2004/08/10 13:51

IBM_TDB USPAT; US-PGPUB; EPO;JPO; DERWENT;

2004/08/10 13:52

IBM_TDB USPAT; US-PGPUB; EPO; JPO; DERWENT;

2004/08/10 13:54

IBM_TDB USPAT; US-PGPUB; EPO;JPO; DERWENT;

2004/08/10 13:55

IBM_TDB USPAT; US-PGPUB; EPO;JPO; DERWENT;

2004/08/10 15:25

IBM_TDB USPAT; US-PGPUB; EPO; JPO; DERWENT;

2004/08/10 15:26

IBM_TDB

((VHDL or IIDL or Verilog) same (deriv$) same (model))

((VHDL or HDL or Verilog) near (deriv$) near (model))

(model) near (conver$) near (VHDL or IIDL or Verilog)

(lib adj model) near (VHDL or HDL or Verilog)

USPAT; US-PGPUB; EPO;JPO; DERWENT;

2004/08/10 15:30

IBM_TDB USPAT; US-PGPUB; EPO;JPO; DERWENT;

2004/08/10 15:32

IBM_TDB USPAT; US-PGPUB; EPO;JPO; DERWENT;

2004/08/10 15:38

IBM_TDB USPAT; US-PGPUB; EPO; JPO; DERWENT;

IBM TDB

Search History 8/10/04 3:59:40 PM

Page 2

C:\APPS\east\workspaces\CASE191 .wsp

2004/08110 15:38

()\-I q-(23 / Please type a plus sign(+) inside this box Under the

EEJ

--.....

Reduction Act of 1995, no

>!JI

ll!if}[l's-

PTO/SB/05 (03-01) Approved for use through 10/31/2002. OMB 0651-0032 U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE a valid OMB control number.

Pl377

UTILITY PATENT APPLICATION TRANSMITTAL

00 00

I-)

[i]

ADDRESS TO: contents.

(preferred arrangement set forth below}

- Descriptive title of the invention - Cross Reference to Related Applications - Statement Regarding Fed sponsored R & D - Reference to sequence listing, a table, or a computer program listing appendix - Background of the Invention - Brief Summary of the Invention - Brief Description of the Drawings (jf filed) - Detailed Description - Claim(s) - Abstract of the Disclosure

Drawing(s) (35 U.S. C. 113)

5. Oath or Declaration

D i. D

CD-ROM or CD-R in duplicate, large table or Computer Program (Appendix) 8. Nucleotide and/or Amino Acid Sequence Submission (if applicable, a// necessary) a. b.

Computer Readable Form (CRF)

Specification Sequence Listing on:

0 ii. 0 i.

10.0

[Total Sheets

11.0

[Total Pages

12.

Newly executed (original or copy) Copy from a prior application (37 CFR 1.63 (d)) (for continuation/divisional with Box 18 completed)

DELETION OF INVENTOR{S) Signed statement attached deleting inventor(s) named in the prior application, see 37 CFR 1.63(d)(2) and 1.33(b).

6.0

Assistant Commissioner for Patents Box Patent Application DC 20231

(Submit an original and a duplicate for fee processing)

Applicant claims small entity status. See 37 CFR 1.27. [Total Pages Specification

Application Data Sheet. See 37 CFR 1.76

CD-ROM or CD-R (2 copies}; or paper

Statements verifying identity of above copies

Assignment Papers (cover sheet & document(s}) 37 CFR 3. 73(b) Statement Power of (when there is an assignee) ~ Attorney

fJCl

English Translation Document (if applicable)

13.0

Information Disclosure Statement (IDS)/PT0-1449 Preliminary Amendment

Copies of IDS Citations

15.0

Certified Copy of Priori!)' Document(s) (ifforeign pnority is claimed)

16.0

Nonpublication Request under 35 U.S.C. 122 (b)(2)(B}(i). Applicant must attach form PTO/SB/35 or its equivalent.

Return Receipt Postcard (MPEP 503) 14.00 {Should be specifically itemized)

17.(i] other:

dled-:iar:fee:s:::::::::::::::::::::::::::

18. If a CONTINUING APPLICATION, check appropriate box, and supply the requisite information below and in a preliminary amendment, or in an Application Data Sheet under 37 CFR 1. 76:

Continuation

Prior application information:

Divisional

Examiner

Continuation-in-part {ClP}

of prior application No.: Group Art Unit:

For CONTINUATION OR DIVISIONAL APPS only: The entire disclosure of the prior application, from which an oath or declaration Is supplied under Box Sb, Is considered a part of the disclosure of the accompanying continuation or divisional application and Is hereby Incorporated by reference. The Incorporation be relied when a has been omitted from the submitted

ID _ _ ~ ......_ :;;~

.-i

APPLICATION ELEMENTS

V4~=-......

g~-g

for new

SeeMPEP 600 Fee Transmittal Form (e.g., PTO/SB/17)

0 f-4 _ Q..q-o ~ ~ â&#x20AC;˘ .:...--~ 0

Custom<>r Number or Bar Code Label

Co"espondence address below

Name

Fax

No. Date

35 03/14/2003

Burden Hour Statement: This form is to take to complete. vary depending upon the needs of the individual case. Any comments on the amount of time you are required to complete this form should be sent to the Chief Information Officer, U.S. Patent and Trademark Office, Washington, DC 20231. DO NOT SEND FEES OR COMPLETED FORMS TO THIS ADDRESS. SEND TO: Assistant Commissioner for Patents, Box Patent Application, Washington, DC 20231.

;;;;;;;;;;

:-::=

!L!L

PTO/SB/17 (01-03) Approved for use through 04/30/2003. OMB 0651-0032 U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE Under the Panerwork Reduction Act of 1995 no nersons are renuired tor snond to a collection of information unless it disolavs a valid OMB control number.

Complete if Known

FEE TRANSMITTAL for FY 2003

Filing Date

I ($)

Art Unit

411.00

Credit card

Money Order

Other

3. ADDITIONAL FEES

None

Laroe Entltv

I I

Deposit 50-0534 Account Number Deposit Mark A Boys Account Name The Commissioner is authorized to: (check aff that apply)

liJ

Ocharge any additional fee(s) during the pendency of this application

FEE CALCULATION 1. BASIC FILING FEE

1001

750

2001

Fee Paid

Utility filing fee

375

1002 330

2002 165

Design filing fee

100:! 520

2003 260

Plant filing fee

1004 750

2004 375

Reissue filing fee

1005 160

2005

Provisional filing fee

SUBTOTAL (1)

I($)

m:J

[TI

375.00

Large Entity Fee Fee Code ($)

o=J

CIJxOD~ 0.00

c:::J9

Small Entitv F- Fee Code ($}

1202

2202

1201

2201

1203 280

2203

140

1204

2204

1205

2205

!Hm

Claims in excess of 20 Independent claims in excess of 3 Multiple dependent claim, if not paid •• Reissue independent claims over original patent •• Reissue claims in excess of 20 and over original patent

1{$~

36.00

••or number previously paid, if qreater; For Reissues, see above

Signature

2051

1052

2052

1053

130

1804

920*

1053

Fee Description

Fee Paid

65 Surcharge - late filing fee or oath 25 Surcharge - late provisional filing fee or cover sheet 130 Non-English specification

1812 2,520 For filing a request for ex parte reexamination 1804

920* Requesting publication of SIR prior to Examiner action

1251

110

2251

1252

410

2252

205 Extension for reply within second month

Extension for reply within first month

1253

930

2253

465

Extension for reply within third month

1254 1,450

2254

725

Extension for reply within fourth month

1255 1,970

2255

985 Extension for reply within fifth month

1401

320

2401

160 Notice of Appeal

1402

320

2402

160 Filing a brief in support of an appeal

1403

280

2403 1451

140 Request for oral hearing 1,510 Petition to institute a public use proceeding

110

2452

1453 1,300

2453

650 Petition to revive - unintentional

55 Petition to revive - unavoidable

1501 1,300

2501

650 Utility issue fee (or reissue)

1502

470

2502

235 Design issue fee

1503

630

2503

315 Plant issue fee

1460

130

1460

130 Petitions to the Commissioner

1807

1806

180

1806

8021

1809

750

2809

375 Filing a submission after final rejection (37 CFR 1.129(a))

1810

750

2810

375 For each additional invention to be examined (37 CFR 1.129(b))

1801

750

2801

375

Request for Continued Examination (RCE)

1802

900

1802

900

Request for expedited examination of a design application

50 Processing fee under37 CFR 1.17(q) 180 Submission of Information Disclosure Stmt 40

Recording each patent assignment per property (limes number of properties)

Other fee (specify) *Reduced by Basic Filing Fee Paid

SUBTOTAL (3)

I<$>

0.00

(Complete (if applicable}

SUBMITTED BY

Name (Prinl/fype}

I I I

Fee Description

SUBTOTAL (2}

130

1452

F-from Extra Claims ~ Fee Paid -20**= X 9 ~ 36.00 - 3*" =

1051

1451 1,510

2. EXTRA CLAIM FEES FOR UTILITY AND REISSUE Total Claims Independent Claims Multiple Dependent

Fee FCode ($)

1805 1,840* 1805 1,840* Requesting publication of SIR after Examiner action

to the above-identified deposit account.

Fee Description

Small Entitv

Fee Fee Code ($)

1812 2,520

Credit any overpayments

ocharge fee(s) indicated below, except for the filing fee

Large Entity Small Entity Fee Fee ee Fee , ~.,;oae• (~) ode ($)

FEE CALCULATION (continued)

Deposit Account:

Ocharge fee(s) indicated below

NA P1377

Attomev Docket No.

METHOD OF PAYMENT (check all that apply) ~ Check

Examiner Name

~ Applicant claims small entity status. See 37 CFR 1.27 TOTAL AMOUNT OF PAYMENT

A1av Janami Daga

First Named Inventor

Effective 0110112003. Patent fees are subject to annual revision.

NA 03/14/2003

Application Number

I I

l).¢}~d D ~-rvr;<

_ _,d

/~~~/7/J.

Registration No.

35074

JTelephone l

Date

_{8312. 726-1457 03114/2003

WARNIN~: Information on 'this lorm rna y'become p ubllc. Credit card information should not be Included on this form. Provide credit card Information and authorization on PT0-2038.

This collection of information is required by 37 CFR 1.17 and 1.27. The information is required to obtain or retain a benefit by the public which is to file (and by the USPTO to process) an application. Confidentiality is governed by 35 U.S.C. 122 and 37 CFR 1.14. This collection is estimated to take 12 minutes to complete, including gathering, preparing, and submitting the completed application form to the USPTO. Time will vary depending upon the individual case. Any comments on the amount of time you require to complete this form and/or suggestions for reducing this burden, should be sent to the Chief Information Officer, U.S. Patent and Trademark Office, U.S. Department of Commerce, Washington, DC 20231. DO NOT SEND FEES OR COMPLETED FORMS TO THIS ADDRESS. SEND TO: Commissioner for Patents, Washington, DC 20231.

tf you need assistance in completing the form, ca/11-800-PT0-9199 (1-800-786-9199) and select option 2.

"!! 路"'!o;T'' !!''1i

,~,'no,

Certificate of Express Mailing

"Express Mail" Mailing Label Number: EV262118478US Date of Deposit: 03/14/2003 Ref: Case Docket No.: P1377 First Named Inventor: Ajay .Janami Daga Serial Number: NA Filing Date: 03/14/2003 Title of Case: Automated Approach to Constraint Generation in IC Design I hereby certify that the attached papers are being deposited with the United States Postal Service "Express Mail Post Office to Addressee" service under 37 C.F.R. 1.10 on the date indicated above and addressed to the Commissioner of Patents and Trademarks, Washington D.C. 20231

1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

Utility patent application transmittal. 20 sheets of specification. 5 sheets of drawings. Fee transmittal. Duplicate fee transmittal. Information Statement Disclosure. Declaration and Power of Attorney. Check for fees in the amount of$411.00. Certificate of express mailing. Postcard listing contents.

Mark A. Boys (Typed or printed name of person ma'ling paper or fee)

(Si

An Automated Approach to Constraint Generation in IC Design by inventor Ajay .Janami Daga

Field of the Invention The present invention is in the technical area of integrated circuit (IC) design, and pertains more specifically to Electronic Design Automation (EDA) tools providing methods and apparatus for generating timing constraints in a design project.

Cross Reference To Related Documents The present non-provisional patent application claims priority to provisional application serial number 60/365,749, filed on 03/18/2002. The entire disclosure of provisional application 60/365,749 is incorporated herein by reference.

Background of the Invention The term integrated circuit (IC) is a very general term covering a very broad range of electronic devices based on solid-state electronics, such as microprocessors. It is now notoriously well-known that a vast array of consumer products, especially those products in the area of telecommunications and computerized devices (including personal computers),

-2-

are based on ICs, such as central processing units (CPUs), microprocessors, and, of course, digital memory devices of many sorts. In the art of IC design and manufacturing, ongoing research and development in a highly competitive environment is conducted to produce new and better devices, which are manufactured by usually well-know techniques involving many ways of treating semiconductor materials (wafers), applying thin-film materials, patterning, and selectively removing materials to create highly concentrated matrices of interconnected semiconductor elements, such as transistors, providing, in the end, minute, complex circuitry to perform specific tasks of computation and logic with almost unbelievable rapidity and reliability. Also typically, in the manufacturing process, many ICs are formed on a single wafer. After what is termed in the art the "front-end" processing, during which the ICs are formed, the individual ICs are separated into discrete units termed chips in the art, which may then be packaged and used in a wide variety ofways for different products and purposes. When developmental engineers conceive a new chip, it is of course necessary to lay out all of the circuits that will accomplish the purposes, which amounts to placing all transistors, resistors, and other devices, and plotting the interconnections that complete the circuitry. In the very early days of chip design this was a relatively straightforward process, at least a lot more straightforward than it is today. The trend in design, however, has always quite naturally been to faster and faster operation (clock speed), higher and higher density (area needed for circuitry), and lower power consumption to attain maximum computing or storage power in the least possible space. The speed motivation is obvious. Part ofthe density motivation is dictated by space and volume requirements in product design, and part by cost considerations. More good chips per wafer drives the cost per part down.

-3-

As need for density and speed steadily increase, new challenges arise in IC design. For example, specific manufacturing techniques, lithography for example, are always limited to such as minimum spacing of elements on a chip, line width in interconnects, and the like, and to achieve higher density it is often necessary to invent new processing techniques or improvements in older techniques. Likewise, even though higher density has a usually beneficial effect on speed capability (devices are connected closer together), allowing higher operating rate (clock speed), there are always limitations associated with device structure, materials, and the like, to speed as welt, and achieving higher and higher speed involves new inventions and discoveries in materials, combinations of materials, structures of devices, and so on. It therefore becomes apparent that a circuit diagram is only a starting

point in a new IC design, even though massive computing engines are needed even for this seminal part of a design. Given stringent requirements for a new design for speed, density, and power consumption, development engineers have to pick very carefully among many alternatives for materials, processes, film characteristics and thicknesses, interconnection alternatives, and much more; and the selections one makes almost always influence other possible selections and decisions, as all are intimately related. Still, even in the face of the complexity ofthe task, small market windows and short product lifecycles provide no room for error in the execution of chip design projects - schedule slippage is measured not just in terms of additional R&D costs, but in lost market opportunities that can be fatal for a company. Integrated circuit designers are therefore under tremendous pressure to design complex chips to meet design and marketing requirements. The design of complex multi-million-transistor chips requires the pervasive use of electronic design automation (EDA) software tools. These tools are used to take high-level descriptions of designs in languages that are

"!L !L!!

- 4-

very similar to programming languages and yield, through a series of complicated steps, the final mask for a chip. This flow is referred to as RTL to GDS-II (RTL is the initial design description in Verilog, VHDL and GDS-II is the mask for chip manufacturing). To counter the risk of designs not converging on requirements, engineers use virtual prototyping tools, a type ofEDA tool, to estimate downstream chip implementation characteristics (speed, area, power) from early design descriptions. The intent is to get an early gauge of design feasibility. Virtual prototyping tools have garnered significant interest in the design community, and virtual prototyping is among the fastest growing of EDA market segments. Virtual prototyping tools arguably provide reasonable estimates of delays along timing paths on a chip. The feasibility of a design, however, hinges on whether these delays are actually within acceptable bounds. Without good constraints on the permissible delays for the millions of timing paths on a chip, virtual prototyping tools are insufficient to gauge actual design feasibility. Absence of good timing constraints early in the design flow also results in chip implementation tools (logic synthesis, place & route) being asked to meet requirements that are both unnecessarily stringent and uncertain. This severely impacts ability of such tools to generate low-cost, low-power implementations that meet performance requirements without requiring design iterations. What is clearly needed is a tool that starts with the fundamental speed performance requirements for an IC to be designed, i.e. its clock speed, and by examining the intended functionality ofthe new chip in regard to how it will be clocked is capable of precisely identifying and constraining acceptable delays of timing paths on the new chip. Such a tool could generate golden timing constraints that must be obeyed for the finished chip to operate at its intended clock speed. Fundamental to the golden timing constraints for a chip

!!"'!!

- 5-

is that they describe not only the bounds on path delays that are established by the clock requirements of a chip, but that they also identify paths on a chip where clock requirements are relaxed. The relaxation of clock requirements is referred to in the industry as "exceptions to single-cycle clocking". The automatic identification ofthe exceptions to single-cycle clocking is fundamental to the generation of the golden timing constraints for a chip. The golden constraints, once determined, could then be used to drive existing virtual prototyping tools, logic synthesis tools, and place & route tools. The use of the golden constraints could, because of the automatically generated exceptions to clock requirements, then empower chip design without expensive and time consuming iterations, while also yielding chips that consume less area, less power, or, if required, run faster than was thought possible. A unique and innovative software system, called Focus by the inventors, for developing such golden timing constraints in IC design is taught in enabling detail in the descriptions of preferred embodiments below.

Summary of the Invention

In a preferred embodiment ofthe present invention a software-based system for generating timing constraints for a proposed IC design is provided, comprising a first input as a synthesizable description of the proposed IC, a second input as a clock specification for the proposed IC, and a processing unit accepting the first and second inputs, and determining therefrom as an output a set oftiming constraints to guide implementation ofthe proposed IC design. In preferred embodiments, the processing unit, in determining the timing constraints, determines exceptions to single-cycle clocking for the proposed IC design. Further, in a preferred embodiment the exceptions include

-6-

false paths and multi-cycle paths. Output in a preferred embodiment is provided in Synopsys Design Constraint (SDC) format useable by one or more of virtual prototyping, logic synthesis, place & route, and static timing tools in design implementation. The IC may be of any of many sorts, including application-specific integrated circuits (ASIC) or field-programmable gate arrays (FPGA). In one aspect of the invention the first and second inputs and output timing constraints may be for an individual functional block on an IC instead of for the entire I C. In another aspect the first and second inputs and output timing constraints may be for paths between functional blocks on an IC. In the latter case the results may be used to partition overall IC timing requirements into b Jock timing budgets. In preferred embodiments the synthesizable description is provided as one ofVerilog or VHDL format. In other embodiments the first input may be derived from a Jib model, and converted into one ofVerilog or VHDL format. In one embodiment a facility is provided for a user to manually refine an automatically-generated model by adding functional detaiL In various embodiments, as a part of clock specification, users may define the clocks, their periods, their phase shifts relative to a reference clock, and the nets on the design to which a clock is applied. In another aspect of the invention a method for guiding an implementation phase for a proposed IC design is provided, comprising the steps of (a) providing to a processing unit as a first input a synthesizable description ofthe proposed IC; (b) providing as a second input to the processing unit clock specification for the proposed IC; and (c) using the first and the second inputs by the processing unit to determine therefrom, as an output, a set of timing constraints to guide implementation of the proposed IC design.

- 7-

In preferred embodiments ofthe method, in step (c), the processing unit, in determining the timing constraints, determines exceptions to singlecycle clocking for the proposed IC design. The exceptions may include false paths and multi-cycle paths. Also in preferred embodiments ofthe invention the output is provided in Synopsys Design Constraint (SDC) format useable by one or more ofvirtual prototyping, logic synthesis, place & route, and static timing tools in design implementation. The method in preferred embodiments is applicable application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs), as well as to many other sorts ofiCs. In some cases the first and second inputs and output timing constraints may be for an individual functional block on an IC instead of for the entire IC. Also in some cases the first and second inputs and output timing constraints are for interaction paths between functional blocks on an IC, and may be used to partition overall IC timing requirements into block timing budgets. In preferred embodiments the synthesizable description is provided as one ofVerilog or VHDL format. In other embodiments the first input may be derived from a .lib model, and converted into one ofVerilog or VHDL format. Further, there may be a facility provided for a user to manually refine an automatically-generated model by adding functional detail. In other embodiments of the present invention, as part of the clock specification, users define the clocks, their periods, their phase shifts relative to a reference clock, and the nets on the design to which a clock is applied. The Focus system, as summarized above, provides significant advantages in IC design, by providing: â&#x20AC;˘

A reduction in the risk of design failures by providing engineers an early understanding of the precise challenges they face in realizing a design. By providing virtual-prototyping tools with golden timing

-8-

constraints, the Focus system empowers the tools to create more realistic block timing budgets. Correct block implementation constraints, in tum, reduce the risk of design iterations. â&#x20AC;˘

A reduction in the cost and power consumption of a design. By generating timing constraints that do not over-constrain a design, the Focus system allows block implementation tools to generate circuits that consume as little area and power as possible, while meeting performance objectives. Reduction in IC area typically translates to a reduction in unit costs. Reduction in power consumption is crucial for several consumer products.

â&#x20AC;˘

A reduction in IC design time by automating a task that is central to IC design. Engineers conventionally specify timing constraints in an adhoc and continually evolving manner. As timing problems are uncovered, and most of them tend be uncovered late in the implementation flow, exceptions to single-cycle clocking are inserted. All ofthis takes time, is error-prone and is the source of much anxiety during IC sign-off

â&#x20AC;˘

The Focus system empowers an RTL-handoff-based design flow. With the Focus system, system design houses are able to describe the design they want to implement and hand this design, along with its constraints, to a semiconductor vendor that will take responsibility for implementing the design to meet requirements. Semiconductor vendors typically prefer RTL handoffbecause it allows them to take responsibility for a greater portion of the design flow. System design houses prefer RTL handoffbecause it allows them to focus on their core competency, which is the design of compelling products.

-9-

In embodiments ofthe invention described in enabling detail below, for the first time a system is provided that allows users to identify false and multicycle paths ahead of implementation of a proposed design, and to use timing constraints determined therefrom in implementing the proposed design.

Brief Description of the Drawing Figures

Fig. l is a block diagram illustrating overall operation ofFocus system I 03 in a preferred embodiment of the present invention_

Fig. 2a is a first part of an example of a synthesizable description furnished as input to the system in an embodiment of the present invention. Fig. 2b is a final part of the example for which the first part is Fig. 2a_ Fig. 3 illustrates a clock specification input to the Focus system in an embodiment of the present invention. Fig. 4 is an SDC file generated for the example design described below with reference to Figs. 2a, 2b, and 3 in an embodiment ofthe present invention.

Description of the Preferred Embodiments

The system of the present invention, in a preferred embodiment, is a software-enabled system that automatically (i.e. without user-specified stimulus), analyzes a cycle-accurate description of interaction among functional blocks on a proposed IC, to generate timing constraints that must be satisfied by the IC to meet design requirements. It is well-known that there are, broadly speaking, two historically

distinct stages in the creation of a new IC: (1) the design stage, and (2) the

- 10-

implementation stage. The system of the invention, termed Focus by the inventors, links the two stages for the first time by establishing constraints imposed on the implementation stage by facts and characteristics of the design stage. It is well-known that development engineers constrain the delays on the

timing paths of a proposed IC based on the speed at which they intend to clock the IC. The engineers specify the clocks on their design and every timing path on the IC is required to have a delay less than the clock cycle. Known IC implementation tools strive to reduce path delays so that they are less than a clock cycle. There are, however, large numbers of timing paths in almost any design that are not relevant, that is, the functionality of the IC is such that the delay on these paths does not matter. These paths are typically termed false

paths, although they are false only in terms of the fact that the delay does not matter. There are also typically a significant number of timing paths on a proposed IC wherein, by design, engineers provide extra time to perform complex operations. These paths are termed multi-cycle paths. False and multi-cycle paths are collectively referred to as exceptions to single-cycle

clocking. The present inventors have determined that the critical timing constraints for an IC are defined by the clocks and exceptions to single-cycle clocking. At the time of filing the present patent application, it is known that engineers do not typically specify exceptions to clocking at the start of design flow. Instead, the engineers respond to timing problems reported by conventional IC implementation tools and, based on communication between design and verification engineers, establish whether a timing problem is real or needs to be handled by adding a timing exception to the constraint file for a design. This conventional process is an error-prone, time-consuming, process that continues throughout IC implementation flow, and compounds errors in the overall process.

- 11-

Overview

Fig. 1 is a block diagram illustrating overall operation ofFocus system 103 in a preferred embodiment of the present invention. The Focus system, as shown by the flow ofFig. 1, takes as inputs the synthesizable description for a design for an IC (102) and a specification for how the design is clocked (101). Without requiring any other information, the Focus system generates exceptions (false paths, multi-cycle paths) to single-cycle clocking. By automatically identifying exceptions to clock requirements, the Focus system relaxes the timing goals that an IC implementation must to obey. These exceptions and the user-provided clock definitions constitute golden timing constraints 104 for an IC under consideration. These constraints are written out in the industry standard Synopsys Design Constraint (SDC) format and are read and used by virtual prototyping, logic synthesis, place & route, and static timing tools, as shown in block 105. Applications in Design Flow

The Focus system is applicable to at least any digital applicationspecific integrated circuit (ASIC) or field-programmable gate array (FPGA) design and implementation. The Focus system is applicable as well for both synchronous and asynchronous designs. Focus is also applicable for the design of large and complex SaCs that contain l 0 million or more gates and run at clock speeds in excess of 300 megahertz (MHz), as well as for the design of FPGAs containing less than a million gates that run at speeds up to 1OOMHz or more. Further, the Focus system may be used to constrain and drive the implementation of individual blocks within an IC, as well as the entire I C. Considering the full IC, the Focus system is used to generate the golden timing constraints that constrain the interaction among blocks on the IC. These

- 12-

constraints are then imported by such as virtual prototyping tools, and used to partition overall IC timing requirements into block timing budgets that establish when information is available at the inputs of a block and when information must be available at the outputs of a block Considering IC block implementation flow, the Focus system generates the golden timing constraints for the internal implementation of a block. These block constraints, along with the block timing budgets generated using the Focus system and virtual prototyping tools, may be used to drive block implementation tools such as logic synthesis tools, place & route tools, and static timing tools. The Focus system in preferred embodiments is plug-and-play in existing design flow. Therefore engineers do not need to alter the way they do design, and they need to provide only minimal new information to the Focus system. The information the Focus system requires, which is substantially synthesizable design descriptions and clock specifications, is already at hand at the start of IC implementation flow. The information the Focus system generates is generated in a standard form (SDC) that is accepted across the industry by major EDA players and start-ups alike. The Focus system does not replace existing design tools, it simply makes them more effective. Synthesizable Description Input (102 of Fig. 1)

The Focus system takes as input the synthesizable description for an IC design and a specification of the clocks on the design. The synthesizable description for a design is provided as input to Focus in Verilog or VHDL format, both of which are well-known to the skilled artisan.

All conventional

synthesizable constructs in these languages are supported by the Focus system. Information for blocks on an lC design that do not have synthesizable descriptions, such as for external hard IP blocks, embedded memory, or user-

- 13-

instantiated library cells, for example, is provided as input to the Focus system using one oftwo approaches: 1) Users can provide a .lib model for the block as input. This model describes black-box timing relationships between pins on the block. This model is converted into a behavioral HDL model (Verilog or VHDL format) that captures the timing relationships between pins on an IP block. Users can refine this auto-generated model manually by adding functional detail. 2) Alternatively, IP providers can use a known product known as Reduce from FishTail Design corporation to generate an interface-logic model (ILM) from a synthesizable description for an IP block. This interfacelogic model, generated in Verilog or VHDL format, may be used as input to Focus in lieu of the full synthesizable description for a block. The constraints for a design can be generated using either a flat or hierarchical methodology. In a flat methodology, the Verilog and VHDL files for the full design are read into the Focus system. An example input as synthesizable description is illustrated in Figs. 2a and 2b, as the example is too large for a single drawing sheet. In a hierarchical methodology, individual blocks on the design are analyzed separately and ILM descriptions for these blocks are used when analyzing the full-chip.

Clock Specification Input (101 of Fig. 1)

In addition to the synthesizable description for a design, as described in examples above, to apply the Focus system users need to specify the clocks on the proposed IC design. As part of their clock specification users define the clocks, their periods, their phase shifts relative to a reference clock, and the nets on the design to which a clock is applied. Fig. 3 illustrates a clock

- 14-

specification input to the Focus system in an embodiment of the present invention.

Focus Analysis (103 of Fig. 1)

Given both the synthesizable description for an lC design and a specification for the clocks on the design, the Focus system proceeds to automatically identify false and multi-cycle paths. This analysis is performed without synthesizing the design description into a gate-level netlist. Instead, functional abstraction is performed on the design to only preserve the functional detail necessary for the purposes of computing false and multi-cycle paths, while discarding superfluous functional detail.

Symbolic simulation is

performed on the functionally abstracted design to ensure that the analysis is exhaustive and is performed without requiring user-specified stimulus. Functional abstraction helps ensure that the entire space of possible behaviors on a design can be symbolically simulated in a computationally feasible manner that scales to handle large designs. Generated by Focus- Golden Timing Restraints (104 of Fig. 1)

The user-specified clocks and the false and multi-cycle paths identified and determined by the Focus system are written out (output) in Synopsys Design Constraint (SDC) format to a text file. The information in this text file constitutes the golden timing constraints for an IC design. IC implementation tools such as virtual prototyping, logic synthesis, place & route and static timing ( l 05 of Fig. 1) import these constraints. The SDC file generated for the example design is shown in Fig 4. It will be apparent to the skilled artisan that there will be a variety of

alterations that may be made in embodiments ofthe invention described herein

- 15-

without departing from the spirit and scope of the invention. For example, there are generally a number of different ways that a software application may be written to accomplish similar or the same purposes, and there are typically also a variety of programming languages that may be used to create software for a system such as that described in preferred embodiments in the present specification. For these and other reasons the invention should be limited only by the scope of the claims that follow:

- 16-

What is claimed is:

l. A software-based system for generating timing constraints for a proposed IC design, comprising: a first input as a synthesizable description of the proposed IC; a second input as a clock specification for the proposed IC; and a processing unit accepting the first and second inputs, and determining therefrom as an output a set of timing constraints to guide implementation of the proposed IC design.

2. The system of claim 1 wherein the processing unit, in determining the timing constraints, determines exceptions to single-cycle clocking for the proposed IC design.

3. The system of claim 2 wherein the exceptions include false paths and multicycle paths.

4. The system of claim 1 wherein the output is provided in Synopsys Design Constraint (SDC) format useable by one or more of virtual prototyping, logic synthesis, place & route, and static timing tools in design implementation.

5. The

system of claim 1 wherein the IC is one of an application-specific

integrated circuit (ASIC) or a field-programmable gate array (FPGA).

ll..]L ,.,

f"'!l

- 17-

6. The system of claim l wherein the first and second inputs and output timing constraints are for an individual functional block on an IC instead of for the entire IC.

7. The system of claim 1 wherein the first and second inputs and output timing constraints are for paths between functional blocks on an IC.

8. The system of claim 7 wherein results are used to partition overalllC timing requirements into block timing budgets.

9. The system of claim 1 wherein the synthesizable description is provided as one of Veri log or VHDL format.

10. The system of claim l wherein the first input is derived from a .lib model, and converted into one of Veri log or VHDL format.

11. The system of claim 10 wherein a facility is provided for a user to manually refine an automatically-generated model by adding functional detail.

12. The system of claim 1 wherein, as part of the clock specification users define the clocks, their periods, their phase shifts relative to a reference clock, and the nets on the design to which a clock is applied.

13. A method for guiding an implementation phase for a proposed IC design, comprising the steps of:

- 18-

(a) providing to a processing unit as a first input a synthesizable description ofthe proposed IC; (b) providing as a second input to the processing unit clock specification for the proposed IC; and (c) using the first and the second inputs by the processing unit to determine therefrom, as an output, a set of timing constraints to guide implementation of the proposed lC design.

14. The method of claim 13 wherein, in step (c), the processing unit, in determining the timing constraints~ determines exceptions to single-cycle clocking for the proposed lC design.

15. The method of claim 14 wherein the exceptions include false paths and multi-cycle paths.

16. The method of claim 13 wherein the output is provided in Synopsys Design Constraint (SDC) format useable-by one or more of virtual prototyping, logic synthesis, place & route, and static timing tools in design implementation.

17. The method of claim 13 wherein the IC is one of an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

18. The method of claim 13 wherein the first and second inputs and output timing constraints are for an individual functional block on an IC instead of for the entire IC.

- 19-

19. The method of claim 13 wherein the first and second inputs and output timing constraints are for interaction paths between functional blocks on an IC.

20. The system of claim 19 wherein results are used to partition overalllC timing requirements into block timing budgets.

21. The method of claim l3 wherein the synthesizable description is provided as one ofVerilog or VHDL format.

22. The method of claim 13 wherein the first input is derived from a .lib model, and converted into one of Veri log or VHDL format.

23. The method of claim 22 wherein a facility is provided for a user to manually refine an automatically-generated model by adding functional detaiL

24. The method of claim l3 wherein, as part of the clock specification users define the clocks, their periods, their phase shifts relative to a reference clock, and the nets on the design to which a clock is applied.

-20-

Abstract of the Disclosure

A software-based system for generating timing constraints for a proposed lC design has a first input as a synthesizable description of the proposed IC, a second input as a clock specification for the proposed IC, and a processing unit accepting the first and second inputs, and determining therefrom. as an output, a set of timing constraints to guide implementation of the proposed IC design.

101

(104

103 Specification

~ FOCUS Tool

Synthesizable HDL Verilog, VHDL

Generates exceptions to single-cycle clocking

Golden Timing Constraints

Read and Used by: Virtual Prototyping Logic Synthesis Place & Route Static Timing

Results Exceptions

'-105

& ., â&#x20AC;˘..;<...

Clock Definitions

102

Fig.l

(Start) n1odule add_1nul (elk, reset, a, b, c, d, in_sel, op_sel, x, y); input elk, a, b, c, d, in_sel, op_sel, reset; output x, y; regx, y, count, latch_en, r_a, r_b, r_c, r_d, r_op_sel, r_in_sel; wire r_x, r_y, a_c, b_d, add, 1nul, add_Inul; always@ (posedge elk or posedge reset) begin if (reset) begin count<= 0; latch- en <= 0 '· r a<= o· ' r b <= o· ' r - c <= o·' r d <= o· ' r_op_sel <= 0; r- in- sel <= o·' end else begin if (!count) begin r_a <=a; r b <= b· ' r_c <= c; r - d <= d·' r _ op_sel <= op_sel; r_in_sel <= in_sel; if(op_sel) count <= count + 1 ; else latch- en<= 1'b1·' end else begin count<= 0; latch- en<= 1'b 1·' end end end

(Continued on Fig. 2b)

Fig. 2a

(Continued from Fig. 2a)

ass_ign a_c = r_in_sel? r_a: r_c; assign b_d = r_in_sel? r_b: r_d; assign add = a_c + b_d; assign n1ul = a_c * b_d~ assign add _n1ul = r_ op_sel ? tnul : add; assign r_ x = r_in_sel ? add_mul : x; assign r_y = r_in_sel? y: add_mul; alvvays@ (posedge elk or posedge reset) begiri if (reset) begin X<= 0; y <= 0; end else if (latch_en) begin x <= r_x; y <= r_y; end end endtnodule

(END)

Fig. 2b

read_design add_mul. v link_design create_clock clk200 -period 5 -net { elk} write sdc add mul. sdc

Fig. 3

#Clock Definitions set clk200_source _pins {} set clk200 _source_nets [get_nets { elk } ] set clk200_source_pins [add_to_collection $clk200_source_pins \ [get_pins -of $clk200_source_nets]] create_clock -name clk200 -period 5 -waveform { 0 2.5 } $clk200_source _pins #Exceptions for endpoints clocked by clk200 set_tnulticycle_path -through [get_nets mul] -setup 2 set_multi cycle_path -through [get_nets 111ul] -hold 1 set_false_path -through [get_nets r_c] -through [get_nets r_x] set_false_path -through [get_nets r_d] -through [get_nets r_x] set_false _path -through [get_nets r_a] -through [get_nets r__y] set_false_path -through [get_nets r_b] -through [get_nets r__y]

Fig. 4

Mar

13 2003

4:08PM

DECLARATION AND PO\VER OF ATTORNEY FOR PATENT APPLICATION ATIORNEY DOCKET NO. P1377 As a below named inventoT, I hereby declare that: My residence, post office address and citizenship are as stated be low nex.t to my name. I believe I am the original, first and sole inventor (if only one name is listed below) or an original, first lllldjoint inventor (if plural names are listed below) of the subject matter which is claimed and for which a patent is sought on the invention entitled: Automated APProach to Constraint Generation in IC Design the specification of which (check one) ~ is attached hereto. 0 was filed on: as patent aoolication serial number 0 and was amended on _ _ (If applicable) I hereby state that 1 have reviewed and understood the contents of the above-identified specification, including the claims, as amended by any amendment referred to above. I acknowledge tbe duty to disclose information which is material to patentability in accordance with Title 37, Code of Federal Regulations sec. 1.56. In the case that the present application is a continuation-in-part application, J further acknowledge the duty to disclose material information as defined in Title 37, Code of Federal Re~ulations sec. 1.56. which became available between the filing date ofthe prior application and the filing date of the present application. I hereby claim foreign priority benefits under Title 35, United States Code sl19 of any foreign applications for patent or inventor's certificate listed below and have also identified below any foreign application for patent or inventor's certificate having a filing date before that ofthe application on which priority is claimed: Prior Foreign Application(s) (Number)

(Country)

(Day/MonthlYear Filed)

(Number)

(Country)

(Day/Month/Year Filed)

I hereby claim the benefit under Title 35, United States Codes, sec. 119 and sec. 120 of any United States application(s) listed below and, insofar as the subject matter of each of the claims of this application is not disclosed in the prior United States application in the manner provided by the tirst paragraph of Title 35, United States Code, sec. 112, I acknowledge the duty to disclose material mformation as defined in Title 37, Code of Federal Regulations, sec. 156(a) which occurred between the filing date of the prior application and the national or PCT international filing date of this application. (Application Serial No.): 60/365.749 (Filing Date): 03/1 &/2002 (Status):~ (Application Serial No.): _ _ (Filing Date): _ _ (Status):---(Application Serial No.):__ (Filing Date): _ _ (Status}:---(Application Serial No.): _ _ (Filing Date): _ _ (Status):---{Application Serial No.):__ (Filing Date): _ _ (Status): _ _ __

POWER OF AITORNEY: As a named inventor, I hereby appoint:

[g)

lllllllllllllllllllllllllllllllllll

Practitioners at customer number: 24739

24739

I'ATENT TRADEMARK OFFICE

Practitioners: Name:

Registration number

to prosecute this application and transact all business in the Patent and Trademark Office connected therewith. Please send all correspondence practitioners at:

[8:1 The practitioners at the customer number indicated above

Customer number:

Place customer bar code label here

Mar

13 2003 4:08PM

Page2 DECLARATION Ai'I(DPOWEROF ATTORI'EY FOR PATENT APPLICATION ATTORNEY DOCKET ~0. P1377 [hereby declare that all statements made herein of my own knowledge are true and that all statements made on infonnation and belief are believed to be true; and further that these statements were made with the knowledge that willful false statements mtd the like so made are punishable by fine or imprisonment, or both, under Section 100 I of Title 18 of the United States Code and that such willful false statements may jeopardize the validity of the application or any patent issued thereon. :I

Post Office Address: same as above

• PATENT APPLICATION SERIAL N O . - - - - - - - - -

U.S. DEPARTMENT OF COMMERCE PATENT AND TRADEMARK OFFICE FEE RECORD SHEET

03/24/2003 tiMEKONEN 00000004 10390194 01 FC:2001 375.00 OP 02 FC:2202 36.00 OP

PT0-1556 (5/87) ·u.s. Government Printing Ofllce:

2001 -

481-697/59173

.... ,

Application or Docket Number

PATENT APPLICATION FEE DETERMINATION RECORD Effective January 1, 2003 CLAIMS AS FILED • PART I

SMALL ENTITY TYPE c::J

TOTAL CLAIMS NUMBER FILED

NUMBER EXTRA

TOTAL CHARGEABLE CLAIMS J.._minus 3 = *

MULTIPLE DEPENDENT CLAIM PRESENT

* If the difference in column

OTHER THAN SMALL ENTITY

X$9=

X$18=

X42=

X84=

+140=

+280=

TOTAL

OR TOTAL

SMALL ENTITY

RATE

FOR

INDEPENDENT CLAIMS

Pl377

1 is less than zero, enter "0" in column 2

FEE

BASIC FEE 375.00

CLAIMS AS AMENDED - PART II PRESENT EXTRA

RATE

ADD ITIONAL FEE

OTHER THAN SMALL ENTITY ADD ITIONAL

RATE

X$9=

X$18=

X42=

X84=.

+140=

+280=

TOTAL ADOIT. FEE

PRESENT. EXTRA

RATE

ADDITIONAL FEE

ADD ITIONAL

RATE

X$9=

X$18=

X42=

X84=

+140=

+280=

TOTAL ADDIT. FEE

PRESENT . EXTRA

·~r,·~···~··~'!'" Ji~l~sl>~th;3n the entry in c:plumn 2, w.rite "0" in column

RATE

ADD ITIONAL FEE

ADDITIONAL

RATE

X$9=

X$18=

X42=

X84=

+140=

.+280=

TOTAL PreviotJsly Paid For" IN THIS SPACE is less than 20, enter "20." ADDIT. FEE ~If the "Highest Number Previously Paid For" IN'•T.HIS SPACE. is less than 3, enter "3." . The "Highest Number Previously Paid For" (Total or Independent) is the highest number found in the appropriate box in column 1.

FORM PTC>-875 (Rev. 12/02)

OF COMMERCE

•.

SERIAI.·NO.

MUL nPLE DEPENDENT CLAJM FEE CALCULAnON SHEET

APPUC.•.NT( S)

CLAIMS

A3 nLEP

-----··---~-·----fl_.-~,: .·;.:;:·'·"-·.:.;-.-_-n--'~:......·•._),

AFTEI\ 10 AMENDMENT

IV' I tiUNU AMfHOMEH1'

,...-.J?!!-~.,.·,;;;IH_,;,o=I:::'-·"".. -,;;:,0:::-'EP:,_·-f

,,1\ji:!,

IHO

·---52

11 12

1 I

15 16

22 24

74 75

25 26

92 93

---~--------+------f----~r-----t---~--t------; 4

100

OEP

IHD

·---

IHO

· OfP

•

+ll< ====M == ~

PTO/SB/08A (10..01) Approved for use through 10/31/2002. OMB 0651..0031 U.S. Patent and Trademark Office: U.S. DEPARTMENT OF COMMERCE Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it contains a valid OMB cnntrnl numhAr

(use as many sheets as necessary)

Iot I

o.....-t=o ..... to:)=

Pages, Columns, lines, Where Relevant Passages or Relevant Fiaures Aooear

Name of Patentee or Applicant of Cited Document

Publication Date MM·DD·YYYY

US-

:····················· . ············ 1,11): ·....................... ················ ,l,ls;:_ US-

••• ••••••••• • ' 'US• • • . . .. . ._......... ~-•

N·················· I · ···I

~----K-~----

-------#-#-~-

\:1~~-

----

...':J.~: . USUS·

··us:· US-

+·····

H ......................

........................

.....................................- ........--------H .....................

...........................................................................

I US·

........ ......... ..!::'.~: ____________________________ ................................. --------------------------------------------··· ----·---··- ···-----------------------------................ ------- ..\!~----·····--------------- ----------------·--·----- _____________________________..________ .......................................,_______________ _

.........................

US·

-~·s:··--·---·---··-·--------------

------·---------------------- .............____________________________________....................................... . . . . . . . . . . . . . . "

.lJS:. US-

FOREIGN PATENT DOCll1wc:N Examiner Cite 1 Initials· No.

Foreion Patent DocumAnl

Cru:lrYCode 3_:~~!:'1.b.EI~:I<Intlt:;<:ld•' Wkil<>":")

N·---------- · --I ·········I··········

..........

: Examiner [, Signature

Publication Date MM·DD·YYYY

Name of Patentee or Applicant of Cited Document

Pages, Columns, Lines, Where Relevant Passages or Relevant Figures Appear

1..................................................................................... 1 ...................................................... ..

................................... ....................... .......................... ,

o:t<

ID---'Mc::::J - M

U.S. PATENT DOCUMENTS Examiner Cite Initials' No. 1 Number- Kind Code'(lfknow

......, ;;;;;;;;;;..-I

NA 03114/2003 Ajay Janami Daga NA NA P1377

Application Number Flllna Date First Named Inventor Art Unit Examiner Name Attorney Docket Number

INFORMATION DISCLOSURE STATEMENT BY APPUCAN'f t

~c::::J

:;,en

Complet if Known

Substitute for form 1449A/PTO

<"L

oo::t"'

en - • .....-4

·H

I Considered Date

'EXAMINER: Initial if reference considered, whether or not citation is in conformance with MPEP 609. Draw line through citation if not in conformance and not considered. Include copy of this form with next communication to applicant. 1 Applicant's unique citation designation number (optional). 2 See Kinds Codes of USPTO Patent Documents at www.uspto.g!lV or MPEP 901.04. 3 Enter Office that issued the document, by the two-letter code (WIPO Standard ST.3). 4 For Japanese patent documents, the indication of the year of the reign of the Emperor must precede the serial number of the patent document. 5 Kind of document by the appropriate symbols as Indicated on the document under WIPO Standard ST. 16 if possible. 6 Applicant is to place a check mark here if English language Translation is attached. Burden Hour Statement: This form is estimated to take 2.0 hours to complete. Time will vary depending upon the needs of the individual case. Any comments on the amount of time you are required to complete this form should be sent to the Chief Information Officer, U.S. Patent and Trademark Office, Washington, DC 20231. DO NOT SEND FEES OR COMPLETED FORMS TO THIS ADDRESS. SEND TO: Assistant Commissioner for Patents, Washington, DC 20231.