Laboratory bench for verification
The final frontier of space exploration Integrated circuits need to withstand a harsh radiative environment if they are to function effectively in space. We spoke to Mr Daniel González about the work of the SEPHY project in designing and developing a new Ethernet transceiver device, work which will enhance European competitiveness in what is a fast-moving area. The harsh environment
of space places heavy demands on equipment, so equipment and components designed for use beyond the Earth’s atmosphere need to be correspondingly robust and reliable. Effective high-speed networking technologies are increasingly essential to modern space systems and the EU is keen to enhance the competitiveness of European companies in this area, a large part of the motivation behind the work of the SEPHY project. “The main goal of the initial funding call was to support the development of integrated circuits for space applications, enabling European countries to compete with components made in the US,” outlines Mr Daniel González, the coordinator of the project. The primary goal of the project is to develop an Ethernet transceiver device, enabling the wider adoption of Ethernet in space applications, including fully synchronous Time-Triggered Ethernet communication, which was developed by Austrian company TTTech, a key partner in the SEPHY consortium.
Protocol stack A large proportion of the key elements of the overall protocol stack for both regular (‘eventdriven’) and scheduled (‘Time-Triggered’) Ethernet has been developed, with only the
physical layer remaining, the part which enables the transmission and reception of packets of information through a cable. This is what Mr González and his colleagues from both the academic and commercial sectors are designing in the project, taking into account the challenges of the space environment. “In order to be used in space, integrated circuits need to be designed in such a way that they can withstand the radiation that they will
robust and reliable. This approach makes them more suitable for use in space. “This is related to radiation hardening by process,” outlines Mr González. The other method is radiation hardening by design, which means that special features or counter-measures are added in the design process, so that the chip will ultimately be able to withstand the radiation levels found in space; both these methods are being used in the SEPHY project.
In order to be used in space, integrated circuits need to be designed in such a way that they can withstand the radiation that they will be exposed to. be exposed to,” he says. There are two main ways in which a chip can be prepared, or hardened, for use in space; the first is called radiation hardening by process. “This means that the process by which the chip is built has some features that make it well-suited to fabricating integrated circuits for space applications. By process, that means all of the fabrication steps required to fabricate a given integrated circuit,” says Mr González. These integrated circuits are built on silicon wafers, the manufacturing of which can be adapted in such a way that they are more
“The process that we are using to fabricate this ASIC (Application-Specific Integrated Circuit) is offered by Microchip Technology Nantes. It’s a SOI (Silicon Over an Insulator) process, which gives full protection against a space radiation effect called Single Event Latchup (SEL), which can cause serious damage,” continues Mr González. “This SOI protects our circuit against SEL, one of the destructive events that can affect a circuit in space.” There are also several other radiation effects to consider, one of which is Total
Ionisation Dose (TID). This relates to the presence of trapped charges, which can cause the transistors in a circuit to behave differently over time. “The greater the radiation dose, the more the transistors – the building blocks of every circuit – will degrade,” explains Mr González. Researchers aim to protect the device against this effect as well as others, including other Single Event Effects (SEEs), aside from SEL, which was previously presented. “For example, Single Event Transients (SETs) and Single Event Upsets (SEUs) can change the state of some of the circuit blocks,” outlines Mr González. “The SEUs affect storage elements of a device. So, when a device is storing a 0 or a 1 as value, it flips the content of this memory – so it turns a 0 into a 1, and vice versa. Meanwhile, SETs are spikes produced on the signals that are driven inside the circuit.” The transceiver is designed to withstand these types of effects, either by process or design, achieving the radiation hardening required for space operations. The specifications have been developed in collaboration with the project’s industrial partners, including several deeply involved in the space industry, who are also playing a key role in testing the circuits. “They are looking to check if the chip behaves as expected electrically, and they are also assessing its performance under radiation conditions,” says Mr González. While there are several options in terms of sites where the chips could be tested for TID, there are less facilities available for heavy ion testing. “The chips will be radiated with the levels that we are expecting the chips to be exposed to when they are applied in space,” continues Mr González. “We will see how well the chips can withstand these radiation levels.”
A first preliminary prototype has already been designed and fabricated, from which invaluable insights were gained into the improvements and modifications required, and a second chip is currently in the process of fabrication. A great deal of progress has been made over the course of the project, and in future Mr González expects to move towards developing a full prototype of the Ethernet device. “The goal of this project was not to get a qualified component, but we hope to have a very good prototype of this Ethernet device within the next year or so,” he says. The transceiver could be relevant to several industrial sectors away from the space market, yet the initial motivation in funding the project was to reduce European dependence on US components, so Mr González is keen to stress that the space
SEPHY test chip 1 with specific carrier.
Consortium meeting in Vienna (from left to right): Úrsula Gutierro (ARQ), Daniel González (ARQ), Jesús López (ARQ), Anselm Breitenreiter (IHP), Jean-Marc Vrignaud (ATM), Ulrich Zurek (ATM), Remy Charavel (EC project officer), Christian Fidi (TTT), Artiza Elosegui (TTT), Matthias Mäke-Kail (TTT), Manuel Sánchez (TASE), Pedro Reviriego (UAN), Anna Ryabokon taking photo (TTT).
SEPHY SPACE ETHERNET PHYSICAL LAYER TRANSCEIVER
The SEPHY project aims to develop an ITARfree and radiation hardened 10/100-base-T Ethernet transceiver (PHY), which can be used worldwide. The project will foster innovation by developing a new space market device, which will reduce European dependence on imports, as it is designed and manufactured with European flows and processes.
This project has been funded under the EU Horizon 2020 COMPET 2014 Enabling European competitiveness, non-dependence and innovation of the European space sector (grant agreement No. 640243).
• Arquimea Ingeneria SLU – Madrid, Spain •M icrochip Technology Nantes – Nantes, France • T TTech Computertechnik AG – Vienna, Austria • Thales Alenia Space – Madrid, Spain • Universitas Nebrissensis – Madrid, Spain • IHP – Frankfurt (Oder), Germany
Project Coordinator, Mr Daniel González CTO ARQUIMEA INGENIERIA S.L.U. C/Margarita Salas, 10 28919, Leganés, Madrid, SPAIN T: +34 91 689 80 94 E: firstname.lastname@example.org W: http://www.sephy.eu/ SEPHY leaflet: http://sephy.eu/leaflet/ SEPHY flyer: http://sephy.eu/flyer/
Mr Daniel González Gutiérrez
Mr Daniel González Gutiérrez received his M.Sc in Telecommunication Engineering from the Technical University of Madrid and is currently working in ARQUIMEA as CTO managing the operations of the company and was previously leading the microelectronics group. Before joining ARQUIMEA Daniel worked for more than ten years in other companies and institutions of the space and consumer microelectronics sectors.
Consortium meeting in Nantes (from left to right): Christophe Guerif (MTN), Pedro Reviriego (UAN), Manuel Sánchez (TASE), Christoph Larndorfer (TTT), Jean-Marc Vrignaud (MTN), Úrsula Gutierro (ARQ), Jesús López (ARQ), Anna Ryabokon (TTT), Anselm Breitenreiter (IHP), Ulrich Zurek (MTN), Yuanqing Li (IHP).
market is the priority. “The technology could be used outside the space sector, but the focus is really on getting the transceiver used in space applications,” he outlines. The project’s work has already attracted a lot of interest from the commercial sector, and so far three non-disclosure agreements (NDAs) have been signed with candidate users of the technology. One area of interest in this respect is launchers, rockets that are used to launch satellites into space. “The lifetime of these rockets is not long – they are launched, and within a few hours they release the equipment into space. The radiation specifications for these launchers are somewhere between those of the commercial world and the space world,” outlines Mr Gonzalez. Research is centred around developing the Ethernet device however, rather than qualifying it for use in space applications, and Mr González says that remains the focus of his attention. “The outcome of the project will be a chip which is
ready to move on to the qualification phase, with a small re-design if necessary, with updates on areas that need to be improved,” he outlines. This work holds clear importance to the wider European space industry. While Europe is home to great scientific expertise, it’s essential to maintain a strong research base if European companies are to remain competitive in a rapidly changing market. “Europe is trying to get components in the market that are manufactured and designed within Europe, to reduce our dependency on parts from the US,” says Mr González. The SEPHY project has an important role to play in these terms, helping to foster innovation and building on Europe’s position as a leader in the field, which in turn will bring benefits to the wider economy. “We’re working with the major European space companies. They typically lead the development of satellites, and hold a lot of expertise on space infrastructures,” continues Mr González.
SEPHY Test chip 2 final layout.
SEPHY Test chip 2 on a frame.